1 /* 2 * Copyright (c) 1988, 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)esp.c 8.2 (Berkeley) 12/14/93 17 * 18 * from: $Header: esp.c,v 1.28 93/04/27 14:40:44 torek Exp $ (LBL) 19 * 20 * Loosely derived from Mary Baker's devSCSIC90.c from the Berkeley 21 * Sprite project, which is: 22 * 23 * Copyright 1988 Regents of the University of California 24 * Permission to use, copy, modify, and distribute this 25 * software and its documentation for any purpose and without 26 * fee is hereby granted, provided that the above copyright 27 * notice appear in all copies. The University of California 28 * makes no representations about the suitability of this 29 * software for any purpose. It is provided "as is" without 30 * express or implied warranty. 31 * 32 * from /sprite/src/kernel/dev/sun4c.md/RCS/devSCSIC90.c,v 1.4 33 * 90/12/19 12:37:58 mgbaker Exp $ SPRITE (Berkeley) 34 */ 35 36 /* 37 * Sbus ESP/DMA driver. A single driver must be used for both devices 38 * as they are physically tied to each other: The DMA chip can only 39 * be used to assist ESP SCSI transactions; the ESP interrupt enable is 40 * in the DMA chip csr. 41 * 42 * Since DMA and SCSI interrupts are handled in the same routine, the 43 * DMA device does not declare itself as an sbus device. This saves 44 * some space. 45 */ 46 47 #include <sys/param.h> 48 #include <sys/buf.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 52 #include <dev/scsi/scsi.h> 53 #include <dev/scsi/scsivar.h> 54 55 #include <machine/autoconf.h> 56 #include <machine/cpu.h> 57 58 #include <sparc/sbus/dmareg.h> 59 #define ESP_PHASE_NAMES 60 #include <sparc/sbus/espreg.h> 61 #include <sparc/sbus/sbusvar.h> 62 63 #include <libkern/libkern.h> 64 65 /* 66 * This driver is largely a giant state machine: 67 * 68 * Given some previous SCSI state (as set up or tracked by us 69 * earlier) and the interrupt registers provided on the chips 70 * (dmacsr, espstat, espstep, and espintr), derive an action. 71 * In many cases this is just a matter of reading the target's 72 * phase and following its orders, which sets a new state. 73 * 74 * This sequencing is done in espact(); the state is primed in espselect(). 75 * 76 * Data transfer is always done via DMA. Unfortunately, there are 77 * limits in the DMA and ESP chips on how much data can be moved 78 * in a single operation. The ESP chip has a 16-bit counter, so 79 * it is limited to 65536 bytes. More insidiously, while the DMA 80 * chip has a 32-bit address, this is composed of a 24-bit counter 81 * with an 8-bit latch, so it cannot cross a 16 MB boundary. To 82 * handle these, we program a smaller count than our caller requests; 83 * when this shorter transfer is done, if the target is still up 84 * for data transfer, we simply keep going (updating the DMA address) 85 * as needed. 86 * 87 * Another state bit is used to recover from bus resets: 88 * 89 * A single TEST UNIT READY is attempted on each target before any 90 * real communication begins; this TEST UNIT READY is allowed to 91 * fail in any way. This is required for the Quantum ProDrive 100 92 * MB disks, for instance, which respond to their first selection 93 * with status phase, and for anything that insists on implementing 94 * the broken SCSI-2 synch transfer initial message. 95 * 96 * This is done in espclear() (which calls espselect(); functions that 97 * call espselect() must check for clearing first). 98 * 99 * The state machines actually intermingle, as some SCSI sequences are 100 * only allowed during clearing. 101 */ 102 103 /* per-DMA variables */ 104 struct dma_softc { 105 struct device dc_dev; /* base device */ 106 volatile struct dmareg *dc_dma; /* register virtual address */ 107 int dc_dmarev; /* revision */ 108 char *dc_dmafmt; /* format for error messages */ 109 }; 110 void dmaattach(struct device *, struct device *, void *); 111 struct cfdriver dmacd = 112 { NULL, "dma", matchbyname, dmaattach, DV_DULL, sizeof(struct dma_softc) }; 113 114 /* per-ESP variables */ 115 struct esp_softc { 116 /* 117 * External interfaces. 118 */ 119 struct hba_softc sc_hba; /* base device + hba, must be first */ 120 #define sc_dev sc_hba.hba_dev 121 struct sbusdev sc_sd; /* sbus device */ 122 struct intrhand sc_ih; /* interrupt entry */ 123 struct evcnt sc_intrcnt; /* interrupt counter */ 124 struct dma_softc *sc_dc; /* pointer to corresponding dma sc */ 125 126 /* 127 * Addresses mapped to hardware registers. 128 */ 129 volatile struct espreg *sc_esp; 130 volatile struct dmareg *sc_dma; 131 132 /* 133 * Copies of registers cleared/unlatched by reading. 134 * (FIFO flags is not cleared, but we want it for debugging.) 135 */ 136 u_long sc_dmacsr; 137 u_char sc_espstat; 138 u_char sc_espstep; 139 u_char sc_espintr; 140 u_char sc_espfflags; 141 142 /* miscellaneous */ 143 int sc_clockfreq; /* clock frequency */ 144 u_char sc_sel_timeout; /* select timeout */ 145 u_char sc_id; /* initiator ID (default = 7) */ 146 u_char sc_needclear; /* uncleared targets (1 bit each) */ 147 u_char sc_esptype; /* 100, 100A, 2xx (see below) */ 148 u_char sc_ccf; /* clock conversion factor */ 149 u_char sc_conf1; /* value for config reg 1 */ 150 u_char sc_conf2; /* value for config reg 2 */ 151 u_char sc_conf3; /* value for config reg 3 */ 152 struct bootpath *sc_bp; /* esp bootpath so far */ 153 154 /* 155 * Information pertaining to the current transfer, 156 * including sequencing. 157 * 158 * The size of sc_msg is the size of the ESP fifo, 159 * since we do message-in simply by allowing the fifo to fill. 160 */ 161 char sc_probing; /* used during autoconf; see below */ 162 char sc_clearing; /* true => cmd is just to clear targ */ 163 char sc_state; /* SCSI protocol state; see below */ 164 char sc_sentcmd; /* set once we get cmd out */ 165 char sc_dmaactive; /* true => doing dma */ 166 #ifdef notyet 167 u_char sc_sync; /* synchronous transfer stuff (?) */ 168 #endif 169 u_char sc_stat[2]; /* status from last `status' phase */ 170 u_char sc_msg[16]; /* message from device */ 171 u_short sc_dmactl; /* control to load into dma csr */ 172 u_long sc_dmaaddr; /* address for next xfer */ 173 int sc_dmasize; /* size of current xfer */ 174 int sc_resid; /* count of bytes not yet xferred */ 175 int sc_targ; /* the target involved */ 176 struct scsi_cdb *sc_curcdb; /* ptr to current command */ 177 /* might cdbspace eventually be per-target? */ 178 struct scsi_cdb sc_cdbspace; /* space for one command */ 179 }; 180 181 /* 182 * Values for sc_esptype (used to control configuration reset, and for 183 * workarounds for chip bugs). The order is important; see espreset(). 184 */ 185 #define ESP100 0 186 #define ESP100A 1 187 #define ESP2XX 2 188 189 /* 190 * Probe state. 0 means not probing. While looking for each target 191 * we set this to PROBE_TESTING and do a TEST UNIT READY on unit 0. 192 * If selection fails, this is changed to PROBE_NO_TARGET; otherwise 193 * we assume the target exists, regardless of the result of the test. 194 */ 195 #define PROBE_TESTING 1 196 #define PROBE_NO_TARGET 2 197 198 /* 199 * States in sc_state. 200 * 201 * Note that S_SVC is rare: normally we load the SCSI command into the 202 * ESP fifo and get interrupted only when the device has gone to data 203 * or status phase. If the device wants to play games, though, we end 204 * up doing things differently. 205 */ 206 char *espstates[] = { 207 #define S_IDLE 0 /* not doing anything */ 208 "idle", 209 #define S_SEL 1 /* expecting select done interrupt */ 210 "selecting", 211 #define S_SVC 2 /* expecting service req interrupt */ 212 "waiting for svc req", 213 #define S_DI 3 /* expecting data-in done interrupt */ 214 "receiving data", 215 #define S_DO 4 /* expecting data-out done interrupt */ 216 "sending data", 217 #define S_STAT 5 /* expecting status done interrupt */ 218 "receiving status", 219 #define S_MI 6 /* expecting message-in done interrupt */ 220 "receiving message", 221 #define S_FI 7 /* expecting final disconnect interrupt */ 222 "waiting for disconnect" 223 }; 224 225 /* 226 * Hardware limits on transfer sizes (see comments at top). 227 */ 228 #define ESPMAX (64 * 1024) 229 #define DMAMAX(a) (0x01000000 - ((a) & 0x00ffffff)) 230 231 /* 232 * Return values from espact(). 233 */ 234 #define ACT_CONT 0 /* espact() handled everything */ 235 #define ACT_IO 1 /* espact() is xferring data */ 236 #define ACT_DONE 2 /* handled everything, and op is now done */ 237 #define ACT_ERROR 3 /* an error occurred, op has been trashed */ 238 #define ACT_RESET 4 /* please reset ESP, then do ACT_ERROR */ 239 #define ACT_QUICKINTR 5 /* another interrupt is expected immediately */ 240 241 /* autoconfiguration driver */ 242 void espattach(struct device *, struct device *, void *); 243 struct cfdriver espcd = 244 { NULL, "esp", matchbyname, espattach, DV_DULL, sizeof(struct esp_softc), 245 "intr" }; 246 247 /* Sbus driver */ 248 void espsbreset(struct device *); 249 250 /* interrupt interface */ 251 int espintr(void *); 252 253 /* SCSI HBA driver */ 254 int espicmd(struct hba_softc *, int, struct scsi_cdb *, caddr_t, int, int); 255 int espdump(struct hba_softc *, int, struct scsi_cdb *, caddr_t, int); 256 void espstart(struct device *, struct sq *, struct buf *, 257 scdgo_fn, struct device *); 258 int espgo(struct device *, int, scintr_fn, struct device *, 259 struct buf *, int); 260 void esprel(struct device *); 261 void esphbareset(struct hba_softc *, int); 262 static struct hbadriver esphbadriver = 263 { espicmd, espdump, espstart, espgo, esprel, esphbareset }; 264 265 /* other prototypes */ 266 static void espdoattach(int); 267 static void dmareset(struct esp_softc *); 268 static void espreset(struct esp_softc *, int); 269 static void esperror(struct esp_softc *, const char *); 270 static int espact(struct esp_softc *); 271 void espselect(struct esp_softc *, int, struct scsi_cdb *); 272 273 /* second arg to espreset() */ 274 #define RESET_ESPCHIP 0x1 275 #define RESET_SCSIBUS 0x2 276 #define RESET_BOTH (RESET_ESPCHIP | RESET_SCSIBUS) 277 278 /* 279 * Attach a found DMA chip. 280 * The second argument is really a pointer to an sbus_attach_args. 281 */ 282 void 283 dmaattach(parent, dev, args) 284 struct device *parent; 285 struct device *dev; 286 void *args; 287 { 288 register struct dma_softc *dc = (struct dma_softc *)dev; 289 register struct sbus_attach_args *sa = args; 290 register volatile struct dmareg *dma; 291 register int rev; 292 struct esp_softc *esc; 293 294 if (sa->sa_ra.ra_vaddr) 295 dma = (volatile struct dmareg *)sa->sa_ra.ra_vaddr; 296 else 297 dma = (volatile struct dmareg *) 298 mapiodev(sa->sa_ra.ra_paddr, sizeof(struct dmareg)); 299 dc->dc_dma = dma; 300 301 switch (rev = DMA_REV(dma->dma_csr)) { 302 case DMAREV_1: 303 printf(": rev 1\n"); 304 dc->dc_dmafmt = DMA_REV1_BITS; 305 break; 306 case DMAREV_2: 307 printf(": rev 2\n"); 308 dc->dc_dmafmt = DMA_REV2_BITS; 309 break; 310 case DMAREV_3: 311 printf(": rev 3\n"); 312 printf("WARNING: esp.c not yet updated for rev 3\n"); 313 dc->dc_dmafmt = DMA_REV3_BITS; 314 break; 315 default: 316 printf(": unknown revision code 0x%x\n", rev); 317 dc->dc_dmafmt = DMA_REV3_BITS; /* cross fingers */ 318 break; 319 } 320 dc->dc_dmarev = rev; 321 espdoattach(dc->dc_dev.dv_unit); 322 } 323 324 /* 325 * Attach a found ESP chip. Search for targets; attach each one found. 326 * The latter must be deferred if the corresponding dma chip has not yet 327 * been configured. 328 */ 329 void 330 espattach(parent, self, args) 331 struct device *parent; 332 struct device *self; 333 void *args; 334 { 335 register struct esp_softc *sc = (struct esp_softc *)self; 336 register struct sbus_attach_args *sa = args; 337 register volatile struct espreg *esp; 338 register struct bootpath *bp; 339 int node, pri, freq, t; 340 341 if (sa->sa_ra.ra_nintr != 1) { 342 printf(": expected 1 interrupt, got %d\n", sa->sa_ra.ra_nintr); 343 return; 344 } 345 pri = sa->sa_ra.ra_intr[0].int_pri; 346 printf(" pri %d", pri); 347 if (sa->sa_ra.ra_vaddr) 348 esp = (volatile struct espreg *)sa->sa_ra.ra_vaddr; 349 else 350 esp = (volatile struct espreg *) 351 mapiodev(sa->sa_ra.ra_paddr, sizeof(struct espreg)); 352 sc->sc_esp = esp; 353 node = sa->sa_ra.ra_node; 354 sc->sc_id = getpropint(node, "initiator-id", 7); 355 freq = getpropint(node, "clock-frequency", -1); 356 if (freq < 0) 357 freq = 358 ((struct sbus_softc *)sc->sc_dev.dv_parent)->sc_clockfreq; 359 360 /* MIGHT NEED TO RESET ESP CHIP HERE ...? */ 361 362 /* 363 * Find out whether we have a -100, -100A, or -2xx, 364 * and what speed it runs at. 365 */ 366 sc->sc_conf1 = sc->sc_id | ESPCONF1_PARENB; 367 /* sc->sc_conf2 = 0; */ 368 /* sc->sc_conf3 = 0; */ 369 esp->esp_conf1 = sc->sc_conf1; 370 esp->esp_conf2 = 0; 371 esp->esp_conf2 = ESPCONF2_SCSI2 | ESPCONF2_RPE; 372 if ((esp->esp_conf2 & ~ESPCONF2_RSVD) != 373 (ESPCONF2_SCSI2 | ESPCONF2_RPE)) { 374 printf(": ESP100"); 375 sc->sc_esptype = ESP100; 376 } else { 377 esp->esp_conf2 = 0; 378 esp->esp_conf3 = 0; 379 esp->esp_conf3 = 5; 380 if (esp->esp_conf3 != 5) { /* XXX def bits */ 381 printf(": ESP100A"); 382 sc->sc_esptype = ESP100A; 383 } else { 384 esp->esp_conf3 = 0; 385 printf(": ESP2XX"); 386 sc->sc_esptype = ESP2XX; 387 } 388 } 389 printf(", clock = %s MHz, ID = %d\n", clockfreq(freq), sc->sc_id); 390 391 /* 392 * Set clock conversion factor and select timeout. 393 * N.B.: clock frequency is not actually used in the rest 394 * of the driver; I calculate it here for completeness only 395 * (so I can see it when debugging). 396 */ 397 sc->sc_clockfreq = freq; 398 freq = howmany(freq, 1000 * 1000); /* convert to MHz */ 399 t = ESPCCF_FROMMHZ(freq); 400 if (t < ESPCCF_MIN) 401 t = ESPCCF_MIN; 402 sc->sc_ccf = t; 403 t = ESPTIMO_REGVAL(250, t, freq); /* timeout = 250 ms. */ 404 if (t >= 256) 405 t = 0; 406 sc->sc_sel_timeout = t; 407 408 /* 409 * Link into sbus; set interrupt handler. 410 */ 411 sc->sc_sd.sd_reset = espsbreset; 412 sbus_establish(&sc->sc_sd, &sc->sc_dev); 413 sc->sc_ih.ih_fun = espintr; 414 sc->sc_ih.ih_arg = sc; 415 intr_establish(pri, &sc->sc_ih); 416 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 417 418 #define SAME_ESP(bp, sa) \ 419 ((bp->val[0] == sa->sa_slot && bp->val[1] == sa->sa_offset) || \ 420 (bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit)) 421 422 bp = sa->sa_ra.ra_bp; 423 if (bp != NULL && strcmp(bp->name, "esp") == 0 && SAME_ESP(bp, sa)) 424 sc->sc_bp = bp + 1; 425 espdoattach(sc->sc_dev.dv_unit); 426 } 427 428 /* 429 * `Final' attach of esp occurs once esp and dma chips have been found 430 * and assigned virtual addresses. Set up the ESP SCSI data structures 431 * and probe the SCSI bus. 432 */ 433 static void 434 espdoattach(unit) 435 int unit; 436 { 437 register struct esp_softc *sc; 438 register struct dma_softc *dc; 439 register struct bootpath *bp; 440 register struct targ *t; 441 register int targ, u; 442 443 /* make sure we have both */ 444 if (espcd.cd_ndevs <= unit || 445 dmacd.cd_ndevs <= unit || 446 (sc = espcd.cd_devs[unit]) == NULL || 447 (dc = dmacd.cd_devs[unit]) == NULL) 448 return; 449 sc->sc_dc = dc; 450 sc->sc_dma = dc->dc_dma; 451 sc->sc_hba.hba_driver = &esphbadriver; 452 453 sc->sc_dma->dma_csr = 0; /* ??? */ 454 espreset(sc, RESET_ESPCHIP); 455 456 /* MAYBE THIS SHOULD BE MOVED TO scsi_subr.c? */ 457 for (targ = 0; targ < 8; targ++) { 458 if (targ == sc->sc_id) 459 continue; 460 sc->sc_probing = PROBE_TESTING; 461 sc->sc_clearing = 1; 462 (void)scsi_test_unit_ready(&sc->sc_hba, targ, 0); 463 if (sc->sc_probing != PROBE_NO_TARGET) { 464 sc->sc_probing = 0; 465 sc->sc_clearing = 0; 466 SCSI_FOUNDTARGET(&sc->sc_hba, targ); 467 } 468 } 469 sc->sc_probing = 0; 470 sc->sc_clearing = 0; 471 472 /* 473 * See if we booted from a unit on this target. We could 474 * compare bp->name against the unit's name but there's no 475 * real need since a target and unit uniquely specify a 476 * scsi device. 477 */ 478 if ((bp = sc->sc_bp) != NULL && (u_int)(targ = bp->val[0]) < 8 && 479 (u_int)(u = bp->val[1]) < 8 && 480 (t = sc->sc_hba.hba_targets[targ]) != NULL && t->t_units[u] != NULL) 481 bootdv = t->t_units[u]->u_dev; 482 } 483 484 /* 485 * We are not allowed to touch the DMA "flush" and "drain" bits 486 * while it is still thinking about a request (DMA_RP). 487 */ 488 #define DMAWAIT(dma) while ((dma)->dma_csr & DMA_RP) DELAY(1) 489 490 /* 491 * Reset the DMA chip. 492 */ 493 static void 494 dmareset(sc) 495 struct esp_softc *sc; 496 { 497 register volatile struct dmareg *dma = sc->sc_dma; 498 499 DMAWAIT(dma); 500 dma->dma_csr |= DMA_RESET; 501 DELAY(200); 502 dma->dma_csr &= ~DMA_RESET; /* ??? */ 503 sc->sc_state = S_IDLE; 504 sc->sc_dmaactive = 0; 505 if (sc->sc_dc->dc_dmarev == DMAREV_2 && sc->sc_esptype != ESP100) 506 dma->dma_csr |= DMA_TURBO; 507 dma->dma_csr |= DMA_IE; /* enable interrupts */ 508 DELAY(200); 509 } 510 511 /* 512 * Reset the chip and/or SCSI bus (always resets DMA). 513 */ 514 static void 515 espreset(sc, how) 516 register struct esp_softc *sc; 517 int how; 518 { 519 register volatile struct espreg *esp = sc->sc_esp; 520 521 dmareset(sc); 522 if (how & RESET_ESPCHIP) { 523 esp->esp_cmd = ESPCMD_RESET_CHIP; 524 esp->esp_cmd = ESPCMD_NOP; 525 /* 526 * Reload configuration registers (cleared by 527 * RESET_CHIP command). Reloading conf2 on an 528 * ESP100 goofs it up, so out of paranoia we load 529 * only the registers that exist. 530 */ 531 esp->esp_conf1 = sc->sc_conf1; 532 if (sc->sc_esptype > ESP100) { /* 100A, 2XX */ 533 esp->esp_conf2 = sc->sc_conf2; 534 if (sc->sc_esptype > ESP100A) /* 2XX only */ 535 esp->esp_conf3 = sc->sc_conf3; 536 } 537 esp->esp_ccf = sc->sc_ccf; 538 esp->esp_timeout = sc->sc_sel_timeout; 539 /* We set synch offset later. */ 540 } 541 if (how & RESET_SCSIBUS) { 542 /* 543 * The chip should retain most of its parameters 544 * (including esp_ccf) across this kind of reset 545 * (see section 3.5 of Emulex documentation). 546 */ 547 /* turn off scsi bus reset interrupts and reset scsi bus */ 548 esp->esp_conf1 = sc->sc_conf1 | ESPCONF1_REPORT; 549 esp->esp_cmd = ESPCMD_RESET_BUS; 550 esp->esp_cmd = ESPCMD_NOP; 551 DELAY(100000); /* ??? */ 552 (void)esp->esp_intr; 553 esp->esp_conf1 = sc->sc_conf1; 554 } 555 556 sc->sc_needclear = 0xff; 557 } 558 559 /* 560 * Reset the SCSI bus and, optionally, all attached targets. 561 */ 562 void 563 esphbareset(hba, resetunits) 564 struct hba_softc *hba; 565 int resetunits; 566 { 567 register struct esp_softc *sc = (struct esp_softc *)hba; 568 569 espreset(sc, RESET_SCSIBUS); 570 if (resetunits) 571 scsi_reset_units(&sc->sc_hba); 572 } 573 574 /* 575 * Reset the esp, after an Sbus reset. 576 * Also resets corresponding dma chip. 577 * 578 * THIS ROUTINE MIGHT GO AWAY 579 */ 580 void 581 espsbreset(dev) 582 struct device *dev; 583 { 584 struct esp_softc *sc = (struct esp_softc *)dev; 585 586 if (sc->sc_dc) { 587 printf(" %s %s", sc->sc_dc->dc_dev.dv_xname, 588 sc->sc_dev.dv_xname); 589 esphbareset(&sc->sc_hba, 1); 590 } 591 } 592 593 /* 594 * Log an error. 595 */ 596 static void 597 esperror(sc, err) 598 register struct esp_softc *sc; 599 const char *err; 600 { 601 int stat; 602 603 stat = sc->sc_espstat; 604 printf( 605 "%s target %d cmd 0x%x (%s): %s:\n\ 606 \tstat=%b (%s) step=%x dmacsr=%b fflags=%x intr=%b\n", 607 sc->sc_dev.dv_xname, sc->sc_targ, sc->sc_curcdb->cdb_bytes[0], 608 espstates[sc->sc_state], err, 609 stat, ESPSTAT_BITS, espphases[stat & ESPSTAT_PHASE], 610 sc->sc_espstep, sc->sc_dmacsr, sc->sc_dc->dc_dmafmt, 611 sc->sc_espfflags, sc->sc_espintr, ESPINTR_BITS); 612 } 613 614 /* 615 * Issue a select, loading command into the FIFO. 616 * Return nonzero on error, 0 if OK. 617 * Sets state to `selecting'; espact() will sequence state FSM. 618 */ 619 void 620 espselect(sc, targ, cdb) 621 register struct esp_softc *sc; 622 register int targ; 623 register struct scsi_cdb *cdb; 624 { 625 register volatile struct espreg *esp; 626 register int i, cmdlen; 627 628 sc->sc_targ = targ; 629 sc->sc_state = S_SEL; 630 sc->sc_curcdb = cdb; 631 sc->sc_sentcmd = 0; 632 sc->sc_stat[0] = 0xff; /* ??? */ 633 sc->sc_msg[0] = 0xff; /* ??? */ 634 635 /* 636 * Try to talk to target. 637 * Synch offset 0 => asynchronous transfer. 638 */ 639 esp = sc->sc_esp; 640 esp->esp_id = targ; 641 esp->esp_syncoff = 0; 642 643 /* 644 * Stuff the command bytes into the fifo. 645 * Select without attention since we do not do disconnect yet. 646 */ 647 cmdlen = SCSICMDLEN(cdb->cdb_bytes[0]); 648 for (i = 0; i < cmdlen; i++) 649 esp->esp_fifo = cdb->cdb_bytes[i]; 650 esp->esp_cmd = ESPCMD_SEL_NATN; 651 /* the rest is done elsewhere */ 652 } 653 654 /* 655 * Sequence through the SCSI state machine. Return the action to take. 656 * 657 * Most of the work happens here. 658 * 659 * There are three interrupt sources: 660 * -- ESP interrupt request (typically, some device wants something). 661 * -- DMA memory error. 662 * -- DMA byte count has reached 0 (we do not often want this one but 663 * can only turn it off in rev 2 DMA chips, it seems). 664 * DOES THIS OCCUR AT ALL HERE? THERE IS NOTHING TO HANDLE IT! 665 */ 666 static int 667 espact(sc) 668 register struct esp_softc *sc; 669 { 670 register volatile struct espreg *esp; 671 register volatile struct dmareg *dma; 672 register int reg, i, resid, newstate; 673 register struct scsi_cdb *cdb; 674 675 dma = sc->sc_dma; 676 /* check various error conditions, using as little code as possible */ 677 if (sc->sc_dmacsr & DMA_EP) { 678 esperror(sc, "DMA error"); 679 DMAWAIT(dma); 680 dma->dma_csr |= DMA_FLUSH; 681 return (ACT_ERROR); 682 } 683 reg = sc->sc_espstat; 684 if (reg & ESPSTAT_GE) { 685 /* 686 * This often occurs when there is no target. 687 * (See DSC code below.) 688 */ 689 if (sc->sc_espintr & ESPINTR_DSC && 690 sc->sc_state == S_SEL && sc->sc_probing) { 691 sc->sc_probing = PROBE_NO_TARGET; 692 return (ACT_RESET); 693 } 694 esperror(sc, "DIAG: gross error (ignored)"); 695 } 696 if (reg & ESPSTAT_PE) { 697 esperror(sc, "parity error"); 698 return (ACT_RESET); 699 } 700 reg = sc->sc_espintr; 701 #define ERR (ESPINTR_SBR|ESPINTR_ILC|ESPINTR_RSL|ESPINTR_SAT|ESPINTR_SEL) 702 if (reg & ERR) { 703 if (reg & ESPINTR_SBR) 704 esperror(sc, "scsi bus reset"); 705 else if (reg & ESPINTR_ILC) 706 esperror(sc, "illegal command (driver bug)"); 707 else { 708 printf("%s: target %d", sc->sc_dev.dv_xname, 709 sc->sc_targ); 710 if (reg & ESPINTR_RSL) 711 printf(" tried to reselect;"); 712 if (reg & ESPINTR_SAT) 713 printf(" selected with ATN;"); 714 if (reg & ESPINTR_SEL) 715 printf(" selected us as target;"); 716 printf("we do not allow this yet\n"); 717 } 718 return (ACT_ERROR); 719 } 720 #undef ERR 721 722 esp = sc->sc_esp; 723 724 /* 725 * Disconnect currently only allowed in `final interrupt' states. 726 */ 727 if (reg & ESPINTR_DSC) { 728 if (sc->sc_state == S_FI) 729 return (ACT_DONE); 730 /* 731 * If we were doing a select just to test the existence 732 * of the target, note that it did not respond; otherwise 733 * gripe. 734 */ 735 if (sc->sc_state == S_SEL) { 736 if (sc->sc_probing) { 737 sc->sc_probing = PROBE_NO_TARGET; 738 return (ACT_RESET); 739 } 740 } 741 /* flush fifo, in case we were selecting or sending data */ 742 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 743 DELAY(1); 744 printf("%s: target %d not responding\n", 745 sc->sc_dev.dv_xname, sc->sc_targ); 746 return (ACT_ERROR); 747 } 748 749 /* 750 * Okay, things are moving along. 751 * What were we doing the last time we did something, 752 * and did it complete normally? 753 */ 754 switch (sc->sc_state) { 755 756 case S_SEL: 757 /* 758 * We were selecting. Arbitration and select are 759 * complete (because ESPINTR_DSC was not set), but 760 * there is no guarantee the command went out. 761 */ 762 if ((reg & (ESPINTR_SVC|ESPINTR_CMP)) != 763 (ESPINTR_SVC|ESPINTR_CMP)) { 764 esperror(sc, "selection failed"); 765 return (ACT_RESET); 766 } 767 if (sc->sc_espstep == ESPSTEP_DONE) { 768 sc->sc_sentcmd = 1; 769 break; 770 } 771 if (sc->sc_espstep == 2) { 772 /* 773 * We got something other than command phase. 774 * Just pretend things are normal; the 775 * device will ask for the command later. 776 */ 777 esperror(sc, "DIAG: esp step 2"); 778 } else if (sc->sc_espstep == 3) { 779 /* 780 * Device entered command phase and then exited it 781 * before we finished handing out the command. 782 * Let this happen iff we are trying to clear the 783 * target state. 784 */ 785 esperror(sc, "DIAG: esp step 3"); 786 if (!sc->sc_clearing) 787 return (ACT_RESET); 788 } else { 789 printf("%s: mysterious esp step %d\n", 790 sc->sc_dev.dv_xname, sc->sc_espstep); 791 return (ACT_RESET); 792 } 793 794 /* 795 * Part of the command may still be lodged in the FIFO. 796 */ 797 if (ESP_NFIFO(sc->sc_espfflags)) { 798 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 799 DELAY(1); 800 } 801 break; 802 803 case S_SVC: 804 /* 805 * We were waiting for phase change after stuffing the command 806 * into the FIFO. Make sure it got out. 807 */ 808 if (ESP_NFIFO(sc->sc_espfflags)) { 809 esperror(sc, "DIAG: CMDSVC, fifo not empty"); 810 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 811 DELAY(1); 812 } else 813 sc->sc_sentcmd = 1; 814 break; 815 816 case S_DI: 817 /* 818 * We were doing DMA data in, and expecting a 819 * transfer-count-zero interrupt or a phase change. 820 * We got that; drain the pack register and handle 821 * as for data out -- but ignore FIFO (it should be 822 * empty, except for sync mode which we are not 823 * using anyway). 824 */ 825 DMAWAIT(dma); 826 dma->dma_csr |= DMA_DRAIN; 827 DELAY(1); 828 resid = 0; 829 goto dma_data_done; 830 831 case S_DO: 832 /* 833 * We were doing DMA data out. If there is data in the 834 * FIFO, it is stuff that got DMAed out but never made 835 * it to the device, so it counts as residual. 836 */ 837 if ((resid = ESP_NFIFO(sc->sc_espfflags)) != 0) { 838 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 839 DELAY(1); 840 } 841 dma_data_done: 842 if (sc->sc_dmaactive == 0) { 843 esperror(sc, "dma done w/o dmaactive"); 844 panic("espact"); 845 } 846 sc->sc_dmaactive = 0; 847 848 /* Finish computing residual count. */ 849 reg = esp->esp_tcl | (esp->esp_tch << 8); 850 if (reg == 0 && (sc->sc_espstat & ESPSTAT_TC) == 0) 851 reg = 65536; 852 resid += reg; 853 854 /* Compute xfer count (requested - resid). */ 855 i = sc->sc_dmasize - resid; 856 if (i < 0) { 857 printf("%s: xfer resid (%d) > xfer req (%d)\n", 858 sc->sc_dev.dv_xname, resid, sc->sc_dmasize); 859 i = sc->sc_dmasize; /* forgiving... */ 860 } 861 862 /* If data came in we must flush cache. */ 863 if (sc->sc_state == S_DI) 864 cache_flush(sc->sc_dmaaddr, i); 865 sc->sc_dmaaddr += i; 866 sc->sc_resid -= i; 867 if ((sc->sc_espintr & ESPINTR_SVC) == 0) { 868 esperror(sc, "no bus service req"); 869 return (ACT_RESET); 870 } 871 break; 872 873 case S_STAT: 874 /* 875 * The last thing we did was tell it `initiator complete' 876 * and so we expect to have gotten both the status byte 877 * and the final message byte. It is possible that we 878 * got something else.... 879 * 880 * Apparently, BUS SERVICE is set if we got just status, 881 * while FUNCTION COMPLETE is set if we got both. 882 */ 883 if ((reg & (ESPINTR_SVC|ESPINTR_CMP)) != ESPINTR_CMP) { 884 esperror(sc, "bad status interrupt state"); 885 return (ACT_RESET); 886 } 887 reg = ESP_NFIFO(sc->sc_espfflags); 888 if (reg < 2) { 889 printf( 890 "%s: command done but fifo count = %d; must be >= 2\n", 891 sc->sc_dev.dv_xname, reg); 892 return (ACT_RESET); 893 } 894 /* 895 * Read the status and the first msg byte. 896 * It should be CMD_COMPLETE. Eventually we 897 * may handle IDENTIFY, DISCONNECT, etc., as well. 898 */ 899 sc->sc_stat[0] = esp->esp_fifo; 900 sc->sc_msg[0] = reg = esp->esp_fifo; 901 esp->esp_cmd = ESPCMD_MSG_ACCEPT; 902 if (reg == MSG_CMD_COMPLETE) { 903 sc->sc_state = S_FI; 904 return (ACT_CONT); 905 } 906 if (SCSIMSGLEN(reg) != 1) { 907 printf("%s: target %d is naughty\n", 908 sc->sc_dev.dv_xname, sc->sc_targ); 909 return (ACT_RESET); 910 } 911 printf("%s: warning: target %d returned msg 0x%x\n", 912 sc->sc_dev.dv_xname, sc->sc_targ, reg); 913 sc->sc_state = S_FI; 914 return (ACT_CONT); 915 916 case S_MI: 917 if ((reg & ESPINTR_SVC) == 0) { 918 esperror(sc, "missing phase after msg in"); 919 return (ACT_RESET); 920 } 921 reg = ESP_NFIFO(sc->sc_espfflags); 922 for (i = 0; i < reg; i++) 923 sc->sc_msg[i] = esp->esp_fifo; 924 break; 925 926 case S_FI: 927 esperror(sc, "target did not disconnect"); 928 return (ACT_RESET); 929 } 930 931 /* 932 * Things are still moving along. The phase tells us 933 * what the device wants next. Do it. 934 */ 935 switch (sc->sc_espstat & ESPSTAT_PHASE) { 936 937 case ESPPHASE_DATA_OUT: 938 if (!sc->sc_sentcmd) esperror(sc, "DIAG: data out without command"); 939 if (sc->sc_dmactl & DMA_READ) { 940 esperror(sc, "wrong phase (want to read)"); 941 return (ACT_RESET); 942 } 943 newstate = S_DO; 944 goto do_data_xfer; 945 946 case ESPPHASE_DATA_IN: 947 if (!sc->sc_sentcmd) esperror(sc, "DIAG: data in without command"); 948 if (!(sc->sc_dmactl & DMA_READ)) { 949 esperror(sc, "wrong phase (want to write)"); 950 return (ACT_RESET); 951 } 952 newstate = S_DI; 953 do_data_xfer: 954 if (sc->sc_resid == 0) { 955 esperror(sc, "data count error"); 956 return (ACT_RESET); 957 } 958 959 /* 960 * Compute DMA count based on chip limits. 961 * Set DMA address and load transfer count into 962 * ESP via DMA NOP, then set DMA control, and 963 * then we can start the DMA. 964 */ 965 sc->sc_state = newstate; 966 i = min(sc->sc_resid, ESPMAX); 967 i = min(i, DMAMAX(sc->sc_dmaaddr)); 968 sc->sc_dmasize = i; 969 dma->dma_addr = sc->sc_dmaaddr; 970 esp->esp_tch = i >> 8; 971 esp->esp_tcl = i; 972 esp->esp_cmd = ESPCMD_DMA | ESPCMD_NOP; 973 dma->dma_csr = sc->sc_dmactl; 974 sc->sc_dmaactive = 1; 975 esp->esp_cmd = ESPCMD_DMA | ESPCMD_XFER_INFO; 976 return (ACT_IO); 977 978 case ESPPHASE_CMD: 979 /* 980 * Silly thing wants the command again. 981 * Load it into the FIFO and go to SVC state. 982 */ 983 printf("%s: redoing command\n", sc->sc_dev.dv_xname); 984 cdb = sc->sc_curcdb; 985 reg = SCSICMDLEN(cdb->cdb_bytes[0]); 986 for (i = 0; i < reg; i++) 987 esp->esp_fifo = cdb->cdb_bytes[i]; 988 sc->sc_state = S_SVC; 989 esp->esp_cmd = ESPCMD_XFER_INFO; 990 return (ACT_CONT); 991 992 case ESPPHASE_STATUS: 993 sc->sc_state = S_STAT; 994 esp->esp_cmd = ESPCMD_INIT_COMP; 995 return (ACT_CONT); 996 997 case ESPPHASE_MSG_IN: 998 printf("%s: accepting (& ignoring) msg from target %d\n", 999 sc->sc_dev.dv_xname, sc->sc_targ); 1000 sc->sc_state = S_MI; 1001 esp->esp_cmd = ESPCMD_MSG_ACCEPT; 1002 return (ACT_CONT); 1003 1004 default: 1005 esperror(sc, "bad phase"); 1006 return (ACT_RESET); 1007 } 1008 /* NOTREACHED */ 1009 } 1010 1011 /* 1012 * Clear out target state by doing a special TEST UNIT READY. 1013 * Note that this calls espicmd (possibly recursively). 1014 */ 1015 void 1016 espclear(sc, targ) 1017 register struct esp_softc *sc; 1018 register int targ; 1019 { 1020 1021 /* turn off needclear immediately since this calls espicmd() again */ 1022 sc->sc_needclear &= ~(1 << targ); 1023 sc->sc_clearing = 1; 1024 (void) scsi_test_unit_ready(&sc->sc_hba, targ, 0); 1025 sc->sc_clearing = 0; 1026 } 1027 1028 /* 1029 * THIS SHOULD BE ADJUSTABLE 1030 */ 1031 /* name howlong purpose */ 1032 #define SELECT_WAIT 300000 /* wait for select to complete */ 1033 #define CMD_WAIT 100000 /* wait for next phase, generic */ 1034 #define DATA_WAIT 100000 /* time to xfer data in/out */ 1035 1036 /* 1037 * Send an `immediate' command, i.e., poll until the whole thing is done. 1038 * Return the status byte from the device, or -1 if we timed out. We use 1039 * DMA to transfer the data as the fifo only moves one byte at a time. 1040 */ 1041 int 1042 espicmd(hba, targ, cdb, buf, len, rw) 1043 struct hba_softc *hba; 1044 int targ; 1045 struct scsi_cdb *cdb; 1046 caddr_t buf; 1047 int len, rw; 1048 { 1049 register struct esp_softc *sc = (struct esp_softc *)hba; 1050 register volatile struct espreg *esp = sc->sc_esp; 1051 register volatile struct dmareg *dma = sc->sc_dma; 1052 register int r, wait; 1053 1054 /* 1055 * Clear the target if necessary. 1056 */ 1057 if (sc->sc_needclear & (1 << targ) && !sc->sc_probing) 1058 espclear(sc, targ); 1059 1060 /* 1061 * Set up DMA transfer control (leaving interrupts disabled). 1062 */ 1063 sc->sc_dmactl = rw & B_READ ? DMA_ENA | DMA_READ : DMA_ENA; 1064 sc->sc_dmaaddr = (u_long)buf; 1065 sc->sc_resid = len; 1066 1067 /* 1068 * Disable hardware interrupts and start select sequence, 1069 * then loop, calling espact() after each ``interrupt''. 1070 */ 1071 DMAWAIT(dma); /* ??? */ 1072 dma->dma_csr = 0; 1073 espselect(sc, targ, cdb); 1074 wait = SELECT_WAIT; 1075 for (;;) { 1076 r = dma->dma_csr; 1077 if (!DMA_INTR(r)) { 1078 if (--wait < 0) { 1079 esperror(sc, "timeout"); 1080 goto reset; 1081 } 1082 DELAY(1); 1083 continue; 1084 } 1085 sc->sc_espstat = esp->esp_stat; 1086 sc->sc_espstep = esp->esp_step & ESPSTEP_MASK; 1087 sc->sc_espintr = esp->esp_intr; 1088 sc->sc_espfflags = esp->esp_fflags; 1089 sc->sc_dmacsr = r; 1090 switch (r = espact(sc)) { 1091 1092 case ACT_CONT: 1093 case ACT_QUICKINTR: 1094 wait = CMD_WAIT; 1095 break; 1096 1097 case ACT_IO: 1098 wait = DATA_WAIT; 1099 break; 1100 1101 case ACT_RESET: 1102 sc->sc_state = S_IDLE; 1103 goto reset; 1104 1105 case ACT_DONE: 1106 sc->sc_state = S_IDLE; 1107 return (sc->sc_stat[0]); 1108 1109 case ACT_ERROR: 1110 sc->sc_state = S_IDLE; 1111 return (-1); 1112 1113 default: 1114 panic("espicmd action"); 1115 } 1116 } 1117 reset: 1118 espreset(sc, RESET_ESPCHIP); /* ??? */ 1119 return (-1); 1120 } 1121 1122 /* 1123 * Dump (write memory, possibly physmem). 1124 * SPARC higher-level dump code always provides virtual addresses, 1125 * so we need not do any I/O mapping here. 1126 */ 1127 int 1128 espdump(hba, targ, cdb, buf, len) 1129 register struct hba_softc *hba; 1130 int targ; 1131 struct scsi_cdb *cdb; 1132 caddr_t buf; 1133 register int len; 1134 { 1135 1136 return (espicmd(hba, targ, cdb, buf, len, B_WRITE)); 1137 } 1138 1139 /* 1140 * Allocate resources (SCSI bus and DVMA space) for the given transfer. 1141 * Must be called at splbio(). 1142 * 1143 * THIS SHOULD RETURN SUCCESS/FAIL INDICATION 1144 */ 1145 void 1146 espstart(self, sq, bp, dgo, dev) 1147 struct device *self; 1148 register struct sq *sq; 1149 struct buf *bp; 1150 scdgo_fn dgo; 1151 struct device *dev; 1152 { 1153 register struct esp_softc *sc = (struct esp_softc *)self; 1154 1155 if (sc->sc_hba.hba_busy == 0) { 1156 /* 1157 * Bus not busy, nothing to do here, just tell 1158 * this target or unit that it has the SCSI bus. 1159 */ 1160 sc->sc_hba.hba_busy = 1; 1161 (*dgo)(dev, &sc->sc_cdbspace); 1162 } else { 1163 /* 1164 * Bus is busy; just enqueue. 1165 */ 1166 sq->sq_dgo = dgo; 1167 sq->sq_dev = dev; 1168 sq->sq_forw = NULL; 1169 if (sc->sc_hba.hba_head == NULL) 1170 sc->sc_hba.hba_head = sq; 1171 else 1172 sc->sc_hba.hba_tail->sq_forw = sq; 1173 sc->sc_hba.hba_tail = sq; 1174 } 1175 } 1176 1177 /* 1178 * Start buffered I/O. 1179 * Return 0 on success, 1 on failure. 1180 */ 1181 int 1182 espgo(self, targ, intr, dev, bp, pad) 1183 struct device *self; 1184 int targ; 1185 scintr_fn intr; 1186 struct device *dev; 1187 register struct buf *bp; 1188 int pad; 1189 { 1190 register struct esp_softc *sc = (struct esp_softc *)self; 1191 1192 if (sc->sc_needclear & (1 << targ)) 1193 espclear(sc, targ); 1194 1195 /* Set up dma control for espact(). */ 1196 sc->sc_dmactl = bp->b_flags & B_READ ? 1197 DMA_ENA | DMA_READ | DMA_IE : DMA_ENA | DMA_IE; 1198 sc->sc_dmaaddr = (u_long)bp->b_un.b_addr; 1199 sc->sc_resid = bp->b_bcount; 1200 1201 /* 1202 * Enable interrupts and start selection. 1203 * The rest is done in espintr() and espact(). 1204 */ 1205 sc->sc_hba.hba_intr = intr; /* remember dev done function */ 1206 sc->sc_hba.hba_intrdev = dev; /* and its first arg */ 1207 sc->sc_dma->dma_csr = DMA_IE; 1208 espselect(sc, targ, &sc->sc_cdbspace); 1209 return (0); 1210 } 1211 1212 /* 1213 * Handle interrupt. Return 1 if taken. 1214 */ 1215 int 1216 espintr(sc0) 1217 void *sc0; 1218 { 1219 register struct esp_softc *sc = (struct esp_softc *)sc0; 1220 register volatile struct espreg *esp = sc->sc_esp; 1221 register volatile struct dmareg *dma = sc->sc_dma; 1222 register int r, wait; 1223 register struct sq *sq; 1224 1225 r = dma->dma_csr; 1226 if (!DMA_INTR(r)) 1227 return (0); /* not ours */ 1228 sc->sc_intrcnt.ev_count++; 1229 1230 again: 1231 sc->sc_espstat = esp->esp_stat; 1232 sc->sc_espstep = esp->esp_step & ESPSTEP_MASK; 1233 sc->sc_espintr = esp->esp_intr; 1234 sc->sc_espfflags = esp->esp_fflags; 1235 sc->sc_dmacsr = r; 1236 1237 if (sc->sc_state == S_IDLE) { 1238 printf("%s: stray interrupt\n", sc->sc_dev.dv_xname); 1239 dma->dma_csr &= ~DMA_IE; /* ??? */ 1240 return (1); 1241 } 1242 switch (r = espact(sc)) { 1243 1244 case ACT_CONT: /* just return */ 1245 case ACT_IO: 1246 break; 1247 1248 case ACT_RESET: /* please reset esp */ 1249 reset: 1250 espreset(sc, RESET_ESPCHIP); /* ??? */ 1251 /* FALLTHROUGH */ 1252 1253 case ACT_DONE: /* this one is done, successfully */ 1254 case ACT_ERROR: /* this one is done due to `severe' error */ 1255 sc->sc_state = S_IDLE; 1256 if (!sc->sc_hba.hba_busy) 1257 panic("espintr sq"); 1258 /* 1259 * This transaction is done. 1260 * Call the driver's intr routine, 1261 * then start the next guy if any. 1262 */ 1263 (*sc->sc_hba.hba_intr)(sc->sc_hba.hba_intrdev, 1264 r == ACT_DONE ? sc->sc_stat[0] : -1, sc->sc_resid); 1265 if ((sq = sc->sc_hba.hba_head) != NULL) { 1266 sc->sc_hba.hba_head = sq->sq_forw; 1267 (*sq->sq_dgo)(sq->sq_dev, &sc->sc_cdbspace); 1268 } else 1269 sc->sc_hba.hba_busy = 0; 1270 break; 1271 1272 case ACT_QUICKINTR: /* wait a short while for another interrupt */ 1273 printf("%s: quickintr: ", sc->sc_dev.dv_xname); 1274 wait = 100; 1275 do { 1276 r = dma->dma_csr; 1277 if (DMA_INTR(r)) { 1278 printf("got one, wait=%d\n", wait); 1279 goto again; 1280 } 1281 } while (--wait > 0); 1282 printf("did not get one\n"); 1283 break; 1284 1285 default: 1286 panic("espintr action"); 1287 } 1288 return (1); 1289 } 1290 1291 /* 1292 * Target or unit decided to let go of the bus early. 1293 */ 1294 void 1295 esprel(self) 1296 struct device *self; 1297 { 1298 register struct esp_softc *sc = (struct esp_softc *)self; 1299 register struct sq *sq; 1300 1301 /* if there is someone else waiting, give them a crack at it */ 1302 if ((sq = sc->sc_hba.hba_head) != NULL) 1303 (*sq->sq_dgo)(sq->sq_dev, &sc->sc_cdbspace); 1304 else 1305 sc->sc_hba.hba_busy = 0; 1306 } 1307