1 /* 2 * Copyright (c) 1988, 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)esp.c 8.4 (Berkeley) 05/06/94 17 * 18 * from: $Header: esp.c,v 1.28 93/04/27 14:40:44 torek Exp $ (LBL) 19 * 20 * Loosely derived from Mary Baker's devSCSIC90.c from the Berkeley 21 * Sprite project, which is: 22 * 23 * Copyright 1988 Regents of the University of California 24 * Permission to use, copy, modify, and distribute this 25 * software and its documentation for any purpose and without 26 * fee is hereby granted, provided that the above copyright 27 * notice appear in all copies. The University of California 28 * makes no representations about the suitability of this 29 * software for any purpose. It is provided "as is" without 30 * express or implied warranty. 31 * 32 * from /sprite/src/kernel/dev/sun4c.md/RCS/devSCSIC90.c,v 1.4 33 * 90/12/19 12:37:58 mgbaker Exp $ SPRITE (Berkeley) 34 */ 35 36 /* 37 * Sbus ESP/DMA driver. A single driver must be used for both devices 38 * as they are physically tied to each other: The DMA chip can only 39 * be used to assist ESP SCSI transactions; the ESP interrupt enable is 40 * in the DMA chip csr. 41 * 42 * Since DMA and SCSI interrupts are handled in the same routine, the 43 * DMA device does not declare itself as an sbus device. This saves 44 * some space. 45 */ 46 47 #include <sys/param.h> 48 #include <sys/buf.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 52 #include <dev/scsi/scsi.h> 53 #include <dev/scsi/scsivar.h> 54 55 #include <machine/autoconf.h> 56 #include <machine/cpu.h> 57 58 #include <sparc/sbus/dmareg.h> 59 #define ESP_PHASE_NAMES 60 #include <sparc/sbus/espreg.h> 61 #include <sparc/sbus/sbusvar.h> 62 63 #include <libkern/libkern.h> 64 65 /* 66 * This driver is largely a giant state machine: 67 * 68 * Given some previous SCSI state (as set up or tracked by us 69 * earlier) and the interrupt registers provided on the chips 70 * (dmacsr, espstat, espstep, and espintr), derive an action. 71 * In many cases this is just a matter of reading the target's 72 * phase and following its orders, which sets a new state. 73 * 74 * This sequencing is done in espact(); the state is primed in espselect(). 75 * 76 * Data transfer is always done via DMA. Unfortunately, there are 77 * limits in the DMA and ESP chips on how much data can be moved 78 * in a single operation. The ESP chip has a 16-bit counter, so 79 * it is limited to 65536 bytes. More insidiously, while the DMA 80 * chip has a 32-bit address, this is composed of a 24-bit counter 81 * with an 8-bit latch, so it cannot cross a 16 MB boundary. To 82 * handle these, we program a smaller count than our caller requests; 83 * when this shorter transfer is done, if the target is still up 84 * for data transfer, we simply keep going (updating the DMA address) 85 * as needed. 86 */ 87 88 /* per-DMA variables */ 89 struct dma_softc { 90 struct device dc_dev; /* base device */ 91 volatile struct dmareg *dc_dma; /* register virtual address */ 92 int dc_dmarev; /* revision */ 93 char *dc_dmafmt; /* format for error messages */ 94 }; 95 void dmaattach(struct device *, struct device *, void *); 96 struct cfdriver dmacd = 97 { NULL, "dma", matchbyname, dmaattach, DV_DULL, sizeof(struct dma_softc) }; 98 99 /* per-ESP variables */ 100 struct esp_softc { 101 /* 102 * External interfaces. 103 */ 104 struct hba_softc sc_hba; /* base device + hba, must be first */ 105 #define sc_dev sc_hba.hba_dev 106 struct sbusdev sc_sd; /* sbus device */ 107 struct intrhand sc_ih; /* interrupt entry */ 108 struct evcnt sc_intrcnt; /* interrupt counter */ 109 struct dma_softc *sc_dc; /* pointer to corresponding dma sc */ 110 111 /* 112 * Addresses mapped to hardware registers. 113 */ 114 volatile struct espreg *sc_esp; 115 volatile struct dmareg *sc_dma; 116 117 /* 118 * Copies of registers cleared/unlatched by reading. 119 * (FIFO flags is not cleared, but we want it for debugging.) 120 */ 121 u_long sc_dmacsr; 122 u_char sc_espstat; 123 u_char sc_espstep; 124 u_char sc_espintr; 125 u_char sc_espfflags; 126 127 /* miscellaneous */ 128 int sc_clockfreq; /* clock frequency */ 129 u_char sc_sel_timeout; /* select timeout */ 130 u_char sc_id; /* initiator ID (default = 7) */ 131 u_char sc_esptype; /* 100, 100A, 2xx (see below) */ 132 u_char sc_ccf; /* clock conversion factor */ 133 u_char sc_conf1; /* value for config reg 1 */ 134 u_char sc_conf2; /* value for config reg 2 */ 135 u_char sc_conf3; /* value for config reg 3 */ 136 struct bootpath *sc_bp; /* esp bootpath so far */ 137 138 /* 139 * Information pertaining to the current transfer, 140 * including sequencing. 141 * 142 * The size of sc_msg is the size of the ESP fifo, 143 * since we do message-in simply by allowing the fifo to fill. 144 */ 145 char sc_probing; /* used during autoconf; see below */ 146 char sc_iwant; /* true => icmd needs wakeup on idle */ 147 char sc_state; /* SCSI protocol state; see below */ 148 char sc_sentcmd; /* set once we get cmd out */ 149 char sc_dmaactive; /* true => doing dma */ 150 #ifdef notyet 151 u_char sc_sync; /* synchronous transfer stuff (?) */ 152 #endif 153 u_char sc_stat[2]; /* status from last `status' phase */ 154 u_char sc_msg[16]; /* message from device */ 155 u_short sc_dmactl; /* control to load into dma csr */ 156 u_long sc_dmaaddr; /* address for next xfer */ 157 int sc_dmasize; /* size of current xfer */ 158 int sc_resid; /* count of bytes not yet xferred */ 159 int sc_targ; /* the target involved */ 160 struct scsi_cdb *sc_curcdb; /* ptr to current command */ 161 /* might cdbspace eventually be per-target? */ 162 struct scsi_cdb sc_cdbspace; /* space for one command */ 163 }; 164 165 /* 166 * Values for sc_esptype (used to control configuration reset, and for 167 * workarounds for chip bugs). The order is important; see espreset(). 168 */ 169 #define ESP100 0 170 #define ESP100A 1 171 #define ESP2XX 2 172 173 /* 174 * Probe state. 0 means not probing. While looking for each target 175 * we set this to PROBE_TESTING and do a TEST UNIT READY on unit 0. 176 * If selection fails, this is changed to PROBE_NO_TARGET; otherwise 177 * we assume the target exists, regardless of the result of the test. 178 */ 179 #define PROBE_TESTING 1 180 #define PROBE_NO_TARGET 2 181 182 /* 183 * States in sc_state. 184 * 185 * Note that S_SVC is rare: normally we load the SCSI command into the 186 * ESP fifo and get interrupted only when the device has gone to data 187 * or status phase. If the device wants to play games, though, we end 188 * up doing things differently. 189 */ 190 char *espstates[] = { 191 #define S_IDLE 0 /* not doing anything */ 192 "idle", 193 #define S_SEL 1 /* expecting select done interrupt */ 194 "selecting", 195 #define S_SVC 2 /* expecting service req interrupt */ 196 "waiting for svc req", 197 #define S_DI 3 /* expecting data-in done interrupt */ 198 "receiving data", 199 #define S_DO 4 /* expecting data-out done interrupt */ 200 "sending data", 201 #define S_STAT 5 /* expecting status done interrupt */ 202 "receiving status", 203 #define S_MI 6 /* expecting message-in done interrupt */ 204 "receiving message", 205 #define S_FI 7 /* expecting final disconnect interrupt */ 206 "waiting for disconnect" 207 }; 208 209 /* 210 * Hardware limits on transfer sizes (see comments at top). 211 */ 212 #define ESPMAX (64 * 1024) 213 #define DMAMAX(a) (0x01000000 - ((a) & 0x00ffffff)) 214 215 /* 216 * Return values from espact(). 217 */ 218 #define ACT_CONT 0 /* espact() handled everything */ 219 #define ACT_IO 1 /* espact() is xferring data */ 220 #define ACT_DONE 2 /* handled everything, and op is now done */ 221 #define ACT_ERROR 3 /* an error occurred, op has been trashed */ 222 #define ACT_RESET 4 /* please reset ESP, then do ACT_ERROR */ 223 #define ACT_QUICKINTR 5 /* another interrupt is expected immediately */ 224 225 /* autoconfiguration driver */ 226 void espattach(struct device *, struct device *, void *); 227 struct cfdriver espcd = 228 { NULL, "esp", matchbyname, espattach, DV_DULL, sizeof(struct esp_softc) }; 229 230 /* Sbus driver */ 231 void espsbreset(struct device *); 232 233 /* interrupt interface */ 234 int espintr(void *); 235 236 /* SCSI HBA driver */ 237 int espicmd(struct hba_softc *, int, struct scsi_cdb *, caddr_t, int, int); 238 int espdump(struct hba_softc *, int, struct scsi_cdb *, caddr_t, int); 239 void espstart(struct device *, struct sq *, struct buf *, 240 scdgo_fn, struct device *); 241 int espgo(struct device *, int, scintr_fn, struct device *, 242 struct buf *, int); 243 void esprel(struct device *); 244 void esphbareset(struct hba_softc *, int); 245 static struct hbadriver esphbadriver = 246 { espicmd, espdump, espstart, espgo, esprel, esphbareset }; 247 248 /* other prototypes */ 249 static void espdoattach(int); 250 static void dmareset(struct esp_softc *); 251 static void espreset(struct esp_softc *, int); 252 static void esperror(struct esp_softc *, const char *); 253 static int espact(struct esp_softc *); 254 void espselect(struct esp_softc *, int, struct scsi_cdb *); 255 256 /* second arg to espreset() */ 257 #define RESET_ESPCHIP 0x1 258 #define RESET_SCSIBUS 0x2 259 #define RESET_BOTH (RESET_ESPCHIP | RESET_SCSIBUS) 260 261 /* 262 * Attach a found DMA chip. 263 * The second argument is really a pointer to an sbus_attach_args. 264 */ 265 void 266 dmaattach(parent, dev, args) 267 struct device *parent; 268 struct device *dev; 269 void *args; 270 { 271 register struct dma_softc *dc = (struct dma_softc *)dev; 272 register struct sbus_attach_args *sa = args; 273 register volatile struct dmareg *dma; 274 register int rev; 275 struct esp_softc *esc; 276 277 if (sa->sa_ra.ra_vaddr) 278 dma = (volatile struct dmareg *)sa->sa_ra.ra_vaddr; 279 else 280 dma = (volatile struct dmareg *) 281 mapiodev(sa->sa_ra.ra_paddr, sizeof(struct dmareg)); 282 dc->dc_dma = dma; 283 284 switch (rev = DMA_REV(dma->dma_csr)) { 285 case DMAREV_1: 286 printf(": rev 1\n"); 287 dc->dc_dmafmt = DMA_REV1_BITS; 288 break; 289 case DMAREV_2: 290 printf(": rev 2\n"); 291 dc->dc_dmafmt = DMA_REV2_BITS; 292 break; 293 case DMAREV_3: 294 printf(": rev 3\n"); 295 printf("WARNING: esp.c not yet updated for rev 3\n"); 296 dc->dc_dmafmt = DMA_REV3_BITS; 297 break; 298 default: 299 printf(": unknown revision code 0x%x\n", rev); 300 dc->dc_dmafmt = DMA_REV3_BITS; /* cross fingers */ 301 break; 302 } 303 dc->dc_dmarev = rev; 304 espdoattach(dc->dc_dev.dv_unit); 305 } 306 307 /* 308 * Attach a found ESP chip. Search for targets; attach each one found. 309 * The latter must be deferred if the corresponding dma chip has not yet 310 * been configured. 311 */ 312 void 313 espattach(parent, self, args) 314 struct device *parent; 315 struct device *self; 316 void *args; 317 { 318 register struct esp_softc *sc = (struct esp_softc *)self; 319 register struct sbus_attach_args *sa = args; 320 register volatile struct espreg *esp; 321 register struct bootpath *bp; 322 int node, pri, freq, t; 323 324 if (sa->sa_ra.ra_nintr != 1) { 325 printf(": expected 1 interrupt, got %d\n", sa->sa_ra.ra_nintr); 326 return; 327 } 328 pri = sa->sa_ra.ra_intr[0].int_pri; 329 printf(" pri %d", pri); 330 if (sa->sa_ra.ra_vaddr) 331 esp = (volatile struct espreg *)sa->sa_ra.ra_vaddr; 332 else 333 esp = (volatile struct espreg *) 334 mapiodev(sa->sa_ra.ra_paddr, sizeof(struct espreg)); 335 sc->sc_esp = esp; 336 node = sa->sa_ra.ra_node; 337 sc->sc_id = getpropint(node, "initiator-id", 7); 338 freq = getpropint(node, "clock-frequency", -1); 339 if (freq < 0) 340 freq = 341 ((struct sbus_softc *)sc->sc_dev.dv_parent)->sc_clockfreq; 342 343 /* MIGHT NEED TO RESET ESP CHIP HERE ...? */ 344 345 /* 346 * Find out whether we have a -100, -100A, or -2xx, 347 * and what speed it runs at. 348 */ 349 sc->sc_conf1 = sc->sc_id | ESPCONF1_PARENB; 350 /* sc->sc_conf2 = 0; */ 351 /* sc->sc_conf3 = 0; */ 352 esp->esp_conf1 = sc->sc_conf1; 353 esp->esp_conf2 = 0; 354 esp->esp_conf2 = ESPCONF2_SCSI2 | ESPCONF2_RPE; 355 if ((esp->esp_conf2 & ~ESPCONF2_RSVD) != 356 (ESPCONF2_SCSI2 | ESPCONF2_RPE)) { 357 printf(": ESP100"); 358 sc->sc_esptype = ESP100; 359 } else { 360 esp->esp_conf2 = 0; 361 esp->esp_conf3 = 0; 362 esp->esp_conf3 = 5; 363 if (esp->esp_conf3 != 5) { /* XXX def bits */ 364 printf(": ESP100A"); 365 sc->sc_esptype = ESP100A; 366 } else { 367 esp->esp_conf3 = 0; 368 printf(": ESP2XX"); 369 sc->sc_esptype = ESP2XX; 370 } 371 } 372 printf(", clock = %s MHz, ID = %d\n", clockfreq(freq), sc->sc_id); 373 374 /* 375 * Set clock conversion factor and select timeout. 376 * N.B.: clock frequency is not actually used in the rest 377 * of the driver; I calculate it here for completeness only 378 * (so I can see it when debugging). 379 */ 380 sc->sc_clockfreq = freq; 381 freq = howmany(freq, 1000 * 1000); /* convert to MHz */ 382 t = ESPCCF_FROMMHZ(freq); 383 if (t < ESPCCF_MIN) 384 t = ESPCCF_MIN; 385 sc->sc_ccf = t; 386 t = ESPTIMO_REGVAL(250, t, freq); /* timeout = 250 ms. */ 387 if (t >= 256) 388 t = 0; 389 sc->sc_sel_timeout = t; 390 391 /* 392 * Link into sbus; set interrupt handler. 393 */ 394 sc->sc_sd.sd_reset = espsbreset; 395 sbus_establish(&sc->sc_sd, &sc->sc_dev); 396 sc->sc_ih.ih_fun = espintr; 397 sc->sc_ih.ih_arg = sc; 398 intr_establish(pri, &sc->sc_ih); 399 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 400 401 #define SAME_ESP(bp, sa) \ 402 ((bp->val[0] == sa->sa_slot && bp->val[1] == sa->sa_offset) || \ 403 (bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit)) 404 405 bp = sa->sa_ra.ra_bp; 406 if (bp != NULL && strcmp(bp->name, "esp") == 0 && SAME_ESP(bp, sa)) 407 sc->sc_bp = bp + 1; 408 espdoattach(sc->sc_dev.dv_unit); 409 } 410 411 /* 412 * `Final' attach of esp occurs once esp and dma chips have been found 413 * and assigned virtual addresses. Set up the ESP SCSI data structures 414 * and probe the SCSI bus. 415 */ 416 static void 417 espdoattach(unit) 418 int unit; 419 { 420 register struct esp_softc *sc; 421 register struct dma_softc *dc; 422 register struct bootpath *bp; 423 register struct targ *t; 424 register int targ, u; 425 426 /* make sure we have both */ 427 if (espcd.cd_ndevs <= unit || 428 dmacd.cd_ndevs <= unit || 429 (sc = espcd.cd_devs[unit]) == NULL || 430 (dc = dmacd.cd_devs[unit]) == NULL) 431 return; 432 sc->sc_dc = dc; 433 sc->sc_dma = dc->dc_dma; 434 sc->sc_hba.hba_driver = &esphbadriver; 435 436 sc->sc_dma->dma_csr = 0; /* ??? */ 437 espreset(sc, RESET_ESPCHIP); 438 439 /* MAYBE THIS SHOULD BE MOVED TO scsi_subr.c? */ 440 for (targ = 0; targ < 8; targ++) { 441 if (targ == sc->sc_id) 442 continue; 443 sc->sc_probing = PROBE_TESTING; 444 (void)scsi_test_unit_ready(&sc->sc_hba, targ, 0); 445 if (sc->sc_probing != PROBE_NO_TARGET) { 446 sc->sc_probing = 0; 447 SCSI_FOUNDTARGET(&sc->sc_hba, targ); 448 } 449 } 450 sc->sc_probing = 0; 451 452 /* 453 * See if we booted from a unit on this target. We could 454 * compare bp->name against the unit's name but there's no 455 * real need since a target and unit uniquely specify a 456 * scsi device. 457 */ 458 if ((bp = sc->sc_bp) != NULL && (u_int)(targ = bp->val[0]) < 8 && 459 (u_int)(u = bp->val[1]) < 8 && 460 (t = sc->sc_hba.hba_targets[targ]) != NULL && t->t_units[u] != NULL) 461 bootdv = t->t_units[u]->u_dev; 462 } 463 464 /* 465 * We are not allowed to touch the DMA "flush" and "drain" bits 466 * while it is still thinking about a request (DMA_RP). 467 */ 468 #define DMAWAIT(dma) while ((dma)->dma_csr & DMA_RP) DELAY(1) 469 #define DMAWAIT1(dma) while ((dma)->dma_csr & DMA_PC) DELAY(1) 470 471 /* 472 * Reset the DMA chip. 473 */ 474 static void 475 dmareset(sc) 476 struct esp_softc *sc; 477 { 478 register volatile struct dmareg *dma = sc->sc_dma; 479 480 DMAWAIT(dma); 481 dma->dma_csr |= DMA_RESET; 482 DELAY(200); 483 dma->dma_csr &= ~DMA_RESET; /* ??? */ 484 sc->sc_dmaactive = 0; 485 if (sc->sc_dc->dc_dmarev == DMAREV_2 && sc->sc_esptype != ESP100) 486 dma->dma_csr |= DMA_TURBO; 487 dma->dma_csr |= DMA_IE; /* enable interrupts */ 488 DELAY(200); 489 } 490 491 /* 492 * Reset the chip and/or SCSI bus (always resets DMA). 493 */ 494 static void 495 espreset(sc, how) 496 register struct esp_softc *sc; 497 int how; 498 { 499 register volatile struct espreg *esp = sc->sc_esp; 500 501 dmareset(sc); 502 if (how & RESET_ESPCHIP) { 503 esp->esp_cmd = ESPCMD_RESET_CHIP; 504 esp->esp_cmd = ESPCMD_NOP; 505 /* 506 * Reload configuration registers (cleared by 507 * RESET_CHIP command). Reloading conf2 on an 508 * ESP100 goofs it up, so out of paranoia we load 509 * only the registers that exist. 510 */ 511 esp->esp_conf1 = sc->sc_conf1; 512 if (sc->sc_esptype > ESP100) { /* 100A, 2XX */ 513 esp->esp_conf2 = sc->sc_conf2; 514 if (sc->sc_esptype > ESP100A) /* 2XX only */ 515 esp->esp_conf3 = sc->sc_conf3; 516 } 517 esp->esp_ccf = sc->sc_ccf; 518 esp->esp_timeout = sc->sc_sel_timeout; 519 /* We set synch offset later. */ 520 } 521 if (how & RESET_SCSIBUS) { 522 /* 523 * The chip should retain most of its parameters 524 * (including esp_ccf) across this kind of reset 525 * (see section 3.5 of Emulex documentation). 526 */ 527 /* turn off scsi bus reset interrupts and reset scsi bus */ 528 esp->esp_conf1 = sc->sc_conf1 | ESPCONF1_REPORT; 529 esp->esp_cmd = ESPCMD_RESET_BUS; 530 esp->esp_cmd = ESPCMD_NOP; 531 DELAY(100000); /* ??? */ 532 (void)esp->esp_intr; 533 esp->esp_conf1 = sc->sc_conf1; 534 } 535 sc->sc_state = S_IDLE; 536 } 537 538 /* 539 * Reset the SCSI bus and, optionally, all attached targets. 540 */ 541 void 542 esphbareset(hba, resetunits) 543 struct hba_softc *hba; 544 int resetunits; 545 { 546 register struct esp_softc *sc = (struct esp_softc *)hba; 547 548 espreset(sc, RESET_SCSIBUS); 549 if (resetunits) 550 scsi_reset_units(&sc->sc_hba); 551 } 552 553 /* 554 * Reset the esp, after an Sbus reset. 555 * Also resets corresponding dma chip. 556 * 557 * THIS ROUTINE MIGHT GO AWAY 558 */ 559 void 560 espsbreset(dev) 561 struct device *dev; 562 { 563 struct esp_softc *sc = (struct esp_softc *)dev; 564 565 if (sc->sc_dc) { 566 printf(" %s %s", sc->sc_dc->dc_dev.dv_xname, 567 sc->sc_dev.dv_xname); 568 esphbareset(&sc->sc_hba, 1); 569 } 570 } 571 572 /* 573 * Log an error. 574 */ 575 static void 576 esperror(sc, err) 577 register struct esp_softc *sc; 578 const char *err; 579 { 580 int stat; 581 582 stat = sc->sc_espstat; 583 printf( 584 "%s target %d cmd 0x%x (%s): %s:\n\ 585 \tstat=%b (%s) step=%x dmacsr=%b fflags=%x intr=%b\n", 586 sc->sc_dev.dv_xname, sc->sc_targ, sc->sc_curcdb->cdb_bytes[0], 587 espstates[sc->sc_state], err, 588 stat, ESPSTAT_BITS, espphases[stat & ESPSTAT_PHASE], 589 sc->sc_espstep, sc->sc_dmacsr, sc->sc_dc->dc_dmafmt, 590 sc->sc_espfflags, sc->sc_espintr, ESPINTR_BITS); 591 } 592 593 /* 594 * Issue a select, loading command into the FIFO. 595 * Return nonzero on error, 0 if OK. 596 * Sets state to `selecting'; espact() will sequence state FSM. 597 */ 598 void 599 espselect(sc, targ, cdb) 600 register struct esp_softc *sc; 601 register int targ; 602 register struct scsi_cdb *cdb; 603 { 604 register volatile struct espreg *esp; 605 register int i, cmdlen; 606 607 sc->sc_targ = targ; 608 sc->sc_state = S_SEL; 609 sc->sc_curcdb = cdb; 610 sc->sc_sentcmd = 0; 611 sc->sc_stat[0] = 0xff; /* ??? */ 612 sc->sc_msg[0] = 0xff; /* ??? */ 613 614 /* 615 * Try to talk to target. 616 * Synch offset 0 => asynchronous transfer. 617 */ 618 esp = sc->sc_esp; 619 esp->esp_id = targ; 620 esp->esp_syncoff = 0; 621 622 /* 623 * Stuff the command bytes into the fifo. 624 * Select without attention since we do not do disconnect yet. 625 */ 626 cmdlen = SCSICMDLEN(cdb->cdb_bytes[0]); 627 for (i = 0; i < cmdlen; i++) 628 esp->esp_fifo = cdb->cdb_bytes[i]; 629 esp->esp_cmd = ESPCMD_SEL_NATN; 630 /* the rest is done elsewhere */ 631 } 632 633 /* 634 * Sequence through the SCSI state machine. Return the action to take. 635 * 636 * Most of the work happens here. 637 * 638 * There are three interrupt sources: 639 * -- ESP interrupt request (typically, some device wants something). 640 * -- DMA memory error. 641 * -- DMA byte count has reached 0 (we do not often want this one but 642 * can only turn it off in rev 2 DMA chips, it seems). 643 * DOES THIS OCCUR AT ALL HERE? THERE IS NOTHING TO HANDLE IT! 644 */ 645 static int 646 espact(sc) 647 register struct esp_softc *sc; 648 { 649 register volatile struct espreg *esp; 650 register volatile struct dmareg *dma; 651 register int reg, i, resid, newstate; 652 register struct scsi_cdb *cdb; 653 654 dma = sc->sc_dma; 655 /* check various error conditions, using as little code as possible */ 656 if (sc->sc_dmacsr & DMA_EP) { 657 esperror(sc, "DMA error"); 658 DMAWAIT(dma); 659 dma->dma_csr |= DMA_FLUSH; 660 DMAWAIT1(dma); 661 return (ACT_ERROR); 662 } 663 reg = sc->sc_espstat; 664 if (reg & ESPSTAT_GE) { 665 /* 666 * This often occurs when there is no target. 667 * (See DSC code below.) 668 */ 669 if (sc->sc_espintr & ESPINTR_DSC && 670 sc->sc_state == S_SEL && sc->sc_probing) { 671 sc->sc_probing = PROBE_NO_TARGET; 672 return (ACT_RESET); 673 } 674 esperror(sc, "DIAG: gross error (ignored)"); 675 } 676 if (reg & ESPSTAT_PE) { 677 esperror(sc, "parity error"); 678 return (ACT_RESET); 679 } 680 reg = sc->sc_espintr; 681 #define ERR (ESPINTR_SBR|ESPINTR_ILC|ESPINTR_RSL|ESPINTR_SAT|ESPINTR_SEL) 682 if (reg & ERR) { 683 if (reg & ESPINTR_SBR) 684 esperror(sc, "scsi bus reset"); 685 else if (reg & ESPINTR_ILC) 686 esperror(sc, "illegal command (driver bug)"); 687 else { 688 printf("%s: target %d", sc->sc_dev.dv_xname, 689 sc->sc_targ); 690 if (reg & ESPINTR_RSL) 691 printf(" tried to reselect;"); 692 if (reg & ESPINTR_SAT) 693 printf(" selected with ATN;"); 694 if (reg & ESPINTR_SEL) 695 printf(" selected us as target;"); 696 printf("we do not allow this yet\n"); 697 } 698 return (ACT_ERROR); 699 } 700 #undef ERR 701 702 esp = sc->sc_esp; 703 704 /* 705 * Disconnect currently only allowed in `final interrupt' states. 706 */ 707 if (reg & ESPINTR_DSC) { 708 if (sc->sc_state == S_FI) 709 return (ACT_DONE); 710 /* 711 * If we were doing a select just to test the existence 712 * of the target, note that it did not respond; otherwise 713 * gripe. 714 */ 715 if (sc->sc_state == S_SEL) { 716 if (sc->sc_probing) { 717 sc->sc_probing = PROBE_NO_TARGET; 718 return (ACT_RESET); 719 } 720 } 721 /* flush fifo, in case we were selecting or sending data */ 722 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 723 DELAY(1); 724 printf("%s: target %d not responding\n", 725 sc->sc_dev.dv_xname, sc->sc_targ); 726 return (ACT_ERROR); 727 } 728 729 /* 730 * Okay, things are moving along. 731 * What were we doing the last time we did something, 732 * and did it complete normally? 733 */ 734 switch (sc->sc_state) { 735 736 case S_SEL: 737 /* 738 * We were selecting. Arbitration and select are 739 * complete (because ESPINTR_DSC was not set), but 740 * there is no guarantee the command went out. 741 */ 742 if ((reg & (ESPINTR_SVC|ESPINTR_CMP)) != 743 (ESPINTR_SVC|ESPINTR_CMP)) { 744 esperror(sc, "selection failed"); 745 return (ACT_RESET); 746 } 747 if (sc->sc_espstep == ESPSTEP_DONE) { 748 sc->sc_sentcmd = 1; 749 break; 750 } 751 if (sc->sc_espstep == 2) { 752 /* 753 * We got something other than command phase. 754 * Just pretend things are normal; the 755 * device will ask for the command later. 756 */ 757 esperror(sc, "DIAG: esp step 2"); 758 } else if (sc->sc_espstep == 3) { 759 /* 760 * Device entered command phase and then exited it 761 * before we finished handing out the command. 762 * Do not know how to handle this. 763 */ 764 esperror(sc, "DIAG: esp step 3"); 765 } else { 766 printf("%s: mysterious esp step %d\n", 767 sc->sc_dev.dv_xname, sc->sc_espstep); 768 return (ACT_RESET); 769 } 770 771 /* 772 * Part of the command may still be lodged in the FIFO. 773 */ 774 if (ESP_NFIFO(sc->sc_espfflags)) { 775 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 776 DELAY(1); 777 } 778 break; 779 780 case S_SVC: 781 /* 782 * We were waiting for phase change after stuffing the command 783 * into the FIFO. Make sure it got out. 784 */ 785 if (ESP_NFIFO(sc->sc_espfflags)) { 786 esperror(sc, "DIAG: CMDSVC, fifo not empty"); 787 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 788 DELAY(1); 789 } else 790 sc->sc_sentcmd = 1; 791 break; 792 793 case S_DI: 794 /* 795 * We were doing DMA data in, and expecting a 796 * transfer-count-zero interrupt or a phase change. 797 * We got that; drain the pack register and handle 798 * as for data out -- but ignore FIFO (it should be 799 * empty, except for sync mode which we are not 800 * using anyway). 801 */ 802 DMAWAIT(dma); 803 dma->dma_csr |= DMA_DRAIN; 804 DMAWAIT1(dma); 805 resid = 0; 806 goto dma_data_done; 807 808 case S_DO: 809 /* 810 * We were doing DMA data out. If there is data in the 811 * FIFO, it is stuff that got DMAed out but never made 812 * it to the device, so it counts as residual. 813 */ 814 if ((resid = ESP_NFIFO(sc->sc_espfflags)) != 0) { 815 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 816 DELAY(1); 817 } 818 dma_data_done: 819 if (sc->sc_dmaactive == 0) { 820 esperror(sc, "dma done w/o dmaactive"); 821 panic("espact"); 822 } 823 sc->sc_dmaactive = 0; 824 825 /* Finish computing residual count. */ 826 reg = esp->esp_tcl | (esp->esp_tch << 8); 827 if (reg == 0 && (sc->sc_espstat & ESPSTAT_TC) == 0) 828 reg = 65536; 829 resid += reg; 830 831 /* Compute xfer count (requested - resid). */ 832 i = sc->sc_dmasize - resid; 833 if (i < 0) { 834 printf("%s: xfer resid (%d) > xfer req (%d)\n", 835 sc->sc_dev.dv_xname, resid, sc->sc_dmasize); 836 i = sc->sc_dmasize; /* forgiving... */ 837 } 838 839 /* If data came in we must flush cache. */ 840 if (sc->sc_state == S_DI) 841 cache_flush(sc->sc_dmaaddr, i); 842 sc->sc_dmaaddr += i; 843 sc->sc_resid -= i; 844 if ((sc->sc_espintr & ESPINTR_SVC) == 0) { 845 esperror(sc, "no bus service req"); 846 return (ACT_RESET); 847 } 848 break; 849 850 case S_STAT: 851 /* 852 * The last thing we did was tell it `initiator complete' 853 * and so we expect to have gotten both the status byte 854 * and the final message byte. It is possible that we 855 * got something else.... 856 * 857 * Apparently, BUS SERVICE is set if we got just status, 858 * while FUNCTION COMPLETE is set if we got both. 859 */ 860 if ((reg & (ESPINTR_SVC|ESPINTR_CMP)) != ESPINTR_CMP) { 861 esperror(sc, "bad status interrupt state"); 862 return (ACT_RESET); 863 } 864 reg = ESP_NFIFO(sc->sc_espfflags); 865 if (reg < 2) { 866 printf( 867 "%s: command done but fifo count = %d; must be >= 2\n", 868 sc->sc_dev.dv_xname, reg); 869 return (ACT_RESET); 870 } 871 /* 872 * Read the status and the first msg byte. 873 * It should be CMD_COMPLETE. Eventually we 874 * may handle IDENTIFY, DISCONNECT, etc., as well. 875 */ 876 sc->sc_stat[0] = esp->esp_fifo; 877 sc->sc_msg[0] = reg = esp->esp_fifo; 878 esp->esp_cmd = ESPCMD_MSG_ACCEPT; 879 if (reg == MSG_CMD_COMPLETE) { 880 sc->sc_state = S_FI; 881 return (ACT_CONT); 882 } 883 if (SCSIMSGLEN(reg) != 1) { 884 printf("%s: target %d is naughty\n", 885 sc->sc_dev.dv_xname, sc->sc_targ); 886 return (ACT_RESET); 887 } 888 printf("%s: warning: target %d returned msg 0x%x\n", 889 sc->sc_dev.dv_xname, sc->sc_targ, reg); 890 sc->sc_state = S_FI; 891 return (ACT_CONT); 892 893 case S_MI: 894 if ((reg & ESPINTR_SVC) == 0) { 895 esperror(sc, "missing phase after msg in"); 896 return (ACT_RESET); 897 } 898 reg = ESP_NFIFO(sc->sc_espfflags); 899 for (i = 0; i < reg; i++) 900 sc->sc_msg[i] = esp->esp_fifo; 901 break; 902 903 case S_FI: 904 esperror(sc, "target did not disconnect"); 905 return (ACT_RESET); 906 } 907 908 /* 909 * Things are still moving along. The phase tells us 910 * what the device wants next. Do it. 911 */ 912 switch (sc->sc_espstat & ESPSTAT_PHASE) { 913 914 case ESPPHASE_DATA_OUT: 915 if (!sc->sc_sentcmd) esperror(sc, "DIAG: data out without command"); 916 if (sc->sc_dmactl & DMA_READ) { 917 esperror(sc, "wrong phase (want to read)"); 918 return (ACT_RESET); 919 } 920 newstate = S_DO; 921 goto do_data_xfer; 922 923 case ESPPHASE_DATA_IN: 924 if (!sc->sc_sentcmd) esperror(sc, "DIAG: data in without command"); 925 if (!(sc->sc_dmactl & DMA_READ)) { 926 esperror(sc, "wrong phase (want to write)"); 927 return (ACT_RESET); 928 } 929 newstate = S_DI; 930 do_data_xfer: 931 if (sc->sc_resid == 0) { 932 esperror(sc, "data count error"); 933 return (ACT_RESET); 934 } 935 936 /* 937 * Compute DMA count based on chip limits. 938 * Set DMA address and load transfer count into 939 * ESP via DMA NOP, then set DMA control, and 940 * then we can start the DMA. 941 */ 942 sc->sc_state = newstate; 943 i = min(sc->sc_resid, ESPMAX); 944 i = min(i, DMAMAX(sc->sc_dmaaddr)); 945 sc->sc_dmasize = i; 946 dma->dma_addr = sc->sc_dmaaddr; 947 esp->esp_tch = i >> 8; 948 esp->esp_tcl = i; 949 esp->esp_cmd = ESPCMD_DMA | ESPCMD_NOP; 950 dma->dma_csr = sc->sc_dmactl; 951 sc->sc_dmaactive = 1; 952 esp->esp_cmd = ESPCMD_DMA | ESPCMD_XFER_INFO; 953 return (ACT_IO); 954 955 case ESPPHASE_CMD: 956 /* 957 * Silly thing wants the command again. 958 * Load it into the FIFO and go to SVC state. 959 */ 960 printf("%s: redoing command\n", sc->sc_dev.dv_xname); 961 cdb = sc->sc_curcdb; 962 reg = SCSICMDLEN(cdb->cdb_bytes[0]); 963 for (i = 0; i < reg; i++) 964 esp->esp_fifo = cdb->cdb_bytes[i]; 965 sc->sc_state = S_SVC; 966 esp->esp_cmd = ESPCMD_XFER_INFO; 967 return (ACT_CONT); 968 969 case ESPPHASE_STATUS: 970 sc->sc_state = S_STAT; 971 esp->esp_cmd = ESPCMD_INIT_COMP; 972 return (ACT_CONT); 973 974 case ESPPHASE_MSG_IN: 975 printf("%s: accepting (& ignoring) msg from target %d\n", 976 sc->sc_dev.dv_xname, sc->sc_targ); 977 sc->sc_state = S_MI; 978 esp->esp_cmd = ESPCMD_MSG_ACCEPT; 979 return (ACT_CONT); 980 981 default: 982 esperror(sc, "bad phase"); 983 return (ACT_RESET); 984 } 985 /* NOTREACHED */ 986 } 987 988 /* 989 * THIS SHOULD BE ADJUSTABLE 990 */ 991 /* name howlong purpose */ 992 #define SELECT_WAIT 300000 /* wait for select to complete */ 993 #define CMD_WAIT 100000 /* wait for next phase, generic */ 994 #define DATA_WAIT 100000 /* time to xfer data in/out */ 995 996 /* 997 * Send an `immediate' command, i.e., poll until the whole thing is done. 998 * Return the status byte from the device, or -1 if we timed out. We use 999 * DMA to transfer the data as the fifo only moves one byte at a time. 1000 */ 1001 int 1002 espicmd(hba, targ, cdb, buf, len, rw) 1003 struct hba_softc *hba; 1004 int targ; 1005 struct scsi_cdb *cdb; 1006 caddr_t buf; 1007 int len, rw; 1008 { 1009 register struct esp_softc *sc = (struct esp_softc *)hba; 1010 register volatile struct espreg *esp = sc->sc_esp; 1011 register volatile struct dmareg *dma = sc->sc_dma; 1012 register int r, s, wait; 1013 register struct sq *sq; 1014 1015 /* 1016 * Wait for any ongoing operation to complete. 1017 */ 1018 s = splbio(); 1019 while (sc->sc_state != S_IDLE) { 1020 sc->sc_iwant = 1; 1021 tsleep((caddr_t)&sc->sc_iwant, PRIBIO, "espicmd", 0); 1022 } 1023 sc->sc_hba.hba_busy = 1; 1024 splx(s); 1025 1026 /* 1027 * Set up DMA transfer control (leaving interrupts disabled). 1028 */ 1029 sc->sc_dmactl = rw & B_READ ? DMA_ENA | DMA_READ : DMA_ENA; 1030 sc->sc_dmaaddr = (u_long)buf; 1031 sc->sc_resid = len; 1032 1033 /* 1034 * Disable hardware interrupts and start select sequence, 1035 * then loop, calling espact() after each ``interrupt''. 1036 */ 1037 DMAWAIT(dma); /* ??? */ 1038 dma->dma_csr = 0; 1039 espselect(sc, targ, cdb); 1040 wait = SELECT_WAIT; 1041 for (;;) { 1042 r = dma->dma_csr; 1043 if (!DMA_INTR(r)) { 1044 if (--wait < 0) { 1045 esperror(sc, "timeout"); 1046 goto reset; 1047 } 1048 DELAY(1); 1049 continue; 1050 } 1051 sc->sc_espstat = esp->esp_stat; 1052 sc->sc_espstep = esp->esp_step & ESPSTEP_MASK; 1053 sc->sc_espintr = esp->esp_intr; 1054 sc->sc_espfflags = esp->esp_fflags; 1055 sc->sc_dmacsr = r; 1056 switch (r = espact(sc)) { 1057 1058 case ACT_CONT: 1059 case ACT_QUICKINTR: 1060 wait = CMD_WAIT; 1061 break; 1062 1063 case ACT_IO: 1064 wait = DATA_WAIT; 1065 break; 1066 1067 case ACT_RESET: 1068 goto reset; 1069 1070 case ACT_DONE: 1071 r = sc->sc_stat[0]; 1072 goto done; 1073 1074 case ACT_ERROR: 1075 r = -1; 1076 goto done; 1077 1078 default: 1079 panic("espicmd action"); 1080 } 1081 } 1082 reset: 1083 espreset(sc, RESET_ESPCHIP); /* ??? */ 1084 r = -1; 1085 done: 1086 sc->sc_state = S_IDLE; 1087 s = splbio(); 1088 if (sc->sc_iwant) { 1089 sc->sc_iwant = 0; 1090 wakeup((caddr_t)&sc->sc_iwant); 1091 } else if ((sq = sc->sc_hba.hba_head) != NULL) { 1092 sc->sc_hba.hba_head = sq->sq_forw; 1093 (*sq->sq_dgo)(sq->sq_dev, &sc->sc_cdbspace); 1094 } else 1095 sc->sc_hba.hba_busy = 0; 1096 splx(s); 1097 return (r); 1098 } 1099 1100 /* 1101 * Dump (write memory, possibly physmem). 1102 * SPARC higher-level dump code always provides virtual addresses, 1103 * so we need not do any I/O mapping here. 1104 */ 1105 int 1106 espdump(hba, targ, cdb, buf, len) 1107 register struct hba_softc *hba; 1108 int targ; 1109 struct scsi_cdb *cdb; 1110 caddr_t buf; 1111 register int len; 1112 { 1113 register struct esp_softc *sc = (struct esp_softc *)hba; 1114 1115 /* 1116 * If we crashed in the middle of a bus transaction... 1117 */ 1118 if (sc->sc_state != S_IDLE) 1119 espreset(sc, RESET_BOTH); /* ??? */ 1120 return (espicmd(hba, targ, cdb, buf, len, B_WRITE)); 1121 } 1122 1123 /* 1124 * Allocate resources (SCSI bus and DVMA space) for the given transfer. 1125 * Must be called at splbio(). 1126 * 1127 * THIS SHOULD RETURN SUCCESS/FAIL INDICATION 1128 */ 1129 void 1130 espstart(self, sq, bp, dgo, dev) 1131 struct device *self; 1132 register struct sq *sq; 1133 struct buf *bp; 1134 scdgo_fn dgo; 1135 struct device *dev; 1136 { 1137 register struct esp_softc *sc = (struct esp_softc *)self; 1138 1139 if (sc->sc_hba.hba_busy == 0) { 1140 /* 1141 * Bus not busy, nothing to do here, just tell 1142 * this target or unit that it has the SCSI bus. 1143 */ 1144 sc->sc_hba.hba_busy = 1; 1145 (*dgo)(dev, &sc->sc_cdbspace); 1146 } else { 1147 /* 1148 * Bus is busy; just enqueue. 1149 */ 1150 sq->sq_dgo = dgo; 1151 sq->sq_dev = dev; 1152 sq->sq_forw = NULL; 1153 if (sc->sc_hba.hba_head == NULL) 1154 sc->sc_hba.hba_head = sq; 1155 else 1156 sc->sc_hba.hba_tail->sq_forw = sq; 1157 sc->sc_hba.hba_tail = sq; 1158 } 1159 } 1160 1161 /* 1162 * Start buffered I/O. 1163 * Return 0 on success, 1 on failure. 1164 */ 1165 int 1166 espgo(self, targ, intr, dev, bp, pad) 1167 struct device *self; 1168 int targ; 1169 scintr_fn intr; 1170 struct device *dev; 1171 register struct buf *bp; 1172 int pad; 1173 { 1174 register struct esp_softc *sc = (struct esp_softc *)self; 1175 1176 /* Set up dma control for espact(). */ 1177 sc->sc_dmactl = bp->b_flags & B_READ ? 1178 DMA_ENA | DMA_READ | DMA_IE : DMA_ENA | DMA_IE; 1179 sc->sc_dmaaddr = (u_long)bp->b_un.b_addr; 1180 sc->sc_resid = bp->b_bcount; 1181 1182 /* 1183 * Enable interrupts and start selection. 1184 * The rest is done in espintr() and espact(). 1185 */ 1186 sc->sc_hba.hba_intr = intr; /* remember dev done function */ 1187 sc->sc_hba.hba_intrdev = dev; /* and its first arg */ 1188 sc->sc_dma->dma_csr = DMA_IE; 1189 espselect(sc, targ, &sc->sc_cdbspace); 1190 return (0); 1191 } 1192 1193 /* 1194 * Handle interrupt. Return 1 if taken. 1195 */ 1196 int 1197 espintr(sc0) 1198 void *sc0; 1199 { 1200 register struct esp_softc *sc = (struct esp_softc *)sc0; 1201 register volatile struct espreg *esp = sc->sc_esp; 1202 register volatile struct dmareg *dma = sc->sc_dma; 1203 register int r, wait; 1204 register struct sq *sq; 1205 1206 r = dma->dma_csr; 1207 if (!DMA_INTR(r)) 1208 return (0); /* not ours */ 1209 sc->sc_intrcnt.ev_count++; 1210 1211 again: 1212 sc->sc_espstat = esp->esp_stat; 1213 sc->sc_espstep = esp->esp_step & ESPSTEP_MASK; 1214 sc->sc_espintr = esp->esp_intr; 1215 sc->sc_espfflags = esp->esp_fflags; 1216 sc->sc_dmacsr = r; 1217 1218 if (sc->sc_state == S_IDLE) { 1219 printf("%s: stray interrupt\n", sc->sc_dev.dv_xname); 1220 dma->dma_csr &= ~DMA_IE; /* ??? */ 1221 return (1); 1222 } 1223 switch (r = espact(sc)) { 1224 1225 case ACT_CONT: /* just return */ 1226 case ACT_IO: 1227 break; 1228 1229 case ACT_RESET: /* please reset esp */ 1230 reset: 1231 espreset(sc, RESET_ESPCHIP); /* ??? */ 1232 /* FALLTHROUGH */ 1233 1234 case ACT_DONE: /* this one is done, successfully */ 1235 case ACT_ERROR: /* this one is done due to `severe' error */ 1236 if (!sc->sc_hba.hba_busy) 1237 panic("espintr sq"); 1238 /* 1239 * This transaction is done. Call the driver's intr routine. 1240 * If an immediate command is pending, let it run in front 1241 * of us, otherwise start the next transation. Note that 1242 * the interrupt routine may run its own immediate commands 1243 * (`request sense' for errors, eg) before we get around to 1244 * the process waiting to do immediate command, but that 1245 * is OK; if we did not set S_IDLE here we could deadlock. 1246 */ 1247 sc->sc_state = S_IDLE; 1248 (*sc->sc_hba.hba_intr)(sc->sc_hba.hba_intrdev, 1249 r == ACT_DONE ? sc->sc_stat[0] : -1, sc->sc_resid); 1250 if (sc->sc_iwant) { 1251 wakeup((caddr_t)&sc->sc_iwant); 1252 sc->sc_iwant = 0; 1253 } else if ((sq = sc->sc_hba.hba_head) != NULL) { 1254 sc->sc_hba.hba_head = sq->sq_forw; 1255 (*sq->sq_dgo)(sq->sq_dev, &sc->sc_cdbspace); 1256 } else 1257 sc->sc_hba.hba_busy = 0; 1258 break; 1259 1260 case ACT_QUICKINTR: /* wait a short while for another interrupt */ 1261 printf("%s: quickintr: ", sc->sc_dev.dv_xname); 1262 wait = 100; 1263 do { 1264 r = dma->dma_csr; 1265 if (DMA_INTR(r)) { 1266 printf("got one, wait=%d\n", wait); 1267 goto again; 1268 } 1269 } while (--wait > 0); 1270 printf("did not get one\n"); 1271 break; 1272 1273 default: 1274 panic("espintr action"); 1275 } 1276 return (1); 1277 } 1278 1279 /* 1280 * Target or unit decided to let go of the bus early. 1281 */ 1282 void 1283 esprel(self) 1284 struct device *self; 1285 { 1286 register struct esp_softc *sc = (struct esp_softc *)self; 1287 register struct sq *sq; 1288 1289 /* if there is someone else waiting, give them a crack at it */ 1290 if (sc->sc_iwant) { 1291 wakeup((caddr_t)&sc->sc_iwant); 1292 sc->sc_iwant = 0; 1293 } else if ((sq = sc->sc_hba.hba_head) != NULL) { 1294 sc->sc_hba.hba_head = sq->sq_forw; 1295 (*sq->sq_dgo)(sq->sq_dev, &sc->sc_cdbspace); 1296 } else 1297 sc->sc_hba.hba_busy = 0; 1298 } 1299