109741ed9Storek /* 21fd2d6dbSbostic * Copyright (c) 1988, 1992, 1993 31fd2d6dbSbostic * The Regents of the University of California. All rights reserved. 409741ed9Storek * 509741ed9Storek * This software was developed by the Computer Systems Engineering group 609741ed9Storek * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 709741ed9Storek * contributed to Berkeley. 809741ed9Storek * 9552ae0faSbostic * All advertising materials mentioning features or use of this software 10552ae0faSbostic * must display the following acknowledgement: 11552ae0faSbostic * This product includes software developed by the University of 128939e7d1Storek * California, Lawrence Berkeley Laboratory. 13552ae0faSbostic * 1409741ed9Storek * %sccs.include.redist.c% 1509741ed9Storek * 16*e578ec4aStorek * @(#)espreg.h 8.2 (Berkeley) 12/14/93 1709741ed9Storek * 188939e7d1Storek * from: $Header: espreg.h,v 1.7 92/11/26 02:28:10 torek Exp $ (LBL) 1909741ed9Storek * 2009741ed9Storek * Derived from Mary Baker's devSCSIC90.c from the Berkeley 2109741ed9Storek * Sprite project, which is: 2209741ed9Storek * 2309741ed9Storek * Copyright 1988 Regents of the University of California 2409741ed9Storek * Permission to use, copy, modify, and distribute this 2509741ed9Storek * software and its documentation for any purpose and without 2609741ed9Storek * fee is hereby granted, provided that the above copyright 2709741ed9Storek * notice appear in all copies. The University of California 2809741ed9Storek * makes no representations about the suitability of this 2909741ed9Storek * software for any purpose. It is provided "as is" without 3009741ed9Storek * express or implied warranty. 3109741ed9Storek */ 3209741ed9Storek 3309741ed9Storek /* 3409741ed9Storek * Emulex ESP100, ESP100A, and ESP200 registers, as found on the 3509741ed9Storek * Sun-4c Sbus. 3609741ed9Storek * 3709741ed9Storek * The registers are all bytes, and all on longword boundaries. 3809741ed9Storek * Grody to the max! 3909741ed9Storek */ 4009741ed9Storek struct espreg { 4109741ed9Storek u_char esp_tcl; /* transfer count low (byte 0) (rw) */ 4209741ed9Storek u_char esp_xxx0[3]; 4309741ed9Storek u_char esp_tch; /* transfer count high (byte 1) (rw) */ 4409741ed9Storek u_char esp_xxx1[3]; 4509741ed9Storek u_char esp_fifo; /* fifo data register (rw) */ 4609741ed9Storek u_char esp_xxx2[3]; 4709741ed9Storek u_char esp_cmd; /* command (rw) */ 4809741ed9Storek u_char esp_xxx3[3]; 4909741ed9Storek u_char esp_stat; /* status (ro); scsi id (wo) */ 5009741ed9Storek #define esp_id esp_stat 5109741ed9Storek u_char esp_xxx4[3]; 5209741ed9Storek u_char esp_intr; /* interrupt (ro); timeout (wo) */ 5309741ed9Storek #define esp_timeout esp_intr 5409741ed9Storek u_char esp_xxx5[3]; 5509741ed9Storek u_char esp_step; /* sequence step (ro); sync period (wo) */ 5609741ed9Storek #define esp_syncperiod esp_step 5709741ed9Storek u_char esp_xxx6[3]; 5809741ed9Storek u_char esp_fflags; /* fifo flags (ro); sync offset (wo) */ 5909741ed9Storek #define esp_syncoff esp_fflags 6009741ed9Storek u_char esp_xxx7[3]; 6109741ed9Storek u_char esp_conf1; /* configuration #1 (rw) */ 6209741ed9Storek u_char esp_xxx8[3]; 6309741ed9Storek u_char esp_ccf; /* clock conversion factor (wo) */ 6409741ed9Storek u_char esp_xxx9[3]; 6509741ed9Storek u_char esp_test; /* test (do not use) */ 6609741ed9Storek u_char esp_xxxA[3]; 67*e578ec4aStorek u_char esp_conf2; /* configuration #2 (rw, ESP100A/2xx) */ 6809741ed9Storek u_char esp_xxxB[3]; 6909741ed9Storek u_char esp_conf3; /* configuration #3 (rw, ESP-236) */ 7009741ed9Storek u_char esp_xxxC[3]; 7109741ed9Storek }; 7209741ed9Storek 7309741ed9Storek /* THE REST OF THESE NAMES COULD STAND TO BE SHORTENED */ 7409741ed9Storek 7509741ed9Storek /* 7609741ed9Storek * Bits in esp_cmd. Note that the cmd register is two levels deep (see 7709741ed9Storek * Emulex documentation, p. 4-3); our typical usage is to set the command, 7809741ed9Storek * then set it again with DMA. 7909741ed9Storek * 8009741ed9Storek * Targets will use disconnected and target mode commands; initiators will use 8109741ed9Storek * disconnected and initiator mode commands. Bit 0x40 indicates disconnected 8209741ed9Storek * mode, 0x20 target mode, and 0x10 initiator mode. (However, everyone can 8309741ed9Storek * use the miscellaneous commands, which have none of those bits set.) 8409741ed9Storek */ 8509741ed9Storek #define ESPCMD_DMA 0x80 /* flag => do DMA */ 8609741ed9Storek 8709741ed9Storek /* miscellaneous */ 8809741ed9Storek #define ESPCMD_NOP 0x00 /* do nothing */ 8909741ed9Storek #define ESPCMD_FLUSH_FIFO 0x01 /* flush FIFO */ 9009741ed9Storek #define ESPCMD_RESET_CHIP 0x02 /* reset ESP chip */ 9109741ed9Storek #define ESPCMD_RESET_BUS 0x03 /* reset SCSI bus */ 92*e578ec4aStorek /* NB: fifo flush takes time, may need delay or NOP to allow completion */ 9309741ed9Storek 9409741ed9Storek /* disconnected */ 9509741ed9Storek #define ESPCMD_RESEL_SEQ 0x40 /* reselect sequence */ 9609741ed9Storek #define ESPCMD_SEL_NATN 0x41 /* select without ATN sequence */ 9709741ed9Storek #define ESPCMD_SEL_ATN 0x42 /* select with ATN sequence */ 9809741ed9Storek #define ESPCMD_SEL_ATNS 0x43 /* select with ATN & stop seq */ 9909741ed9Storek #define ESPCMD_SEL_ENA 0x44 /* enable selection/reselection */ 10009741ed9Storek #define ESPCMD_SEL_DIS 0x45 /* disable selection/reselection */ 10109741ed9Storek #define ESPCMD_SEL_ATN3 0x46 /* select with ATN3 sequence */ 10209741ed9Storek 10309741ed9Storek /* target state */ 10409741ed9Storek #define ESPCMD_SEND_MSG 0x20 /* send message */ 10509741ed9Storek #define ESPCMD_SEND_STATUS 0x21 /* send status */ 10609741ed9Storek #define ESPCMD_SEND_DATA 0x22 /* send data */ 10709741ed9Storek #define ESPCMD_DIS_SEQ 0x23 /* disconnect sequence */ 10809741ed9Storek #define ESPCMD_TERM_SEQ 0x24 /* terminate sequence */ 10909741ed9Storek #define ESPCMD_TARG_COMP 0x25 /* target command complete sequence */ 11009741ed9Storek #define ESPCMD_DISCONNECT 0x27 /* disconnect */ 11109741ed9Storek #define ESPCMD_RCV_MSG 0x28 /* receive message sequence */ 11209741ed9Storek #define ESPCMD_RCV_CMD 0x29 /* receive command */ 11309741ed9Storek #define ESPCMD_RCV_DATA 0x2a /* receive data */ 11409741ed9Storek #define ESPCMD_REC_CMD_SEQ 0x2b /* receive command sequence */ 11509741ed9Storek #define ESPCMD_STOP_DMA 0x04 /* stop DMA (see p. 4-6) */ 11609741ed9Storek /* ESPCMD_TARG_ABORT 0x06 target abort sequence */ 11709741ed9Storek 11809741ed9Storek /* initiator state */ 11909741ed9Storek #define ESPCMD_XFER_INFO 0x10 /* transfer information */ 12009741ed9Storek #define ESPCMD_INIT_COMP 0x11 /* initiator command complete seq */ 12109741ed9Storek #define ESPCMD_MSG_ACCEPT 0x12 /* message accepted */ 12209741ed9Storek #define ESPCMD_XFER_PAD 0x18 /* transfer pad (use only w/ DMA) */ 12309741ed9Storek #define ESPCMD_SET_ATN 0x1a /* set ATN */ 12409741ed9Storek #define ESPCMD_RESET_ATN 0x1b /* reset ATN */ 12509741ed9Storek 12609741ed9Storek /* 12709741ed9Storek * Bits in esp_stat. 12809741ed9Storek * Bits 3 through 7 are latched until esp_intr is read; 12909741ed9Storek * bits 0 through 2 (the phase) are not normally latched. 13009741ed9Storek * The interrupt bit is set even if interrupts are disabled. 13109741ed9Storek * Hardware or software reset, or reading esp_intr, will 13209741ed9Storek * clear the interrupt and turn off ESPSTAT_INT. 13309741ed9Storek */ 13409741ed9Storek #ifdef notdef 13509741ed9Storek #define ESPSTAT_INT 0x80 /* ASC interrupting processor */ 13609741ed9Storek #else 13709741ed9Storek #define ESPSTAT_XXX 0x80 /* rumored unreliable: use dma IP */ 13809741ed9Storek #endif 13909741ed9Storek #define ESPSTAT_GE 0x40 /* gross error */ 14009741ed9Storek #define ESPSTAT_PE 0x20 /* parity error */ 14109741ed9Storek #define ESPSTAT_ERR 0x60 /* pseudo composite */ 14209741ed9Storek #define ESPSTAT_TC 0x10 /* terminal count */ 14309741ed9Storek #define ESPSTAT_VGC 0x08 /* valid group code */ 14409741ed9Storek #define ESPSTAT_MSG 0x04 /* MSG line from SCSI bus */ 14509741ed9Storek #define ESPSTAT_CD 0x02 /* CD line from SCSI bus */ 14609741ed9Storek #define ESPSTAT_IO 0x01 /* IO line from SCSI bus */ 14709741ed9Storek #define ESPSTAT_PHASE 7 /* phase mask */ 14809741ed9Storek #define ESPPHASE_DATA_OUT 0 /* data out */ 14909741ed9Storek #define ESPPHASE_DATA_IN 1 /* data in */ 15009741ed9Storek #define ESPPHASE_CMD 2 /* command */ 15109741ed9Storek #define ESPPHASE_STATUS 3 /* status */ 15209741ed9Storek #define ESPPHASE_MSG_OUT 6 /* message out (w.r.t. initiator) */ 15309741ed9Storek #define ESPPHASE_MSG_IN 7 /* message in */ 15409741ed9Storek 15509741ed9Storek #ifdef ESP_PHASE_NAMES 15609741ed9Storek /* printed as `... during %s phase' */ 15709741ed9Storek char *espphases[] = 15809741ed9Storek { "data out", "data in", "command", "status", 15909741ed9Storek "impossible(4)", "impossible(5)", "message out", "message in" }; 16009741ed9Storek #endif 16109741ed9Storek 16209741ed9Storek #define ESPSTAT_BITS "\20\10INT\7GE\6PE\5TC\4VGC\3MSG\2CD\1IO" 16309741ed9Storek 16409741ed9Storek /* 16509741ed9Storek * Bits in esp_intr. 16609741ed9Storek */ 16709741ed9Storek #define ESPINTR_SBR 0x80 /* SCSI bus reset detected */ 16809741ed9Storek #define ESPINTR_ILC 0x40 /* illegal command */ 16909741ed9Storek #define ESPINTR_DSC 0x20 /* target disconnected, or timeout */ 17009741ed9Storek #define ESPINTR_SVC 0x10 /* a device wants bus service */ 17109741ed9Storek #define ESPINTR_CMP 0x08 /* function complete */ 17209741ed9Storek #define ESPINTR_RSL 0x04 /* reselected */ 17309741ed9Storek #define ESPINTR_SAT 0x02 /* selected with ATN */ 17409741ed9Storek #define ESPINTR_SEL 0x01 /* selected (no ATN) */ 17509741ed9Storek 17609741ed9Storek #define ESPINTR_BITS "\20\10SBR\7ILC\6DSC\5SVC\4CMP\3RSL\2SAT\1SEL" 17709741ed9Storek 17809741ed9Storek /* 17909741ed9Storek * Formula for select/reselect timeout (esp_timeout). 18009741ed9Storek * TU = 7682 * CCF * TCP 18109741ed9Storek * T / TU = register value 18209741ed9Storek * CCF = clock conversion factor 18309741ed9Storek * TCP = input clock period (in same units as T) 18409741ed9Storek * TU = time unit (i.e., the esp_timeout register counts in TUs) 18509741ed9Storek * T = desired timeout 18609741ed9Storek * (i.e., we want ceil(timeout / (7682*ccf*tcp))). If timeout is in ms., 18709741ed9Storek * and tcp is in MHz, then (ccf * 7682)/tcp gives us 1000*TU, and 18809741ed9Storek * 1000*timeout/(1000*TU) gives us our result (but remember to round up). 18909741ed9Storek * 19009741ed9Storek * N.B.: The register value 0 gives a TU of 256. 19109741ed9Storek */ 19209741ed9Storek #define ESPTIMO_REGVAL(timo_ms, ccf, mhz) \ 19309741ed9Storek howmany(1000 * (timo_ms), ((ccf) * 7682) / (mhz)) 19409741ed9Storek 19509741ed9Storek /* 19609741ed9Storek * Value in esp_step. These tell us how much of a `sequence' completed, 19709741ed9Storek * and apply to the following sequenced operations: 19809741ed9Storek * [initiator] 19909741ed9Storek * select without ATN 20009741ed9Storek * select with ATN 20109741ed9Storek * select with ATN3 20209741ed9Storek * select with ATN and stop 20309741ed9Storek * [target] 20409741ed9Storek * bus-initiated select with ATN 20509741ed9Storek * bus-initiated select 20609741ed9Storek * receive command sequence 20709741ed9Storek * command complete sequence 20809741ed9Storek * disconnect sequence 20909741ed9Storek * terminate sequence 21009741ed9Storek * The actual values are too complicated to define here, except that 21109741ed9Storek * code 4 always means `everything worked and the command went out' 21209741ed9Storek * (and is thus typical for everything except ATN-and-stop). 21309741ed9Storek */ 21409741ed9Storek #define ESPSTEP_MASK 0x07 /* only these bits are valid */ 21509741ed9Storek #define ESPSTEP_DONE 4 /* command went out */ 21609741ed9Storek 21709741ed9Storek /* 218*e578ec4aStorek * Synchronous transfer period (esp_syncperiod, 5 bits). 21909741ed9Storek * The minimum clocks-per-period is 5 and the max is 35; 22009741ed9Storek * the default on reset is 5. Note that a period value of 4 22109741ed9Storek * actually gives 5 clocks. 22209741ed9Storek */ 22309741ed9Storek #define ESP_CLOCKS_TO_PERIOD(nclocks) ((nclocks) & 31) 22409741ed9Storek 22509741ed9Storek /* 22609741ed9Storek * Bits in fifo flags (esp_fflags) register. The FIFO itself 22709741ed9Storek * is only 16 bytes, so the byte count fits in 5 bits. Normally 22809741ed9Storek * a copy of the sequence step register appears in the top 3 bits, 22909741ed9Storek * but in test mode the chip re-uses one of those for a synchronous 230*e578ec4aStorek * offset bit; in any case, they are pretty much worthless. 231*e578ec4aStorek * 232*e578ec4aStorek * Note that the fifo flags register must not be read while the 233*e578ec4aStorek * fifo is changing. 23409741ed9Storek */ 235*e578ec4aStorek #define ESP_NFIFO(fflags) ((fflags) & 0x1f) 23609741ed9Storek 23709741ed9Storek #define ESPFFLAGS_TM_SOFFNZ 0x20 /* nonzero sync offset (test mode) */ 23809741ed9Storek 23909741ed9Storek /* 24009741ed9Storek * Bits in esp_conf1. 24109741ed9Storek */ 24209741ed9Storek #define ESPCONF1_SLOW_CABLE 0x80 /* ``slow cable'' mode */ 24309741ed9Storek #define ESPCONF1_REPORT 0x40 /* disable reporting of interrupts 24409741ed9Storek from scsi bus reset command */ 24509741ed9Storek #define ESPCONF1_PARTST 0x20 /* parity test mode */ 24609741ed9Storek #define ESPCONF1_PARENB 0x10 /* enable parity */ 24709741ed9Storek #define ESPCONF1_TEST 0x08 /* chip test mode */ 24809741ed9Storek #define ESPCONF1_ID_MASK 0x07 /* SCSI bus ID field */ 24909741ed9Storek 25009741ed9Storek #define ESPCONF1_BITS "\20\10SLOW_CABLE\7REPORT\6PARTST\5PARENB\4TEST" 25109741ed9Storek 25209741ed9Storek /* 25309741ed9Storek * Values for clock conversion factor (esp_ccf). 25409741ed9Storek */ 25509741ed9Storek #define ESPCCF_FROMMHZ(mhz) (((mhz) + 4) / 5) 25609741ed9Storek #define ESPCCF_MIN 2 /* minimum CCF value */ 25709741ed9Storek 25809741ed9Storek /* 25909741ed9Storek * Bits in esp_test (for board testing only; can only be used in test mode). 26009741ed9Storek */ 26109741ed9Storek #define ESPTEST_MBZ 0xf8 /* reserved; must be 0 */ 26209741ed9Storek #define ESPTEST_TRISTATE 0x04 /* all output pins tristated */ 26309741ed9Storek #define ESPTEST_INITIATOR 0x02 /* operate as initiator */ 26409741ed9Storek #define ESPTEST_TARGET 0x01 /* operate as target */ 26509741ed9Storek 26609741ed9Storek /* 26709741ed9Storek * Bits in esp_conf2. 26809741ed9Storek */ 26909741ed9Storek #define ESPCONF2_RSVD 0xe0 /* reserved */ 27009741ed9Storek #define ESPCONF2_TRISTATE_DMA 0x10 /* tristate the DMA REQ pin */ 27109741ed9Storek #define ESPCONF2_SCSI2 0x08 /* enable SCSI 2 (see p. 4-18) */ 27209741ed9Storek #define ESPCONF2_TBPA 0x04 /* enable target bad parity abort */ 27309741ed9Storek #define ESPCONF2_RPE 0x02 /* register parity ena (ESP2xx only) */ 27409741ed9Storek #define ESPCONF2_DPE 0x01 /* DMA parity enable (ESP2xx only) */ 275