179e0c2b1Storek /*- 21fd2d6dbSbostic * Copyright (c) 1982, 1992, 1993 31fd2d6dbSbostic * The Regents of the University of California. All rights reserved. 479e0c2b1Storek * 579e0c2b1Storek * %sccs.include.redist.c% 679e0c2b1Storek * 7*9cef2f72Storek * @(#)if_lereg.h 8.2 (Berkeley) 10/30/93 879e0c2b1Storek * 9*9cef2f72Storek * from: $Header: if_lereg.h,v 1.7 93/10/31 04:41:00 leres Locked $ 1079e0c2b1Storek */ 1179e0c2b1Storek 1279e0c2b1Storek #define LEMTU 1518 1379e0c2b1Storek #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 1479e0c2b1Storek #define LERBUF 8 1579e0c2b1Storek #define LERBUFLOG2 3 1679e0c2b1Storek #define LE_RLEN (LERBUFLOG2 << 13) 1779e0c2b1Storek #define LETBUF 1 1879e0c2b1Storek #define LETBUFLOG2 0 1979e0c2b1Storek #define LE_TLEN (LETBUFLOG2 << 13) 2079e0c2b1Storek 2179e0c2b1Storek /* Local Area Network Controller for Ethernet (LANCE) registers */ 2279e0c2b1Storek struct lereg1 { 2379e0c2b1Storek u_short ler1_rdp; /* register data port */ 2479e0c2b1Storek u_short ler1_rap; /* register address port */ 2579e0c2b1Storek }; 2679e0c2b1Storek 2779e0c2b1Storek /* register addresses */ 2879e0c2b1Storek #define LE_CSR0 0 /* Control and status register */ 2979e0c2b1Storek #define LE_CSR1 1 /* low address of init block */ 3079e0c2b1Storek #define LE_CSR2 2 /* high address of init block */ 3179e0c2b1Storek #define LE_CSR3 3 /* Bus master and control */ 3279e0c2b1Storek 3379e0c2b1Storek /* Control and status register 0 (csr0) */ 3479e0c2b1Storek #define LE_C0_ERR 0x8000 /* error summary */ 3579e0c2b1Storek #define LE_C0_BABL 0x4000 /* transmitter timeout error */ 3679e0c2b1Storek #define LE_C0_CERR 0x2000 /* collision */ 3779e0c2b1Storek #define LE_C0_MISS 0x1000 /* missed a packet */ 3879e0c2b1Storek #define LE_C0_MERR 0x0800 /* memory error */ 3979e0c2b1Storek #define LE_C0_RINT 0x0400 /* receiver interrupt */ 4079e0c2b1Storek #define LE_C0_TINT 0x0200 /* transmitter interrupt */ 4179e0c2b1Storek #define LE_C0_IDON 0x0100 /* initalization done */ 4279e0c2b1Storek #define LE_C0_INTR 0x0080 /* interrupt condition */ 4379e0c2b1Storek #define LE_C0_INEA 0x0040 /* interrupt enable */ 4479e0c2b1Storek #define LE_C0_RXON 0x0020 /* receiver on */ 4579e0c2b1Storek #define LE_C0_TXON 0x0010 /* transmitter on */ 4679e0c2b1Storek #define LE_C0_TDMD 0x0008 /* transmit demand */ 4779e0c2b1Storek #define LE_C0_STOP 0x0004 /* disable all external activity */ 4879e0c2b1Storek #define LE_C0_STRT 0x0002 /* enable external activity */ 4979e0c2b1Storek #define LE_C0_INIT 0x0001 /* begin initalization */ 5079e0c2b1Storek 5179e0c2b1Storek #define LE_C0_BITS \ 5279e0c2b1Storek "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\ 5379e0c2b1Storek \12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT" 5479e0c2b1Storek 5579e0c2b1Storek /* Control and status register 3 (csr3) */ 5679e0c2b1Storek #define LE_C3_BSWP 0x4 /* byte swap */ 5779e0c2b1Storek #define LE_C3_ACON 0x2 /* ALE control, eh? */ 5879e0c2b1Storek #define LE_C3_BCON 0x1 /* byte control */ 5979e0c2b1Storek /* 6079e0c2b1Storek * Current size is 13,758 bytes with 8 x 1518 receive buffers and 6179e0c2b1Storek * 1 x 1518 transmit buffer. 6279e0c2b1Storek */ 6379e0c2b1Storek struct lereg2 { 6479e0c2b1Storek /* initialization block */ 65*9cef2f72Storek u_short ler2_mode; /* mode */ 66*9cef2f72Storek u_char ler2_padr[6]; /* physical address */ 67*9cef2f72Storek u_short ler2_ladrf[4]; /* logical address filter */ 68*9cef2f72Storek u_short ler2_rdra; /* receive descriptor addr */ 69*9cef2f72Storek u_short ler2_rlen; /* rda high and ring size */ 70*9cef2f72Storek u_short ler2_tdra; /* transmit descriptor addr */ 71*9cef2f72Storek u_short ler2_tlen; /* tda high and ring size */ 7279e0c2b1Storek /* receive message descriptors. bits/hadr are byte order dependent. */ 73*9cef2f72Storek struct lermd { 7479e0c2b1Storek u_short rmd0; /* low address of packet */ 7579e0c2b1Storek u_char rmd1_bits; /* descriptor bits */ 7679e0c2b1Storek u_char rmd1_hadr; /* high address of packet */ 7779e0c2b1Storek short rmd2; /* buffer byte count */ 7879e0c2b1Storek u_short rmd3; /* message byte count */ 7979e0c2b1Storek } ler2_rmd[LERBUF]; 8079e0c2b1Storek /* transmit message descriptors */ 81*9cef2f72Storek struct letmd { 8279e0c2b1Storek u_short tmd0; /* low address of packet */ 8379e0c2b1Storek u_char tmd1_bits; /* descriptor bits */ 8479e0c2b1Storek u_char tmd1_hadr; /* high address of packet */ 8579e0c2b1Storek short tmd2; /* buffer byte count */ 8679e0c2b1Storek u_short tmd3; /* transmit error bits */ 8779e0c2b1Storek } ler2_tmd[LETBUF]; 88*9cef2f72Storek char ler2_rbuf[LERBUF][LEMTU]; 89*9cef2f72Storek char ler2_tbuf[LETBUF][LEMTU]; 9079e0c2b1Storek }; 9179e0c2b1Storek 9279e0c2b1Storek /* Initialzation block (mode) */ 9379e0c2b1Storek #define LE_MODE_PROM 0x8000 /* promiscuous mode */ 9479e0c2b1Storek /* 0x7f80 reserved, must be zero */ 9579e0c2b1Storek #define LE_MODE_INTL 0x0040 /* internal loopback */ 9679e0c2b1Storek #define LE_MODE_DRTY 0x0020 /* disable retry */ 9779e0c2b1Storek #define LE_MODE_COLL 0x0010 /* force a collision */ 9879e0c2b1Storek #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */ 9979e0c2b1Storek #define LE_MODE_LOOP 0x0004 /* loopback mode */ 10079e0c2b1Storek #define LE_MODE_DTX 0x0002 /* disable transmitter */ 10179e0c2b1Storek #define LE_MODE_DRX 0x0001 /* disable receiver */ 10279e0c2b1Storek #define LE_MODE_NORMAL 0 /* none of the above */ 10379e0c2b1Storek 10479e0c2b1Storek 10579e0c2b1Storek /* Receive message descriptor 1 (rmd1_bits) */ 10679e0c2b1Storek #define LE_R1_OWN 0x80 /* LANCE owns the packet */ 10779e0c2b1Storek #define LE_R1_ERR 0x40 /* error summary */ 10879e0c2b1Storek #define LE_R1_FRAM 0x20 /* framing error */ 10979e0c2b1Storek #define LE_R1_OFLO 0x10 /* overflow error */ 11079e0c2b1Storek #define LE_R1_CRC 0x08 /* CRC error */ 11179e0c2b1Storek #define LE_R1_BUFF 0x04 /* buffer error */ 11279e0c2b1Storek #define LE_R1_STP 0x02 /* start of packet */ 11379e0c2b1Storek #define LE_R1_ENP 0x01 /* end of packet */ 11479e0c2b1Storek 11579e0c2b1Storek #define LE_R1_BITS \ 11679e0c2b1Storek "\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP" 11779e0c2b1Storek 11879e0c2b1Storek /* Transmit message descriptor 1 (tmd1_bits) */ 11979e0c2b1Storek #define LE_T1_OWN 0x80 /* LANCE owns the packet */ 12079e0c2b1Storek #define LE_T1_ERR 0x40 /* error summary */ 12179e0c2b1Storek #define LE_T1_MORE 0x10 /* multiple collisions */ 12279e0c2b1Storek #define LE_T1_ONE 0x08 /* single collision */ 12379e0c2b1Storek #define LE_T1_DEF 0x04 /* defferred transmit */ 12479e0c2b1Storek #define LE_T1_STP 0x02 /* start of packet */ 12579e0c2b1Storek #define LE_T1_ENP 0x01 /* end of packet */ 12679e0c2b1Storek 12779e0c2b1Storek #define LE_T1_BITS \ 12879e0c2b1Storek "\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP" 12979e0c2b1Storek 13079e0c2b1Storek /* Transmit message descriptor 3 (tmd3) */ 13179e0c2b1Storek #define LE_T3_BUFF 0x8000 /* buffer error */ 13279e0c2b1Storek #define LE_T3_UFLO 0x4000 /* underflow error */ 13379e0c2b1Storek #define LE_T3_LCOL 0x1000 /* late collision */ 13479e0c2b1Storek #define LE_T3_LCAR 0x0800 /* loss of carrier */ 13579e0c2b1Storek #define LE_T3_RTRY 0x0400 /* retry error */ 13679e0c2b1Storek #define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */ 13779e0c2b1Storek 13879e0c2b1Storek #define LE_T3_BITS \ 13979e0c2b1Storek "\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY" 140