1 /*- 2 * Copyright (c) 1982, 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * @(#)if_lereg.h 8.1 (Berkeley) 06/11/93 8 * 9 * from: $Header: if_lereg.h,v 1.6 92/11/26 02:28:12 torek Exp $ 10 */ 11 12 #define LEMTU 1518 13 #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 14 #define LERBUF 8 15 #define LERBUFLOG2 3 16 #define LE_RLEN (LERBUFLOG2 << 13) 17 #define LETBUF 1 18 #define LETBUFLOG2 0 19 #define LE_TLEN (LETBUFLOG2 << 13) 20 21 /* Local Area Network Controller for Ethernet (LANCE) registers */ 22 struct lereg1 { 23 u_short ler1_rdp; /* register data port */ 24 u_short ler1_rap; /* register address port */ 25 }; 26 27 /* register addresses */ 28 #define LE_CSR0 0 /* Control and status register */ 29 #define LE_CSR1 1 /* low address of init block */ 30 #define LE_CSR2 2 /* high address of init block */ 31 #define LE_CSR3 3 /* Bus master and control */ 32 33 /* Control and status register 0 (csr0) */ 34 #define LE_C0_ERR 0x8000 /* error summary */ 35 #define LE_C0_BABL 0x4000 /* transmitter timeout error */ 36 #define LE_C0_CERR 0x2000 /* collision */ 37 #define LE_C0_MISS 0x1000 /* missed a packet */ 38 #define LE_C0_MERR 0x0800 /* memory error */ 39 #define LE_C0_RINT 0x0400 /* receiver interrupt */ 40 #define LE_C0_TINT 0x0200 /* transmitter interrupt */ 41 #define LE_C0_IDON 0x0100 /* initalization done */ 42 #define LE_C0_INTR 0x0080 /* interrupt condition */ 43 #define LE_C0_INEA 0x0040 /* interrupt enable */ 44 #define LE_C0_RXON 0x0020 /* receiver on */ 45 #define LE_C0_TXON 0x0010 /* transmitter on */ 46 #define LE_C0_TDMD 0x0008 /* transmit demand */ 47 #define LE_C0_STOP 0x0004 /* disable all external activity */ 48 #define LE_C0_STRT 0x0002 /* enable external activity */ 49 #define LE_C0_INIT 0x0001 /* begin initalization */ 50 51 #define LE_C0_BITS \ 52 "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\ 53 \12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT" 54 55 /* Control and status register 3 (csr3) */ 56 #define LE_C3_BSWP 0x4 /* byte swap */ 57 #define LE_C3_ACON 0x2 /* ALE control, eh? */ 58 #define LE_C3_BCON 0x1 /* byte control */ 59 /* 60 * Current size is 13,758 bytes with 8 x 1518 receive buffers and 61 * 1 x 1518 transmit buffer. 62 */ 63 struct lereg2 { 64 /* initialization block */ 65 u_short ler2_mode; /* +0x0000: mode */ 66 u_char ler2_padr[6]; /* +0x0002: physical address */ 67 u_long ler2_ladrf[2]; /* +0x0008: logical address filter */ 68 u_short ler2_rdra; /* +0x0010: receive descriptor addr */ 69 u_short ler2_rlen; /* +0x0012: rda high and ring size */ 70 u_short ler2_tdra; /* +0x0014: transmit descriptor addr */ 71 u_short ler2_tlen; /* +0x0016: tda high and ring size */ 72 /* receive message descriptors. bits/hadr are byte order dependent. */ 73 struct lermd { /* +0x0018 */ 74 u_short rmd0; /* low address of packet */ 75 u_char rmd1_bits; /* descriptor bits */ 76 u_char rmd1_hadr; /* high address of packet */ 77 short rmd2; /* buffer byte count */ 78 u_short rmd3; /* message byte count */ 79 } ler2_rmd[LERBUF]; 80 /* transmit message descriptors */ 81 struct letmd { /* +0x0058 */ 82 u_short tmd0; /* low address of packet */ 83 u_char tmd1_bits; /* descriptor bits */ 84 u_char tmd1_hadr; /* high address of packet */ 85 short tmd2; /* buffer byte count */ 86 u_short tmd3; /* transmit error bits */ 87 } ler2_tmd[LETBUF]; 88 char ler2_rbuf[LERBUF][LEMTU]; /* +0x0060 */ 89 char ler2_tbuf[LETBUF][LEMTU]; /* +0x2fd0 */ 90 }; 91 92 /* Initialzation block (mode) */ 93 #define LE_MODE_PROM 0x8000 /* promiscuous mode */ 94 /* 0x7f80 reserved, must be zero */ 95 #define LE_MODE_INTL 0x0040 /* internal loopback */ 96 #define LE_MODE_DRTY 0x0020 /* disable retry */ 97 #define LE_MODE_COLL 0x0010 /* force a collision */ 98 #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */ 99 #define LE_MODE_LOOP 0x0004 /* loopback mode */ 100 #define LE_MODE_DTX 0x0002 /* disable transmitter */ 101 #define LE_MODE_DRX 0x0001 /* disable receiver */ 102 #define LE_MODE_NORMAL 0 /* none of the above */ 103 104 105 /* Receive message descriptor 1 (rmd1_bits) */ 106 #define LE_R1_OWN 0x80 /* LANCE owns the packet */ 107 #define LE_R1_ERR 0x40 /* error summary */ 108 #define LE_R1_FRAM 0x20 /* framing error */ 109 #define LE_R1_OFLO 0x10 /* overflow error */ 110 #define LE_R1_CRC 0x08 /* CRC error */ 111 #define LE_R1_BUFF 0x04 /* buffer error */ 112 #define LE_R1_STP 0x02 /* start of packet */ 113 #define LE_R1_ENP 0x01 /* end of packet */ 114 115 #define LE_R1_BITS \ 116 "\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP" 117 118 /* Transmit message descriptor 1 (tmd1_bits) */ 119 #define LE_T1_OWN 0x80 /* LANCE owns the packet */ 120 #define LE_T1_ERR 0x40 /* error summary */ 121 #define LE_T1_MORE 0x10 /* multiple collisions */ 122 #define LE_T1_ONE 0x08 /* single collision */ 123 #define LE_T1_DEF 0x04 /* defferred transmit */ 124 #define LE_T1_STP 0x02 /* start of packet */ 125 #define LE_T1_ENP 0x01 /* end of packet */ 126 127 #define LE_T1_BITS \ 128 "\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP" 129 130 /* Transmit message descriptor 3 (tmd3) */ 131 #define LE_T3_BUFF 0x8000 /* buffer error */ 132 #define LE_T3_UFLO 0x4000 /* underflow error */ 133 #define LE_T3_LCOL 0x1000 /* late collision */ 134 #define LE_T3_LCAR 0x0800 /* loss of carrier */ 135 #define LE_T3_RTRY 0x0400 /* retry error */ 136 #define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */ 137 138 #define LE_T3_BITS \ 139 "\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY" 140