148c2c6a0Storek /* 2*304a8d6dSbostic * Copyright (c) 1992, 1993 3*304a8d6dSbostic * The Regents of the University of California. All rights reserved. 448c2c6a0Storek * 548c2c6a0Storek * This software was developed by the Computer Systems Engineering group 648c2c6a0Storek * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 748c2c6a0Storek * contributed to Berkeley. 848c2c6a0Storek * 983548bb1Sbostic * All advertising materials mentioning features or use of this software 1083548bb1Sbostic * must display the following acknowledgement: 1183548bb1Sbostic * This product includes software developed by the University of 127cbc93a3Storek * California, Lawrence Berkeley Laboratory. 1383548bb1Sbostic * 1448c2c6a0Storek * %sccs.include.redist.c% 1548c2c6a0Storek * 16*304a8d6dSbostic * @(#)cache.h 8.1 (Berkeley) 06/11/93 1748c2c6a0Storek * 189dfbde0aStorek * from: $Header: cache.h,v 1.7 93/04/27 14:31:16 torek Exp $ 1948c2c6a0Storek */ 2048c2c6a0Storek 2148c2c6a0Storek /* 2248c2c6a0Storek * Sun-4 and Sun-4c virtual address cache. 2348c2c6a0Storek * 2448c2c6a0Storek * Sun-4 virtual caches come in two flavors, write-through (Sun-4c) 2548c2c6a0Storek * and write-back (Sun-4). The write-back caches are much faster 2648c2c6a0Storek * but require a bit more care. 2748c2c6a0Storek * 2848c2c6a0Storek * VAC_NONE is not actually used now, but if someone builds a physical 2948c2c6a0Storek * cache Sun-4 (or, more likely, a virtual index/physical tag cache) 3048c2c6a0Storek * everything will work (after pulling out the #ifdef notdef's: grep 3148c2c6a0Storek * for VAC_NONE to find them). 3248c2c6a0Storek */ 3348c2c6a0Storek enum vactype { VAC_NONE, VAC_WRITETHROUGH, VAC_WRITEBACK }; 3448c2c6a0Storek 359dfbde0aStorek extern enum vactype vactype; /* XXX move into cacheinfo struct */ 3648c2c6a0Storek 3748c2c6a0Storek /* 3848c2c6a0Storek * Cache tags can be written in control space, and must be set to 0 3948c2c6a0Storek * (or invalid anyway) before turning on the cache. The tags are 4048c2c6a0Storek * addressed as an array of 32-bit structures of the form: 4148c2c6a0Storek * 4248c2c6a0Storek * struct cache_tag { 4348c2c6a0Storek * u_int :7, (unused; must be zero) 4448c2c6a0Storek * ct_cid:3, (context ID) 4548c2c6a0Storek * ct_w:1, (write flag from PTE) 4648c2c6a0Storek * ct_s:1, (supervisor flag from PTE) 4748c2c6a0Storek * ct_v:1, (set => cache entry is valid) 4848c2c6a0Storek * :3, (unused; must be zero) 4948c2c6a0Storek * ct_tid:14, (cache tag ID) 5048c2c6a0Storek * :2; (unused; must be zero) 5148c2c6a0Storek * }; 5248c2c6a0Storek * 539dfbde0aStorek * The SPARCstation 1 cache sees virtual addresses as: 5448c2c6a0Storek * 5548c2c6a0Storek * struct cache_va { 5648c2c6a0Storek * u_int :2, (unused; probably copies of va_tid<13>) 5748c2c6a0Storek * cva_tid:14, (tag ID) 5848c2c6a0Storek * cva_line:12, (cache line number) 5948c2c6a0Storek * cva_byte:4; (byte in cache line) 6048c2c6a0Storek * }; 6148c2c6a0Storek * 629dfbde0aStorek * (The SS2 cache is similar but has half as many lines, each twice as long.) 639dfbde0aStorek * 6448c2c6a0Storek * Note that, because the 12-bit line ID is `wider' than the page offset, 6548c2c6a0Storek * it is possible to have one page map to two different cache lines. 6648c2c6a0Storek * This can happen whenever two different physical pages have the same bits 6748c2c6a0Storek * in the part of the virtual address that overlaps the cache line ID, i.e., 6848c2c6a0Storek * bits <15:12>. In order to prevent cache duplication, we have to 6948c2c6a0Storek * make sure that no one page has more than one virtual address where 7048c2c6a0Storek * (va1 & 0xf000) != (va2 & 0xf000). (The cache hardware turns off ct_v 7148c2c6a0Storek * when a cache miss occurs on a write, i.e., if va1 is in the cache and 7248c2c6a0Storek * va2 is not, and you write to va2, va1 goes out of the cache. If va1 7348c2c6a0Storek * is in the cache and va2 is not, reading va2 also causes va1 to become 7448c2c6a0Storek * uncached, and the [same] data is then read from main memory into the 7548c2c6a0Storek * cache.) 7648c2c6a0Storek * 7748c2c6a0Storek * The other alternative, of course, is to disable caching of aliased 7848c2c6a0Storek * pages. (In a few cases this might be faster anyway, but we do it 7948c2c6a0Storek * only when forced.) 8048c2c6a0Storek * 8148c2c6a0Storek * THE CURRENT VM CODE DOES NOT ALLOW US TO SPECIFY PREFERRED VIRTUAL 8248c2c6a0Storek * ADDRESSES ... THIS MUST BE FIXED! 8348c2c6a0Storek */ 8448c2c6a0Storek 8548c2c6a0Storek #define CACHE_ALIAS_DISTANCE (256 * 1024) /* 256 kbytes */ 8648c2c6a0Storek 8748c2c6a0Storek /* 8848c2c6a0Storek * True iff a1 and a2 are `bad' aliases (will cause cache duplication). 8948c2c6a0Storek */ 9048c2c6a0Storek #define BADALIAS(a1, a2) (((int)(a1) ^ (int)(a2)) & 0xf000) 9148c2c6a0Storek 9248c2c6a0Storek /* 9348c2c6a0Storek * Routines for dealing with the cache. 9448c2c6a0Storek */ 9548c2c6a0Storek void cache_enable __P((void)); /* turn it on */ 9648c2c6a0Storek void cache_flush_context __P((void)); /* flush current context */ 9748c2c6a0Storek void cache_flush_segment __P((int vseg)); /* flush seg in cur ctx */ 9848c2c6a0Storek void cache_flush_page __P((int va)); /* flush page in cur ctx */ 9948c2c6a0Storek void cache_flush __P((caddr_t base, u_int len));/* flush region */ 1009dfbde0aStorek 1019dfbde0aStorek /* 1029dfbde0aStorek * Cache control information. 1039dfbde0aStorek */ 1049dfbde0aStorek struct cacheinfo { 1059dfbde0aStorek int c_totalsize; /* total size, in bytes */ 1069dfbde0aStorek int c_enabled; /* true => cache is enabled */ 1079dfbde0aStorek int c_hwflush; /* true => have hardware flush */ 1089dfbde0aStorek int c_linesize; /* line size, in bytes */ 1099dfbde0aStorek int c_l2linesize; /* log2(linesize) */ 1109dfbde0aStorek }; 1119dfbde0aStorek extern struct cacheinfo cacheinfo; 1129dfbde0aStorek 1139dfbde0aStorek /* 1149dfbde0aStorek * Cache control statistics. 1159dfbde0aStorek */ 1169dfbde0aStorek struct cachestats { 1179dfbde0aStorek int cs_npgflush; /* # page flushes */ 1189dfbde0aStorek int cs_nsgflush; /* # seg flushes */ 1199dfbde0aStorek int cs_ncxflush; /* # context flushes */ 1209dfbde0aStorek int cs_nraflush; /* # range flushes */ 1219dfbde0aStorek #ifdef notyet 1229dfbde0aStorek int cs_ra[65]; /* pages/range */ 1239dfbde0aStorek #endif 1249dfbde0aStorek }; 125