1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)vaddrs.h 8.1 (Berkeley) 06/11/93 17 * 18 * from: $Header: vaddrs.h,v 1.3 92/11/26 03:05:11 torek Exp $ 19 */ 20 21 /* 22 * Special (fixed) virtual addresses on the SPARC. 23 * 24 * IO virtual space begins at 0xfe000000 (a segment boundary) and 25 * continues up to the DMVA edge at 0xff000000. (The upper all-1s 26 * byte is special since some of the hardware supplies this to pad 27 * a 24-bit address space out to 32 bits. This is a legacy of the 28 * IBM PC AT bus, actually, just so you know who to blame.) 29 * 30 * We reserve several pages at the base of our IO virtual space 31 * for `oft-used' devices which must be present anyway in order to 32 * configure. In particular, we want the counter-timer register and 33 * the Zilog ZSCC serial port chips to be mapped at fixed VAs to make 34 * microtime() and the zs hardware interrupt handlers faster. 35 * 36 * Ideally, we should map the interrupt enable register here as well, 37 * but that would require allocating pmegs in locore.s, so instead we 38 * use one of the two `wasted' pages at KERNBASE+2*NBPG (see locore.s). 39 */ 40 41 #ifndef IODEV_0 42 #define IODEV_0 0xfe000000 /* must match VM_MAX_KERNEL_ADDRESS */ 43 44 #define TIMERREG_VA (IODEV_0 + 0*NBPG) 45 #define ZS0_VA (IODEV_0 + 1*NBPG) 46 #define ZS1_VA (IODEV_0 + 2*NBPG) 47 #define AUXREG_VA (IODEV_0 + 3*NBPG) 48 #define IODEV_BASE (IODEV_0 + 4*NBPG) 49 #define IODEV_END 0xff000000 /* 16 MB of iospace */ 50 51 #define DVMA_BASE 0xfff00000 52 #define DVMA_END 0xfffc0000 53 54 #endif /* IODEV_0 */ 55