1 /* if_acereg.h 1.1 85/07/21 */ 2 3 /* 4 * VERSAbus ACC ethernet controller definitions 5 */ 6 7 /* 8 * Register definitions 9 */ 10 struct acedevice { 11 short station[6]; /* station address */ 12 short bcastena[2]; /* broadcast enable */ 13 short hash[8]; /* multicast hash codes */ 14 short csr; /* control and status register */ 15 short tseg; /* current transmit segment # */ 16 short rseg; /* current receive segment # */ 17 short segb; /* segment boundary register */ 18 short lrf; /* lost receive frame counter */ 19 short ivct; /* interrupt vector register */ 20 short resv; /* reserved for future use */ 21 short fcoll; /* force collision register */ 22 }; 23 24 /* 25 * Transmit segment in dual ported ram. 26 */ 27 struct tx_segment { 28 short tx_csr; /* packet status */ 29 char tx_data[2014]; 30 short tx_backoff[16]; /* random backoff counters */ 31 }; 32 33 /* 34 * Receive segment in dual ported ram. 35 */ 36 struct rx_segment { 37 short rx_csr; /* packet status */ 38 char rx_data[2046]; 39 }; 40 41 /* 42 * ACC statistics block. 43 */ 44 struct ace_stats { 45 int rx_datagrams; /* valid packets received */ 46 int rx_crc_errors; /* CRC errors */ 47 int rx_overruns; /* packets too large */ 48 int rx_underruns; /* packets too small */ 49 int rx_align_errors; /* packets w/ odd byte count */ 50 int rx_reserved; 51 int rx_busy; /* recv segment filled */ 52 int rx_mbuf; /* out of mbufs */ 53 int rx_oddoff; /* odd offset in mbuf */ 54 int rx_rintcnt; /* recvr interrupt */ 55 56 int tx_datagrams; /* packets xmit'd */ 57 int tx_retries; /* collision retries */ 58 int tx_discarded; /* packets w/ max retries */ 59 int tx_busy; /* xmit segment filled in acestart */ 60 int tx_cbusy; /* xmit segment filled in acecint */ 61 int tx_mbuf; /* total mbufs */ 62 int tx_oddoff; /* odd offset in mbuf */ 63 int tx_outcnt; /* calls to aceoutput */ 64 int tx_startcnt; /* calls to acestart */ 65 int tx_cintcnt; /* xmit's completed */ 66 }; 67 68 /* 69 * Control status definitions. 70 */ 71 #define CSR_OBCENA 0x0200 /* enable xmit of odd byte count */ 72 #define CSR_ACTIVE 0x0080 /* board active */ 73 #define CSR_RESET 0x0040 /* reset board */ 74 #define CSR_PROMISC 0x0020 /* enable promiscous mode */ 75 #define CSR_CRCDIS 0x0010 /* disable CRC generation */ 76 #define CSR_LOOP3 0x0008 /* enable loopback mode 3 */ 77 #define CSR_LOOP2 0x0004 /* enable loopback mode 2 */ 78 #define CSR_IENA 0x0002 /* interrupt enable */ 79 #define CSR_GO 0x0001 /* enable micro-engine */ 80 81 #define ACE_CSRBITS \ 82 "\20\12OBCENA\10ACTIVE\7RESET\6PROMISC\5CRCDIS\4LOOP3\3LOOP2\2IENA\1GO" 83 /* 84 * Transmit packet status definitions. 85 */ 86 #define TCS_TBFULL (short)0x8000 /* buffer filled, send it */ 87 #define TCS_TBC (short)0x07FF /* byte count */ 88 #define TCS_TBMT (short)0x8000 /* buffer empty */ 89 #define TCS_RTFAIL (short)0x4000 /* retries failed */ 90 #define TCS_RTC (short)0x000F /* collision retry mask */ 91 92 /* 93 * Receive packet status definitions. 94 */ 95 #define RCS_RBMT 0x8000 /* buffer ready for recv */ 96 #define RCS_RBFULL 0x8000 /* buffer full, take data */ 97 #define RCS_ROVRN 0x4000 /* overrun error */ 98 #define RCS_RCRC 0x2000 /* CRC error */ 99 #define RCS_RODD 0x1000 /* odd byte count error */ 100 #define RCS_RBC 0x07FF /* byte count mask */ 101 102 #define ACE_RCSBITS "\20\20RBFULL\17ROVRN\16RCSR\15RODD" 103 104 #define CRC_SIZE 4 /* number of bytes in a rx seg's CRC */ 105 #define RCW_SIZE 2 /* number of bytes in a rx seg's csr */ 106 #define SEG_MAX 15 /* largest valid segment number */ 107 #define ET_MINLEN 64 /* min frame size */ 108 #define ET_MAXLEN 1514 /* max frame size w/o CRC & RCW */ 109