1 /* 2 * @(#)mtpr.h 7.1 (Berkeley) 05/21/88 3 * from mtpr.h 4.5 82/11/05 4 */ 5 6 /* 7 * TAHOE processor register numbers 8 */ 9 10 #define SBR 0x0 /* system base register */ 11 #define SLR 0x1 /* system length register */ 12 #define P0BR 0x2 /* p0 base register */ 13 #define P0LR 0x3 /* p0 length register */ 14 #define P1BR 0x4 /* p1 base register */ 15 #define P1LR 0x5 /* p1 length register */ 16 #define P2BR 0x6 /* p2 base register */ 17 #define P2LR 0x7 /* p2 length register */ 18 #define IPL 0x8 /* interrupt priority level */ 19 #define MME 0x9 /* memory management enable */ 20 #define TBIA 0xa /* translation buffer invalidate all */ 21 #define TBIS 0xb /* translation buffer invalidate single */ 22 #define DCK 0xc /* data cache key */ 23 #define CCK 0xd /* code cache key */ 24 #define PCBB 0xe /* process control block base */ 25 #define ISP 0xf /* interrupt stack pointer */ 26 #define SIRR 0x10 /* software interrupt request */ 27 #define SISR 0x11 /* software interrupt summary */ 28 #define SCBB 0x12 /* system control block base */ 29 #define KSP 0x13 /* kernelack pointer */ 30 #define USP 0x14 /* user stack pointer */ 31 #define CPMDCB 0x15 /* CP master DCM pointer */ 32 #define PACC 0x17 /* purge all code cache */ 33 #define P1DC 0x18 /* purge one data cache */ 34 #define PADC 0x19 /* purge all data cache */ 35 #define HISR 0x1a /* hardware interrupt summery register */ 36 #define DCR 0x1b /* diagnostic control register */ 37 #define PDCS 0x1c /* purge data cache slot */ 38