1 /*- 2 * Copyright (c) 1986 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Computer Consoles Inc. 7 * 8 * %sccs.include.proprietary.c% 9 * 10 * @(#)mtpr.h 7.3 (Berkeley) 02/20/92 11 */ 12 13 #ifndef _MTPR_H__ 14 #define _MTPR_H_ 15 /* 16 * TAHOE processor register numbers 17 */ 18 #define SBR 0x0 /* system base register */ 19 #define SLR 0x1 /* system length register */ 20 #define P0BR 0x2 /* p0 base register */ 21 #define P0LR 0x3 /* p0 length register */ 22 #define P1BR 0x4 /* p1 base register */ 23 #define P1LR 0x5 /* p1 length register */ 24 #define P2BR 0x6 /* p2 base register */ 25 #define P2LR 0x7 /* p2 length register */ 26 #define IPL 0x8 /* interrupt priority level */ 27 #define MME 0x9 /* memory management enable */ 28 #define TBIA 0xa /* translation buffer invalidate all */ 29 #define TBIS 0xb /* translation buffer invalidate single */ 30 #define DCK 0xc /* data cache key */ 31 #define CCK 0xd /* code cache key */ 32 #define PCBB 0xe /* process control block base */ 33 #define ISP 0xf /* interrupt stack pointer */ 34 #define SIRR 0x10 /* software interrupt request */ 35 #define SISR 0x11 /* software interrupt summary */ 36 #define SCBB 0x12 /* system control block base */ 37 #define KSP 0x13 /* kernelack pointer */ 38 #define USP 0x14 /* user stack pointer */ 39 #define CPMDCB 0x15 /* CP master DCM pointer */ 40 #define PACC 0x17 /* purge all code cache */ 41 #define P1DC 0x18 /* purge one data cache */ 42 #define PADC 0x19 /* purge all data cache */ 43 #define HISR 0x1a /* hardware interrupt summery register */ 44 #define DCR 0x1b /* diagnostic control register */ 45 #define PDCS 0x1c /* purge data cache slot */ 46 #endif /* !_MTPR_H_ */ 47