1*75093b96Ssam /* udc.h 1.2 86/01/05 */ 21b560adaSsam 31b560adaSsam struct UDPAC { /* UDC command packet */ 41b560adaSsam char _stx ; 51b560adaSsam char _pkid ; 61b560adaSsam char _pksiz ; /* 21 bytes */ 71b560adaSsam char _pkdev ; /* device # */ 81b560adaSsam char _pkcmd ; /* Command type */ 91b560adaSsam char _pkfnc ; /* Function type */ 101b560adaSsam short _pkcnt ; /* # of data blocks (1/4K each) */ 111b560adaSsam short _pbsiz ; /* Block length size (0x100 = 1/4K) */ 121b560adaSsam short _pkmem[2] ; /* Starting memory address.Should be 'long' but 131b560adaSsam we can't write it this way on Tahoe, 141b560adaSsam because of alignment problems - the C 151b560adaSsam will gap after the previous 'short' */ 161b560adaSsam short _pcksm ; /* Checksum (unused) */ 171b560adaSsam long _psecno ; /* Starting sector # */ 181b560adaSsam char _etx ; 191b560adaSsam } 201b560adaSsam ; 211b560adaSsam 221b560adaSsam #define SECTSIZ 256 /* sector size */ 231b560adaSsam #define L2SIZ 8 /* log2 of sector size */ 241b560adaSsam #define L2BSIZ 10 /* log2 of block size */ 251b560adaSsam #define NUDC 1 /* number of UDC controllers */ 261b560adaSsam #define NUNIT 8 /* number of units per controller */ 271b560adaSsam #define NUDDRV 5 /* number of drive types supported */ 281b560adaSsam #define DK_N 1 /* Monitoring device bit */ 291b560adaSsam 301b560adaSsam /* 311b560adaSsam ** Block devices sizes structure 321b560adaSsam */ 331b560adaSsam 341b560adaSsam struct size 351b560adaSsam { 361b560adaSsam daddr_t nblocks; 371b560adaSsam int block0; 381b560adaSsam }; 391b560adaSsam 401b560adaSsam #define udaddr ( (char *)(0xff0000+IOBASE) ) 411b560adaSsam #define INT 0x00d /* interrupt offset */ 421b560adaSsam #define RST 0x00f /* controller reset offset */ 431b560adaSsam #define OB1 0x101 441b560adaSsam #define OB2 0x103 451b560adaSsam #define IB1 0x181 461b560adaSsam #define IB2 0x183 471b560adaSsam #define PKID 0x187 /* packet id */ 481b560adaSsam #define PKLEN 0x189 /* packet length */ 491b560adaSsam #define PKDEV 0x18b /* device # */ 501b560adaSsam #define PKCMD 0x18d /* command type */ 511b560adaSsam #define PKSTT 0x18f /* status type */ 521b560adaSsam #define STAT1 0x191 /* i/o status result offset */ 531b560adaSsam #define STAT2 0x193 541b560adaSsam #define DEVSTAT1 0x195 551b560adaSsam #define DEVSTAT2 0x197 561b560adaSsam #define DEVSIZE 0x199 /* # of sectors in device status message */ 571b560adaSsam 581b560adaSsam #define UDREAD 0x10 591b560adaSsam #define UDWTRY 0x01 /* read with retry */ 601b560adaSsam 611b560adaSsam #define UDWRITE 0x20 621b560adaSsam #define UDWCRC 0x01 /* write sectors and check CRC */ 631b560adaSsam #define UDWSECT 0x02 /* write sectors */ 641b560adaSsam 651b560adaSsam #define UDTEST 0x30 661b560adaSsam #define UDSTAT 0x02 /* Test status */ 671b560adaSsam 681b560adaSsam #define DEVRDY 0x80 /* device ready bit in status byte */ 691b560adaSsam #define DEVTYPE 0x7 /* bits 0-2 in status byte define device */ 701b560adaSsam #define FLP 0x1 711b560adaSsam #define HARDDISK 0x2 721b560adaSsam #define TAPE 0x5 731b560adaSsam 741b560adaSsam /* Some I/O addresses used to generate pulses for scopes */ 751b560adaSsam #define OUT1 0xffffb034 761b560adaSsam #define OUT2 0xffffb018 771b560adaSsam #define OUT3 0xffffb020 781b560adaSsam #define OUT4 0xffffb004 791b560adaSsam #define OUT5 0xffffb024 801b560adaSsam #define OUT6 0xffffb00c 811b560adaSsam #define OUT7 0xffffb02c 821b560adaSsam 831b560adaSsam #define IN1 0xffffb030 841b560adaSsam #define IN2 0xffffb03c 851b560adaSsam #define IN3 0xffffb004 861b560adaSsam #define IN4 0xffffb00c 871b560adaSsam #define IN5 0xffffb02c 881b560adaSsam 891b560adaSsam int dummy; 901b560adaSsam extern char vmem[][16*NBPG]; 911b560adaSsam 92*75093b96Ssam #define IOaddr(off) (caddr_t)((int)vmem + ((off) & 0x0fffff)) 931b560adaSsam 941b560adaSsam int iospace_mapped; 95*75093b96Ssam #define scope_out(x) if(iospace_mapped) movob(IOaddr(OUT/**/x),0) 961b560adaSsam #define scope_in(x) if(iospace_mapped) dummy = *IOaddr(IN/**/x) 97