1/* scb.s 1.2 86/01/12 */ 2 3/* 4 * System control block 5 */ 6#define STRAY .long _Xstray 7#define STRAY8 STRAY;STRAY;STRAY;STRAY;STRAY;STRAY;STRAY;STRAY 8#define KS(a) .long _X/**/a 9#define IS(a) .long _X/**/a 10 11_scb: .globl _scb 12/* 000 */ STRAY; IS(powfail); IS(doadump); STRAY; 13/* 004 */ STRAY; STRAY; STRAY; IS(hardclock); 14/* 008 */ STRAY; STRAY; IS(cnrint); IS(cnxint); 15/* 00c */ IS(rmtrint); IS(rmtxint); STRAY; STRAY; 16/* 010 */ STRAY; STRAY; STRAY; IS(netintr); 17/* 014 */ STRAY; STRAY; STRAY; IS(softclock); 18/* 018 */ STRAY; STRAY; STRAY; STRAY; 19/* 01c */ STRAY; STRAY; STRAY; STRAY; 20/* 020 */ IS(buserr); STRAY; STRAY; STRAY; 21/* 024 */ STRAY; STRAY; STRAY; STRAY; 22/* 028 */ STRAY; STRAY; STRAY; KS(syscall); 23/* 02c */ KS(privinflt); KS(resopflt); KS(resadflt); KS(protflt); 24/* 030 */ KS(transflt); IS(kspnotval); KS(tracep); KS(bptflt); 25/* 034 */ KS(arithtrap); KS(alignflt); KS(sfexcep); KS(fpm); 26/* 038 */ STRAY; STRAY; STRAY; STRAY; 27/* 03c */ STRAY; STRAY; STRAY; STRAY; 28 /* device interrupt vectors */ 29/* 040 */ STRAY8; STRAY8; STRAY8; STRAY8; 30/* 060 */ STRAY8; STRAY8; STRAY8; STRAY8; 31/* 080 */ STRAY8; STRAY8; STRAY8; STRAY8; 32/* 0a0 */ STRAY8; STRAY8; STRAY8; STRAY8; 33/* 0c0 */ STRAY8; STRAY8; STRAY8; STRAY8; 34/* 0e0 */ STRAY8; STRAY8; STRAY8; STRAY8; 35