158a10c11Skarels /* 2cbb11358Sbostic * Copyright (c) 1988 The Regents of the University of California. 3cbb11358Sbostic * All rights reserved. 4cbb11358Sbostic * 5cbb11358Sbostic * This code is derived from software contributed to Berkeley by 6cbb11358Sbostic * Computer Consoles Inc. 7cbb11358Sbostic * 8*f69c3528Sbostic * %sccs.include.redist.c% 9cbb11358Sbostic * 10*f69c3528Sbostic * @(#)drreg.h 7.3 (Berkeley) 06/28/90 1158a10c11Skarels */ 1244144c92Ssam 1344144c92Ssam /* 1444144c92Ssam ------------------------------------------ 1544144c92Ssam Must include <h/types.h> and <h/buf.h> 1644144c92Ssam ------------------------------------------ 1744144c92Ssam */ 1844144c92Ssam 1944144c92Ssam #define DRINTV 0x9c /* Has to match with ml/scb.s */ 2044144c92Ssam #define DRADDMOD 0x01 /* Addr modifier used to access TAHOE memory */ 2144144c92Ssam #define DR_ZERO 0 2244144c92Ssam #define DRPRI (PZERO+1) 2344144c92Ssam 2444144c92Ssam #define DR_TICK 600 /* Default # of clock ticks between call 2544144c92Ssam to local timer watchdog routine */ 2644144c92Ssam #define DR_TOCK 2 /* default # of calls to local watch dog 2744144c92Ssam before an IO or wait is determined to 2844144c92Ssam have timeout */ 2944144c92Ssam 3044144c92Ssam 3144144c92Ssam struct rsdevice { 3244144c92Ssam ushort dr_cstat; /* Control & status registers */ 3344144c92Ssam ushort dr_data; /* Input/Ouptut data registers */ 3444144c92Ssam char dr_addmod; /* Address modifier for DMA */ 3544144c92Ssam char dr_intvect; /* Interrupt vector */ 3644144c92Ssam ushort dr_pulse; /* Pulse command register */ 3744144c92Ssam ushort dr_xx08; /* Not used */ 3844144c92Ssam ushort dr_xx0A; /* Not used */ 3944144c92Ssam ushort dr_xx0C; /* Not used */ 4044144c92Ssam ushort dr_xx0E; /* Not used */ 4144144c92Ssam ushort dr_xx10; /* Not used */ 4244144c92Ssam ushort dr_walo; /* Low DMA address register --when written-- */ 4344144c92Ssam ushort dr_range; /* DMA range counter */ 4444144c92Ssam ushort dr_ralo; /* Low DMA address register --when read-- */ 4544144c92Ssam ushort dr_xx18; /* Not used */ 4644144c92Ssam ushort dr_wahi; /* High DMA address register --when written-- */ 4744144c92Ssam ushort dr_xx1C; /* Not used */ 4844144c92Ssam ushort dr_rahi; /* High DMA address register --when read-- */ 4944144c92Ssam }; 5044144c92Ssam 5144144c92Ssam 5244144c92Ssam struct dr_aux { 5344144c92Ssam struct rsdevice *dr_addr; /* Physical addr of currently active DR11 */ 5444144c92Ssam struct buf *dr_actf; /* Pointers to DR11's active buffers list */ 5544144c92Ssam unsigned int dr_flags; /* State: Hold open, active,... */ 5644144c92Ssam ushort dr_cmd; /* Hold cmd placed here by ioctl 5744144c92Ssam for later execution by rsstrategy() */ 5844144c92Ssam ushort dr_op; /* Current operation: DR_READ/DR_WRITE */ 5944144c92Ssam long dr_bycnt; /* Total byte cnt of current operation */ 6044144c92Ssam /* decremented by completion interrupt */ 6144144c92Ssam caddr_t dr_oba; /* original xfer addr, count */ 6244144c92Ssam long dr_obc; 6344144c92Ssam unsigned long 6444144c92Ssam rtimoticks, /* No of ticks before timing out on no stall 6544144c92Ssam read */ 6644144c92Ssam wtimoticks, /* No of ticks before timing out on no stall 6744144c92Ssam write */ 6844144c92Ssam currenttimo; /* the number of current timeout call to 6944144c92Ssam omrwtimo() */ 7044144c92Ssam ushort dr_istat; /* Latest interrupt status */ 7144144c92Ssam struct buf dr_buf; 7244144c92Ssam 7344144c92Ssam /*ushort dr_time; /* # of ticks until timeout */ 7444144c92Ssam /*ushort dr_tock; /* # of ticks accumulated */ 7544144c92Ssam /*ushort dr_cseq; /* Current sequence number */ 7644144c92Ssam /*ushort dr_lseq; /* Last sequence number */ 7744144c92Ssam }; 7844144c92Ssam 7944144c92Ssam /* Command used by drioctl() 8044144c92Ssam */ 8144144c92Ssam struct dr11io { 8244144c92Ssam ushort arg[8]; 8344144c92Ssam }; 8444144c92Ssam 8544144c92Ssam #define RSADDR(unit) ((struct rsdevice *)drinfo[unit]->ui_addr) 8644144c92Ssam 8744144c92Ssam /* Control register bits */ 8844144c92Ssam #define RDMA 0x8000 /* reset DMA end-of-range flag */ 8944144c92Ssam #define RATN 0x4000 /* reset attention flag */ 9044144c92Ssam #define RPER 0x2000 /* reset device parity error flag */ 9144144c92Ssam #define MCLR 0x1000 /* master clear board and INT device */ 9244144c92Ssam #define CYCL 0x0100 /* forces DMA cycle if DMA enabled */ 9344144c92Ssam #define IENB 0x0040 /* enables interrupt */ 9444144c92Ssam #define FCN3 0x0008 /* func. bit 3 to device (FNCT3 H) */ 9544144c92Ssam #define FCN2 0x0004 /* func. bit 2 to device (FNCT2 H) */ 9644144c92Ssam /* also asserts ACLO FCNT2 H to device */ 9744144c92Ssam #define FCN1 0x0002 /* func. bit 1 to device (FNCT1 H) */ 9844144c92Ssam #define GO 0x0001 /* enable DMA and pulse GO to device */ 9944144c92Ssam 10044144c92Ssam /* Status register bits */ 10144144c92Ssam #define DMAF 0x8000 /* indicates DMA end-of-range */ 10244144c92Ssam #define ATTF 0x4000 /* indicates attention false-to-true */ 10344144c92Ssam #define ATTN 0x2000 /* current state of ATTENTION H input */ 10444144c92Ssam #define PERR 0x1000 /* Set by external parity error */ 10544144c92Ssam #define STTA 0x0800 /* STATUS A H input state */ 10644144c92Ssam #define STTB 0x0400 /* STATUS B H input state */ 10744144c92Ssam #define STTC 0x0200 /* STATUS C H input state */ 10844144c92Ssam #define REDY 0x0080 /* board ready for cmd (dma not on) */ 10944144c92Ssam #define IENF 0x0040 /* Interrupt enabled if on */ 11044144c92Ssam #define BERR 0x0020 /* Set if bus error during DMA */ 11144144c92Ssam #define TERR 0x0010 /* Set if bus timeout during DMA */ 11244144c92Ssam #define FC3S 0x0008 /* State of FCN3 latch */ 11344144c92Ssam #define FC2S 0x0004 /* State of FCN2 latch */ 11444144c92Ssam #define FC1S 0x0002 /* State of FCN1 latch */ 11544144c92Ssam #define DLFG 0x0001 /* 0 -> IKON-10083 *** 1 -> IKON-10077 */ 11644144c92Ssam 11744144c92Ssam /* Pulse command register bits */ 11844144c92Ssam #define SMSK 0x0040 /* pulse interrupt mask on: Set IENB */ 11944144c92Ssam #define RMSK 0x0020 /* pulse interrupt mask off: Reset IENB */ 12044144c92Ssam 12144144c92Ssam 12244144c92Ssam /* 12344144c92Ssam * DR11 driver's internal flags -- to be stored in dr_flags 12444144c92Ssam */ 12544144c92Ssam #define DR_FMSK 0x0000E /* function bits mask */ 12644144c92Ssam #define DR_OPEN 0x00001 /* This dr11 has been opened */ 12744144c92Ssam #define DR_PRES 0x00002 /* This dr11 is present */ 12844144c92Ssam #define DR_ACTV 0x00004 /* waiting for end-of-range */ 12944144c92Ssam #define DR_ATWT 0x00008 /* waiting for attention interrupt */ 13044144c92Ssam #define DR_ATRX 0x00010 /* attn received-resets when read */ 13144144c92Ssam #define DR_TMDM 0x00020 /* timeout waiting for end-of-range */ 13244144c92Ssam #define DR_TMAT 0x00040 /* timeout waiting for attention */ 13344144c92Ssam #define DR_DMAX 0x00080 /* end-of-range interrupt received */ 13444144c92Ssam #define DR_PCYL 0x00100 /* set cycle with next go */ 13544144c92Ssam #define DR_DFCN 0x00200 /* donot update function bits until next go */ 13644144c92Ssam #define DR_DACL 0x00400 /* defer alco pulse until go */ 13744144c92Ssam #define DR_LOOPTST 0x02000 /* This dr11 is in loopback test mode */ 13844144c92Ssam #define DR_LNKMODE 0x04000 /* This dr11 is in link mode */ 13944144c92Ssam #define DR_NORSTALL 0x10000 /* Device is set to no stall mode for reads. */ 14044144c92Ssam #define DR_NOWSTALL 0x20000 /* Device is set to no stall mode for writes. */ 14144144c92Ssam #define DR_TIMEDOUT 0x40000 /* The device timed out on a stall mode R/W */ 14244144c92Ssam 14344144c92Ssam /* 14444144c92Ssam * DR11 driver's internal flags -- to be stored in dr_op 14544144c92Ssam */ 14644144c92Ssam #define DR_READ FCN1 14744144c92Ssam #define DR_WRITE 0 14844144c92Ssam 14944144c92Ssam /* 15044144c92Ssam * Ioctl commands 15144144c92Ssam */ 152e4e75e08Sbostic #define DRWAIT _IOWR('d',1,long) 153e4e75e08Sbostic #define DRPIOW _IOWR('d',2,long) 154e4e75e08Sbostic #define DRPACL _IOWR('d',3,long) 155e4e75e08Sbostic #define DRDACL _IOWR('d',4,long) 156e4e75e08Sbostic #define DRPCYL _IOWR('d',5,long) 157e4e75e08Sbostic #define DRDFCN _IOWR('d',6,long) 158e4e75e08Sbostic #define DRRPER _IOWR('d',7,long) 159e4e75e08Sbostic #define DRRATN _IOWR('d',8,long) 160e4e75e08Sbostic #define DRRDMA _IOWR('d',9,long) 161e4e75e08Sbostic #define DRSFCN _IOWR('d',10,long) 16244144c92Ssam 163e4e75e08Sbostic #define DRSETRSTALL _IOWR('d',13,long) 164e4e75e08Sbostic #define DRSETNORSTALL _IOWR('d',14,long) 165e4e75e08Sbostic #define DRGETRSTALL _IOWR('d',15,long) 166e4e75e08Sbostic #define DRSETRTIMEOUT _IOWR('d',16,long) 167e4e75e08Sbostic #define DRGETRTIMEOUT _IOWR('d',17,long) 168e4e75e08Sbostic #define DRSETWSTALL _IOWR('d',18,long) 169e4e75e08Sbostic #define DRSETNOWSTALL _IOWR('d',19,long) 170e4e75e08Sbostic #define DRGETWSTALL _IOWR('d',20,long) 171e4e75e08Sbostic #define DRSETWTIMEOUT _IOWR('d',21,long) 172e4e75e08Sbostic #define DRGETWTIMEOUT _IOWR('d',22,long) 173e4e75e08Sbostic #define DRWRITEREADY _IOWR('d',23,long) 174e4e75e08Sbostic #define DRREADREADY _IOWR('d',24,long) 175e4e75e08Sbostic #define DRBUSY _IOWR('d',25,long) 176e4e75e08Sbostic #define DRRESET _IOWR('d',26,long) 17744144c92Ssam 17844144c92Ssam /* The block size for buffering and DMA transfers. */ 17944144c92Ssam /* OM_BLOCKSIZE must be even and <= 32768. Multiples of 512 are prefered. */ 18044144c92Ssam #define OM_BLOCKSIZE 32768 18144144c92Ssam 18244144c92Ssam 18344144c92Ssam /* --- Define ioctl call used by dr11 utility device -- */ 18444144c92Ssam 185e4e75e08Sbostic #define DR11STAT _IOWR('d',30,struct dr11io) /* Get status dr11, unit 18644144c92Ssam number is dr11io.arg[0] */ 187e4e75e08Sbostic #define DR11LOOP _IOR('d',31,struct dr11io) /* Perform loopback test */ 18844144c92Ssam 18944144c92Ssam /* ---------------------------------------------------- */ 19044144c92Ssam 191