1 /* 2 * Copyright (c) 1988 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Chris Torek. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)bireg.h 7.3 (Berkeley) 06/28/90 11 */ 12 13 /* 14 * VAXBI node definitions. 15 */ 16 17 /* 18 * BI node addresses 19 */ 20 #define BI_BASE(bi) ((struct bi_node *) (0x20000000 + (bi)*0x2000000)) 21 #define NNODEBI 16 /* 16 nodes per BI */ 22 /* `local space' 0x20800000 /* ??? */ 23 24 #ifndef LOCORE 25 /* 26 * BI nodes all start with BI interface registers (those on the BIIC chip). 27 * These are followed with interface-specific registers. 28 * 29 * NB: This structure does NOT include the four GPRs (not anymore!) 30 */ 31 struct biiregs { 32 u_short bi_dtype; /* device type */ 33 u_short bi_revs; /* revisions */ 34 u_long bi_csr; /* control and status register */ 35 u_long bi_ber; /* bus error register */ 36 u_long bi_eintrcsr; /* error interrupt control register */ 37 u_long bi_intrdes; /* interrupt destination register */ 38 /* the rest are not required for all nodes */ 39 u_long bi_ipintrmsk; /* IP interrupt mask register */ 40 u_long bi_fipsdes; /* Force-Bit IPINTR/STOP destination reg */ 41 u_long bi_ipintrsrc; /* IPINTR source register */ 42 u_long bi_sadr; /* starting address register */ 43 u_long bi_eadr; /* ending address register */ 44 u_long bi_bcicsr; /* BCI control and status register */ 45 u_long bi_wstat; /* write status register */ 46 u_long bi_fipscmd; /* Force-Bit IPINTR/STOP command reg */ 47 u_long bi_xxx1[3]; /* unused */ 48 u_long bi_uintrcsr; /* user interface interrupt control reg */ 49 u_long bi_xxx2[43]; /* unused */ 50 /* although these are on the BIIC, their interpretation varies */ 51 /* u_long bi_gpr[4]; /* general purpose registers */ 52 }; 53 54 /* 55 * A generic BI node. 56 */ 57 struct bi_node { 58 struct biiregs biic; /* interface */ 59 u_long bi_xxx[1988]; /* pad to 8K */ 60 }; 61 62 /* 63 * A cpu node. 64 */ 65 struct bi_cpu { 66 struct biiregs biic; /* interface chip */ 67 u_long bi_gpr[4]; /* gprs (unused) */ 68 u_long bi_sosr; /* slave only status register */ 69 u_long bi_xxx[63]; /* pad */ 70 u_long bi_rxcd; /* receive console data register */ 71 }; 72 #endif LOCORE 73 74 /* device types */ 75 #define BIDT_MS820 0x0001 /* MS820 memory board */ 76 #define BIDT_DWBUA 0x0102 /* DWBUA Unibus adapter */ 77 #define BIDT_KLESI 0x0103 /* KLESI-B adapter */ 78 #define BIDT_KA820 0x0105 /* KA820 cpu */ 79 #define BIDT_DB88 0x0106 /* DB88 adapter */ 80 #define BIDT_DMB32 0x0109 /* DMB32 adapter */ 81 #define BIDT_KDB50 0x010e /* KDB50 disk controller */ 82 #define BIDT_DEBNK 0x410e /* BI Ethernet (Lance) + TK50 */ 83 #define BIDT_DEBNA 0x410f /* BI Ethernet (Lance) adapter */ 84 85 #ifdef notdef /* CPU (KA820) bits in bi_revs */ 86 #define BI_CPUREV(x) (((x) >> 11)) /* CPU revision code */ 87 #define BI_UPATCHREV(x) (((x) >> 1) & 0x3ff) /* microcode patch rev */ 88 #define BI_SPATCHREV(x) (((x) & 1) /* secondary patch rev */ 89 #endif 90 91 /* bits in bi_csr */ 92 #define BICSR_IREV(x) ((u_char)((x) >> 24)) /* VAXBI interface rev */ 93 #define BICSR_TYPE(x) ((u_char)((x) >> 16)) /* BIIC type */ 94 #define BICSR_HES 0x8000 /* hard error summary */ 95 #define BICSR_SES 0x4000 /* soft error summary */ 96 #define BICSR_INIT 0x2000 /* initialise node */ 97 #define BICSR_BROKE 0x1000 /* broke */ 98 #define BICSR_STS 0x0800 /* self test status */ 99 #define BICSR_NRST 0x0400 /* node reset */ 100 #define BICSR_UWP 0x0100 /* unlock write pending */ 101 #define BICSR_HEIE 0x0080 /* hard error interrupt enable */ 102 #define BICSR_SEIE 0x0040 /* soft error interrupt enable */ 103 #define BICSR_ARB_MASK 0x0030 /* mask to get arbitration codes */ 104 #define BICSR_ARB_NONE 0x0030 /* no arbitration */ 105 #define BICSR_ARB_LOG 0x0020 /* low priority */ 106 #define BICSR_ARB_HIGH 0x0010 /* high priority */ 107 #define BICSR_ARB_RR 0x0000 /* round robin */ 108 #define BICSR_NODEMASK 0x000f /* node ID */ 109 110 #define BICSR_BITS \ 111 "\20\20HES\17SES\16INIT\15BROKE\14STS\13NRST\11UWP\10HEIE\7SEIE" 112 113 /* bits in bi_ber */ 114 #define BIBER_MBZ 0x8000fff0 115 #define BIBER_NMR 0x40000000 /* no ack to multi-responder command */ 116 #define BIBER_MTCE 0x20000000 /* master transmit check error */ 117 #define BIBER_CTE 0x10000000 /* control transmit error */ 118 #define BIBER_MPE 0x08000000 /* master parity error */ 119 #define BIBER_ISE 0x04000000 /* interlock sequence error */ 120 #define BIBER_TDF 0x02000000 /* transmitter during fault */ 121 #define BIBER_IVE 0x01000000 /* ident vector error */ 122 #define BIBER_CPE 0x00800000 /* command parity error */ 123 #define BIBER_SPE 0x00400000 /* slave parity error */ 124 #define BIBER_RDS 0x00200000 /* read data substitute */ 125 #define BIBER_RTO 0x00100000 /* retry timeout */ 126 #define BIBER_STO 0x00080000 /* stall timeout */ 127 #define BIBER_BTO 0x00040000 /* bus timeout */ 128 #define BIBER_NEX 0x00020000 /* nonexistent address */ 129 #define BIBER_ICE 0x00010000 /* illegal confirmation error */ 130 #define BIBER_UPEN 0x00000008 /* user parity enable */ 131 #define BIBER_IPE 0x00000004 /* ID parity error */ 132 #define BIBER_CRD 0x00000002 /* corrected read data */ 133 #define BIBER_NPE 0x00000001 /* null bus parity error */ 134 #define BIBER_HARD 0x4fff0000 135 136 #define BIBER_BITS \ 137 "\20\37NMR\36MTCE\35CTE\34MPE\33ISE\32TDF\31IVE\30CPE\ 138 \27SPE\26RDS\25RTO\24STO\23BTO\22NEX\21ICE\4UPEN\3IPE\2CRD\1NPE" 139 140 /* bits in bi_eintrcsr */ 141 #define BIEIC_INTRAB 0x01000000 /* interrupt abort */ 142 #define BIEIC_INTRC 0x00800000 /* interrupt complete */ 143 #define BIEIC_INTRSENT 0x00200000 /* interrupt command sent */ 144 #define BIEIC_INTRFORCE 0x00100000 /* interrupt force */ 145 #define BIEIC_LEVELMASK 0x000f0000 /* mask for interrupt levels */ 146 #define BIEIC_IPL17 0x00080000 /* ipl 0x17 */ 147 #define BIEIC_IPL16 0x00040000 /* ipl 0x16 */ 148 #define BIEIC_IPL15 0x00020000 /* ipl 0x15 */ 149 #define BIEIC_IPL14 0x00010000 /* ipl 0x14 */ 150 #define BIEIC_VECMASK 0x00003ffc /* vector mask for error intr */ 151 152 /* bits in bi_intrdes */ 153 #define BIDEST_MASK 0x0000ffff /* one bit per node to be intr'ed */ 154 155 /* bits in bi_ipintrmsk */ 156 #define BIIPINTR_MASK 0xffff0000 /* one per node to allow to ipintr */ 157 158 /* bits in bi_fipsdes */ 159 #define BIFIPSD_MASK 0x0000ffff 160 161 /* bits in bi_ipintrsrc */ 162 #define BIIPSRC_MASK 0xffff0000 163 164 /* sadr and eadr are simple addresses */ 165 166 /* bits in bi_bcicsr */ 167 #define BCI_BURSTEN 0x00020000 /* burst mode enable */ 168 #define BCI_IPSTOP_FRC 0x00010000 /* ipintr/stop force */ 169 #define BCI_MCASTEN 0x00008000 /* multicast space enable */ 170 #define BCI_BCASTEN 0x00004000 /* broadcast enable */ 171 #define BCI_STOPEN 0x00002000 /* stop enable */ 172 #define BCI_RSRVDEN 0x00001000 /* reserved enable */ 173 #define BCI_IDENTEN 0x00000800 /* ident enable */ 174 #define BCI_INVALEN 0x00000400 /* inval enable */ 175 #define BCI_WINVEN 0x00000200 /* write invalidate enable */ 176 #define BCI_UINTEN 0x00000100 /* user interface csr space enable */ 177 #define BCI_BIICEN 0x00000080 /* BIIC csr space enable */ 178 #define BCI_INTEN 0x00000040 /* interrupt enable */ 179 #define BCI_IPINTEN 0x00000020 /* ipintr enable */ 180 #define BCI_PIPEEN 0x00000010 /* pipeline NXT enable */ 181 #define BCI_RTOEVEN 0x00000008 /* read timeout EV enable */ 182 183 #define BCI_BITS \ 184 "\20\22BURSTEN\21IPSTOP_FRC\20MCASTEN\ 185 \17BCASTEN\16STOPEN\15RSRVDEN\14IDENTEN\13INVALEN\12WINVEN\11UINTEN\ 186 \10BIICEN\7INTEN\6IPINTEN\5PIPEEN\4RTOEVEN" 187 188 /* bits in bi_wstat */ 189 #define BIW_GPR3 0x80000000 /* gpr 3 was written */ 190 #define BIW_GPR2 0x40000000 /* gpr 2 was written */ 191 #define BIW_GPR1 0x20000000 /* gpr 1 was written */ 192 #define BIW_GPR0 0x10000000 /* gpr 0 was written */ 193 194 /* bits in force-bit ipintr/stop command register 8/ 195 #define BIFIPSC_CMDMASK 0x0000f000 /* command */ 196 #define BIFIPSC_MIDEN 0x00000800 /* master ID enable */ 197 198 /* bits in bi_uintcsr */ 199 #define BIUI_INTAB 0xf0000000 /* interrupt abort level */ 200 #define BIUI_INTC 0x0f000000 /* interrupt complete bits */ 201 #define BIUI_SENT 0x00f00000 /* interrupt sent bits */ 202 #define BIUI_FORCE 0x000f0000 /* force interrupt level */ 203 #define BIUI_EVECEN 0x00008000 /* external vector enable */ 204 #define BIUI_VEC 0x00003ffc /* interrupt vector */ 205 206 /* tell if a bi device is a slave (hence has SOSR) */ 207 #define BIDT_ISSLAVE(x) (((x) & 0x7f00) == 0) 208 209 /* bits in bi_sosr */ 210 #define BISOSR_MEMSIZE 0x1ffc0000 /* memory size */ 211 #define BISOSR_BROKE 0x00001000 /* broke */ 212 213 /* bits in bi_rxcd */ 214 #define BIRXCD_BUSY2 0x80000000 /* busy 2 */ 215 #define BIRXCD_NODE2 0x0f000000 /* node id 2 */ 216 #define BIRXCD_CHAR2 0x00ff0000 /* character 2 */ 217 #define BIRXCD_BUSY1 0x00008000 /* busy 1 */ 218 #define BIRXCD_NODE1 0x00000f00 /* node id 1 */ 219 #define BIRXCD_CHAR1 0x000000ff /* character 1 */ 220