1 /* 2 * Copyright (c) 1982, 1986 Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms are permitted 6 * provided that the above copyright notice and this paragraph are 7 * duplicated in all such forms and that any documentation, 8 * advertising materials, and other materials related to such 9 * distribution and use acknowledge that the software was developed 10 * by the University of California, Berkeley. The name of the 11 * University may not be used to endorse or promote products derived 12 * from this software without specific prior written permission. 13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 15 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 16 * 17 * @(#)if_accreg.h 7.2 (Berkeley) 08/04/88 18 */ 19 20 /* 21 * ACC LH/DH-11 interface 22 */ 23 24 struct accdma { 25 short csr; /* control and status */ 26 short db; /* data buffer */ 27 u_short ba; /* buss address */ 28 short wc; /* word count */ 29 }; 30 31 struct accdevice { 32 struct accdma input; 33 struct accdma output; 34 }; 35 36 #define icsr input.csr 37 #define iba input.ba 38 #define iwc input.wc 39 #define ocsr output.csr 40 #define oba output.ba 41 #define owc output.wc 42 43 /* 44 * Bits Common to both input and out CSR's 45 */ 46 #define ACC_ERR 0x8000 /* error present */ 47 #define ACC_NXM 0x4000 /* non-existant memory */ 48 #define ACC_RDY 0x0080 /* ready */ 49 #define ACC_IE 0x0040 /* interrupt enable */ 50 #define ACC_RESET 0x0002 /* reset interface */ 51 #define ACC_GO 0x0001 /* start operation */ 52 53 /* 54 * Input Control Status Register 55 */ 56 #define IN_EOM 0x2000 /* end-of-message recieved */ 57 #define IN_HRDY 0x0800 /* host ready */ 58 #define IN_IMPBSY 0x0400 /* IMP not ready */ 59 #define IN_RMR 0x0200 /* receive master ready error */ 60 #define IN_IBF 0x0100 /* input data buffer full */ 61 #define IN_WEN 0x0008 /* write enable */ 62 #define IN_MRDY 0x0004 /* master ready */ 63 64 #define ACC_INBITS \ 65 "\20\20ERR\17NXM\16EOM\14HRDY\13IMPBSY\12RMR\11IBF\10RDY\7IE\ 66 \4WEN\3MRDY\2RESET\1GO" 67 68 /* 69 * Output Control Status Register 70 */ 71 #define OUT_TMR 0x0200 /* transmit master ready error */ 72 #define OUT_BBACK 0x0008 /* bus back */ 73 #define OUT_ENLB 0x0004 /* enable last bit */ 74 75 #define ACC_OUTBITS \ 76 "\20\20ERR\17NXM\12TMR\10RDY\7IE\4BBACK\3ENLB\2RESET\1GO" 77