1 /* if_accreg.h 4.2 82/02/21 */ 2 3 /* 4 * ACC LH/DH-11 interface 5 */ 6 7 struct accdma { 8 short csr; /* control and status */ 9 short db; /* data buffer */ 10 u_short ba; /* buss address */ 11 short wc; /* word count */ 12 }; 13 14 struct accdevice { 15 struct accdma input; 16 struct accdma output; 17 }; 18 19 #define icsr input.csr 20 #define iba input.ba 21 #define iwc input.wc 22 #define ocsr output.csr 23 #define oba output.ba 24 #define owc output.wc 25 26 /* 27 * Bits Common to both input and out CSR's 28 */ 29 #define ACC_ERR 0x8000 /* error present */ 30 #define ACC_NXM 0x4000 /* non-existant memory */ 31 #define ACC_RDY 0x0080 /* ready */ 32 #define ACC_IE 0x0040 /* interrupt enable */ 33 #define ACC_RESET 0x0002 /* reset interface */ 34 #define ACC_GO 0x0001 /* start operation */ 35 36 /* 37 * Input Control Status Register 38 */ 39 #define IN_EOM 0x2000 /* end-of-message recieved */ 40 #define IN_HRDY 0x0800 /* host ready */ 41 #define IN_IMPBSY 0x0400 /* IMP not ready */ 42 #define IN_RMR 0x0200 /* receive master ready error */ 43 #define IN_IBF 0x0100 /* input data buffer full */ 44 #define IN_WEN 0x0008 /* write enable */ 45 #define IN_MRDY 0x0004 /* master ready */ 46 47 #define ACC_INBITS \ 48 "\20\20ERR\17NXM\16EOM\14HRDY\13IMPBSY\12RMR\11IBF\10RDY\7IE\ 49 \4WEN\3MRDY\2RESET\1GO" 50 51 /* 52 * Output Control Status Register 53 */ 54 #define OUT_TMR 0x0200 /* transmit master ready error */ 55 #define OUT_BBACK 0x0008 /* bus back */ 56 #define OUT_ENLB 0x0004 /* enable last bit */ 57 58 #define ACC_OUTBITS \ 59 "\20\20ERR\17NXM\12TMR\10RDY\7IE\4BBACK\3ENLB\2RESET\1GO" 60