1 /* 2 * Copyright (c) 1982, 1986 Regents of the University of California. 3 * All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * @(#)if_dereg.h 7.3 (Berkeley) 06/28/90 8 */ 9 10 /* 11 * DEC DEUNA interface 12 */ 13 struct dedevice { 14 union { 15 short p0_w; 16 char p0_b[2]; 17 } u_p0; 18 #define pcsr0 u_p0.p0_w 19 #define pclow u_p0.p0_b[0] 20 #define pchigh u_p0.p0_b[1] 21 short pcsr1; 22 short pcsr2; 23 short pcsr3; 24 }; 25 26 /* 27 * PCSR 0 bit descriptions 28 */ 29 #define PCSR0_SERI 0x8000 /* Status error interrupt */ 30 #define PCSR0_PCEI 0x4000 /* Port command error interrupt */ 31 #define PCSR0_RXI 0x2000 /* Receive done interrupt */ 32 #define PCSR0_TXI 0x1000 /* Transmit done interrupt */ 33 #define PCSR0_DNI 0x0800 /* Done interrupt */ 34 #define PCSR0_RCBI 0x0400 /* Receive buffer unavail intrpt */ 35 #define PCSR0_FATI 0x0100 /* Fatal error interrupt */ 36 #define PCSR0_INTR 0x0080 /* Interrupt summary */ 37 #define PCSR0_INTE 0x0040 /* Interrupt enable */ 38 #define PCSR0_RSET 0x0020 /* DEUNA reset */ 39 #define PCSR0_CMASK 0x000f /* command mask */ 40 41 #define PCSR0_BITS "\20\20SERI\17PCEI\16RXI\15TXI\14DNI\13RCBI\11FATI\10INTR\7INTE\6RSET" 42 43 /* bits 0-3 are for the PORT_COMMAND */ 44 #define CMD_NOOP 0x0 45 #define CMD_GETPCBB 0x1 /* Get PCB Block */ 46 #define CMD_GETCMD 0x2 /* Execute command in PCB */ 47 #define CMD_STEST 0x3 /* Self test mode */ 48 #define CMD_START 0x4 /* Reset xmit and receive ring ptrs */ 49 #define CMD_BOOT 0x5 /* Boot DEUNA */ 50 #define CMD_PDMD 0x8 /* Polling demand */ 51 #define CMD_TMRO 0x9 /* Sanity timer on */ 52 #define CMD_TMRF 0xa /* Sanity timer off */ 53 #define CMD_RSTT 0xb /* Reset sanity timer */ 54 #define CMD_STOP 0xf /* Suspend operation */ 55 56 /* 57 * PCSR 1 bit descriptions 58 */ 59 #define PCSR1_XPWR 0x8000 /* Transceiver power BAD */ 60 #define PCSR1_ICAB 0x4000 /* Interconnect cabling BAD */ 61 #define PCSR1_STCODE 0x3f00 /* Self test error code */ 62 #define PCSR1_PCTO 0x0080 /* Port command timed out */ 63 #define PCSR1_ILLINT 0x0040 /* Illegal interrupt */ 64 #define PCSR1_TIMEOUT 0x0020 /* Timeout */ 65 #define PCSR1_POWER 0x0010 /* Power fail */ 66 #define PCSR1_RMTC 0x0008 /* Remote console reserved */ 67 #define PCSR1_STMASK 0x0007 /* State */ 68 69 /* bit 0-3 are for STATE */ 70 #define STAT_RESET 0x0 71 #define STAT_PRIMLD 0x1 /* Primary load */ 72 #define STAT_READY 0x2 73 #define STAT_RUN 0x3 74 #define STAT_UHALT 0x5 /* UNIBUS halted */ 75 #define STAT_NIHALT 0x6 /* NI halted */ 76 #define STAT_NIUHALT 0x7 /* NI and UNIBUS Halted */ 77 78 #define PCSR1_BITS "\20\20XPWR\17ICAB\10PCTO\7ILLINT\6TIMEOUT\5POWER\4RMTC" 79 80 /* 81 * Port Control Block Base 82 */ 83 struct de_pcbb { 84 short pcbb0; /* function */ 85 short pcbb2; /* command specific */ 86 short pcbb4; 87 short pcbb6; 88 }; 89 90 /* PCBB function codes */ 91 #define FC_NOOP 0x00 /* NO-OP */ 92 #define FC_LSUADDR 0x01 /* Load and start microaddress */ 93 #define FC_RDDEFAULT 0x02 /* Read default physical address */ 94 #define FC_RDPHYAD 0x04 /* Read physical address */ 95 #define FC_WTPHYAD 0x05 /* Write physical address */ 96 #define FC_RDMULTI 0x06 /* Read multicast address list */ 97 #define FC_WTMULTI 0x07 /* Read multicast address list */ 98 #define FC_RDRING 0x08 /* Read ring format */ 99 #define FC_WTRING 0x09 /* Write ring format */ 100 #define FC_RDCNTS 0x0a /* Read counters */ 101 #define FC_RCCNTS 0x0b /* Read and clear counters */ 102 #define FC_RDMODE 0x0c /* Read mode */ 103 #define FC_WTMODE 0x0d /* Write mode */ 104 #define FC_RDSTATUS 0x0e /* Read port status */ 105 #define FC_RCSTATUS 0x0f /* Read and clear port status */ 106 #define FC_DUMPMEM 0x10 /* Dump internal memory */ 107 #define FC_LOADMEM 0x11 /* Load internal memory */ 108 #define FC_RDSYSID 0x12 /* Read system ID parameters */ 109 #define FC_WTSYSID 0x13 /* Write system ID parameters */ 110 #define FC_RDSERAD 0x14 /* Read load server address */ 111 #define FC_WTSERAD 0x15 /* Write load server address */ 112 113 /* 114 * Unibus Data Block Base (UDBB) for ring buffers 115 */ 116 struct de_udbbuf { 117 short b_tdrbl; /* Transmit desc ring base low 16 bits */ 118 char b_tdrbh; /* Transmit desc ring base high 2 bits */ 119 char b_telen; /* Length of each transmit entry */ 120 short b_trlen; /* Number of entries in the XMIT desc ring */ 121 short b_rdrbl; /* Receive desc ring base low 16 bits */ 122 char b_rdrbh; /* Receive desc ring base high 2 bits */ 123 char b_relen; /* Length of each receive entry */ 124 short b_rrlen; /* Number of entries in the RECV desc ring */ 125 }; 126 127 /* 128 * Transmit/Receive Ring Entry 129 */ 130 struct de_ring { 131 short r_slen; /* Segment length */ 132 short r_segbl; /* Segment address (low 16 bits) */ 133 char r_segbh; /* Segment address (hi 2 bits) */ 134 u_char r_flags; /* Status flags */ 135 u_short r_tdrerr; /* Errors */ 136 #define r_lenerr r_tdrerr 137 short r_rid; /* Request ID */ 138 }; 139 140 #define XFLG_OWN 0x80 /* If 0 then owned by driver */ 141 #define XFLG_ERRS 0x40 /* Error summary */ 142 #define XFLG_MTCH 0x20 /* Address match on xmit request */ 143 #define XFLG_MORE 0x10 /* More than one entry required */ 144 #define XFLG_ONE 0x08 /* One collision encountered */ 145 #define XFLG_DEF 0x04 /* Transmit deferred */ 146 #define XFLG_STP 0x02 /* Start of packet */ 147 #define XFLG_ENP 0x01 /* End of packet */ 148 149 #define XFLG_BITS "\10\10OWN\7ERRS\6MTCH\5MORE\4ONE\3DEF\2STP\1ENP" 150 151 #define XERR_BUFL 0x8000 /* Buffer length error */ 152 #define XERR_UBTO 0x4000 /* UNIBUS tiemout 153 #define XERR_LCOL 0x1000 /* Late collision */ 154 #define XERR_LCAR 0x0800 /* Loss of carrier */ 155 #define XERR_RTRY 0x0400 /* Failed after 16 retries */ 156 #define XERR_TDR 0x03ff /* TDR value */ 157 158 #define XERR_BITS "\20\20BUFL\17UBTO\15LCOL\14LCAR\13RTRY" 159 160 #define RFLG_OWN 0x80 /* If 0 then owned by driver */ 161 #define RFLG_ERRS 0x40 /* Error summary */ 162 #define RFLG_FRAM 0x20 /* Framing error */ 163 #define RFLG_OFLO 0x10 /* Message overflow */ 164 #define RFLG_CRC 0x08 /* CRC error */ 165 #define RFLG_STP 0x02 /* Start of packet */ 166 #define RFLG_ENP 0x01 /* End of packet */ 167 168 #define RFLG_BITS "\10\10OWN\7ERRS\6FRAM\5OFLO\4CRC\2STP\1ENP" 169 170 #define RERR_BUFL 0x8000 /* Buffer length error */ 171 #define RERR_UBTO 0x4000 /* UNIBUS tiemout */ 172 #define RERR_NCHN 0x2000 /* No data chaining */ 173 #define RERR_MLEN 0x0fff /* Message length */ 174 175 #define RERR_BITS "\20\20BUFL\17UBTO\16NCHN" 176 177 /* mode description bits */ 178 #define MOD_HDX 0x0001 /* Half duplex mode */ 179 #define MOD_LOOP 0x0004 /* Enable internal loopback */ 180 #define MOD_DTCR 0x0008 /* Disables CRC generation */ 181 #define MOD_DMNT 0x0200 /* Disable maintenance features */ 182 #define MOD_ECT 0x0400 /* Enable collision test */ 183 #define MOD_TPAD 0x1000 /* Transmit message pad enable */ 184 #define MOD_DRDC 0x2000 /* Disable data chaining */ 185 #define MOD_ENAL 0x4000 /* Enable all multicast */ 186 #define MOD_PROM 0x8000 /* Enable promiscuous mode */ 187 188 struct de_buf { 189 struct ether_header db_head; /* header */ 190 char db_data[ETHERMTU]; /* packet data */ 191 int db_crc; /* CRC - on receive only */ 192 }; 193