1 /* 2 * Copyright (c) 1982, 1986 Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms are permitted 6 * provided that the above copyright notice and this paragraph are 7 * duplicated in all such forms and that any documentation, 8 * advertising materials, and other materials related to such 9 * distribution and use acknowledge that the software was developed 10 * by the University of California, Berkeley. The name of the 11 * University may not be used to endorse or promote products derived 12 * from this software without specific prior written permission. 13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 15 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 16 * 17 * @(#)if_dereg.h 7.2 (Berkeley) 08/04/88 18 */ 19 20 /* 21 * DEC DEUNA interface 22 */ 23 struct dedevice { 24 union { 25 short p0_w; 26 char p0_b[2]; 27 } u_p0; 28 #define pcsr0 u_p0.p0_w 29 #define pclow u_p0.p0_b[0] 30 #define pchigh u_p0.p0_b[1] 31 short pcsr1; 32 short pcsr2; 33 short pcsr3; 34 }; 35 36 /* 37 * PCSR 0 bit descriptions 38 */ 39 #define PCSR0_SERI 0x8000 /* Status error interrupt */ 40 #define PCSR0_PCEI 0x4000 /* Port command error interrupt */ 41 #define PCSR0_RXI 0x2000 /* Receive done interrupt */ 42 #define PCSR0_TXI 0x1000 /* Transmit done interrupt */ 43 #define PCSR0_DNI 0x0800 /* Done interrupt */ 44 #define PCSR0_RCBI 0x0400 /* Receive buffer unavail intrpt */ 45 #define PCSR0_FATI 0x0100 /* Fatal error interrupt */ 46 #define PCSR0_INTR 0x0080 /* Interrupt summary */ 47 #define PCSR0_INTE 0x0040 /* Interrupt enable */ 48 #define PCSR0_RSET 0x0020 /* DEUNA reset */ 49 #define PCSR0_CMASK 0x000f /* command mask */ 50 51 #define PCSR0_BITS "\20\20SERI\17PCEI\16RXI\15TXI\14DNI\13RCBI\11FATI\10INTR\7INTE\6RSET" 52 53 /* bits 0-3 are for the PORT_COMMAND */ 54 #define CMD_NOOP 0x0 55 #define CMD_GETPCBB 0x1 /* Get PCB Block */ 56 #define CMD_GETCMD 0x2 /* Execute command in PCB */ 57 #define CMD_STEST 0x3 /* Self test mode */ 58 #define CMD_START 0x4 /* Reset xmit and receive ring ptrs */ 59 #define CMD_BOOT 0x5 /* Boot DEUNA */ 60 #define CMD_PDMD 0x8 /* Polling demand */ 61 #define CMD_TMRO 0x9 /* Sanity timer on */ 62 #define CMD_TMRF 0xa /* Sanity timer off */ 63 #define CMD_RSTT 0xb /* Reset sanity timer */ 64 #define CMD_STOP 0xf /* Suspend operation */ 65 66 /* 67 * PCSR 1 bit descriptions 68 */ 69 #define PCSR1_XPWR 0x8000 /* Transceiver power BAD */ 70 #define PCSR1_ICAB 0x4000 /* Interconnect cabling BAD */ 71 #define PCSR1_STCODE 0x3f00 /* Self test error code */ 72 #define PCSR1_PCTO 0x0080 /* Port command timed out */ 73 #define PCSR1_ILLINT 0x0040 /* Illegal interrupt */ 74 #define PCSR1_TIMEOUT 0x0020 /* Timeout */ 75 #define PCSR1_POWER 0x0010 /* Power fail */ 76 #define PCSR1_RMTC 0x0008 /* Remote console reserved */ 77 #define PCSR1_STMASK 0x0007 /* State */ 78 79 /* bit 0-3 are for STATE */ 80 #define STAT_RESET 0x0 81 #define STAT_PRIMLD 0x1 /* Primary load */ 82 #define STAT_READY 0x2 83 #define STAT_RUN 0x3 84 #define STAT_UHALT 0x5 /* UNIBUS halted */ 85 #define STAT_NIHALT 0x6 /* NI halted */ 86 #define STAT_NIUHALT 0x7 /* NI and UNIBUS Halted */ 87 88 #define PCSR1_BITS "\20\20XPWR\17ICAB\10PCTO\7ILLINT\6TIMEOUT\5POWER\4RMTC" 89 90 /* 91 * Port Control Block Base 92 */ 93 struct de_pcbb { 94 short pcbb0; /* function */ 95 short pcbb2; /* command specific */ 96 short pcbb4; 97 short pcbb6; 98 }; 99 100 /* PCBB function codes */ 101 #define FC_NOOP 0x00 /* NO-OP */ 102 #define FC_LSUADDR 0x01 /* Load and start microaddress */ 103 #define FC_RDDEFAULT 0x02 /* Read default physical address */ 104 #define FC_RDPHYAD 0x04 /* Read physical address */ 105 #define FC_WTPHYAD 0x05 /* Write physical address */ 106 #define FC_RDMULTI 0x06 /* Read multicast address list */ 107 #define FC_WTMULTI 0x07 /* Read multicast address list */ 108 #define FC_RDRING 0x08 /* Read ring format */ 109 #define FC_WTRING 0x09 /* Write ring format */ 110 #define FC_RDCNTS 0x0a /* Read counters */ 111 #define FC_RCCNTS 0x0b /* Read and clear counters */ 112 #define FC_RDMODE 0x0c /* Read mode */ 113 #define FC_WTMODE 0x0d /* Write mode */ 114 #define FC_RDSTATUS 0x0e /* Read port status */ 115 #define FC_RCSTATUS 0x0f /* Read and clear port status */ 116 #define FC_DUMPMEM 0x10 /* Dump internal memory */ 117 #define FC_LOADMEM 0x11 /* Load internal memory */ 118 #define FC_RDSYSID 0x12 /* Read system ID parameters */ 119 #define FC_WTSYSID 0x13 /* Write system ID parameters */ 120 #define FC_RDSERAD 0x14 /* Read load server address */ 121 #define FC_WTSERAD 0x15 /* Write load server address */ 122 123 /* 124 * Unibus Data Block Base (UDBB) for ring buffers 125 */ 126 struct de_udbbuf { 127 short b_tdrbl; /* Transmit desc ring base low 16 bits */ 128 char b_tdrbh; /* Transmit desc ring base high 2 bits */ 129 char b_telen; /* Length of each transmit entry */ 130 short b_trlen; /* Number of entries in the XMIT desc ring */ 131 short b_rdrbl; /* Receive desc ring base low 16 bits */ 132 char b_rdrbh; /* Receive desc ring base high 2 bits */ 133 char b_relen; /* Length of each receive entry */ 134 short b_rrlen; /* Number of entries in the RECV desc ring */ 135 }; 136 137 /* 138 * Transmit/Receive Ring Entry 139 */ 140 struct de_ring { 141 short r_slen; /* Segment length */ 142 short r_segbl; /* Segment address (low 16 bits) */ 143 char r_segbh; /* Segment address (hi 2 bits) */ 144 u_char r_flags; /* Status flags */ 145 u_short r_tdrerr; /* Errors */ 146 #define r_lenerr r_tdrerr 147 short r_rid; /* Request ID */ 148 }; 149 150 #define XFLG_OWN 0x80 /* If 0 then owned by driver */ 151 #define XFLG_ERRS 0x40 /* Error summary */ 152 #define XFLG_MTCH 0x20 /* Address match on xmit request */ 153 #define XFLG_MORE 0x10 /* More than one entry required */ 154 #define XFLG_ONE 0x08 /* One collision encountered */ 155 #define XFLG_DEF 0x04 /* Transmit deferred */ 156 #define XFLG_STP 0x02 /* Start of packet */ 157 #define XFLG_ENP 0x01 /* End of packet */ 158 159 #define XFLG_BITS "\10\10OWN\7ERRS\6MTCH\5MORE\4ONE\3DEF\2STP\1ENP" 160 161 #define XERR_BUFL 0x8000 /* Buffer length error */ 162 #define XERR_UBTO 0x4000 /* UNIBUS tiemout 163 #define XERR_LCOL 0x1000 /* Late collision */ 164 #define XERR_LCAR 0x0800 /* Loss of carrier */ 165 #define XERR_RTRY 0x0400 /* Failed after 16 retries */ 166 #define XERR_TDR 0x03ff /* TDR value */ 167 168 #define XERR_BITS "\20\20BUFL\17UBTO\15LCOL\14LCAR\13RTRY" 169 170 #define RFLG_OWN 0x80 /* If 0 then owned by driver */ 171 #define RFLG_ERRS 0x40 /* Error summary */ 172 #define RFLG_FRAM 0x20 /* Framing error */ 173 #define RFLG_OFLO 0x10 /* Message overflow */ 174 #define RFLG_CRC 0x08 /* CRC error */ 175 #define RFLG_STP 0x02 /* Start of packet */ 176 #define RFLG_ENP 0x01 /* End of packet */ 177 178 #define RFLG_BITS "\10\10OWN\7ERRS\6FRAM\5OFLO\4CRC\2STP\1ENP" 179 180 #define RERR_BUFL 0x8000 /* Buffer length error */ 181 #define RERR_UBTO 0x4000 /* UNIBUS tiemout */ 182 #define RERR_NCHN 0x2000 /* No data chaining */ 183 #define RERR_MLEN 0x0fff /* Message length */ 184 185 #define RERR_BITS "\20\20BUFL\17UBTO\16NCHN" 186 187 /* mode description bits */ 188 #define MOD_HDX 0x0001 /* Half duplex mode */ 189 #define MOD_LOOP 0x0004 /* Enable internal loopback */ 190 #define MOD_DTCR 0x0008 /* Disables CRC generation */ 191 #define MOD_DMNT 0x0200 /* Disable maintenance features */ 192 #define MOD_ECT 0x0400 /* Enable collision test */ 193 #define MOD_TPAD 0x1000 /* Transmit message pad enable */ 194 #define MOD_DRDC 0x2000 /* Disable data chaining */ 195 #define MOD_ENAL 0x4000 /* Enable all multicast */ 196 #define MOD_PROM 0x8000 /* Enable promiscuous mode */ 197 198 struct de_buf { 199 struct ether_header db_head; /* header */ 200 char db_data[ETHERMTU]; /* packet data */ 201 int db_crc; /* CRC - on receive only */ 202 }; 203