1 /* if_dereg.h 6.1 83/11/02 */ 2 /* 3 * DEC DEUNA interface 4 */ 5 struct dedevice { 6 union { 7 short p0_w; 8 char p0_b[2]; 9 } u_p0; 10 #define pcsr0 u_p0.p0_w 11 #define pclow u_p0.p0_b[0] 12 #define pchigh u_p0.p0_b[1] 13 short pcsr1; 14 short pcsr2; 15 short pcsr3; 16 }; 17 18 /* 19 * PCSR 0 bit descriptions 20 */ 21 #define PCSR0_SERI 0x8000 /* Status error interrupt */ 22 #define PCSR0_PCEI 0x4000 /* Port command error interrupt */ 23 #define PCSR0_RXI 0x2000 /* Receive done interrupt */ 24 #define PCSR0_TXI 0x1000 /* Transmit done interrupt */ 25 #define PCSR0_DNI 0x0800 /* Done interrupt */ 26 #define PCSR0_RCBI 0x0400 /* Receive buffer unavail intrpt */ 27 #define PCSR0_FATI 0x0100 /* Fatal error interrupt */ 28 #define PCSR0_INTR 0x0080 /* Interrupt summary */ 29 #define PCSR0_INTE 0x0040 /* Interrupt enable */ 30 #define PCSR0_RSET 0x0020 /* DEUNA reset */ 31 #define PCSR0_CMASK 0x000f /* command mask */ 32 33 #define PCSR0_BITS "\20\20SERI\17PCEI\16RXI\15TXI\14DNI\13RCBI\11FATI\10INTR\7INTE\6RSET" 34 35 /* bits 0-3 are for the PORT_COMMAND */ 36 #define CMD_NOOP 0x0 37 #define CMD_GETPCBB 0x1 /* Get PCB Block */ 38 #define CMD_GETCMD 0x2 /* Execute command in PCB */ 39 #define CMD_STEST 0x3 /* Self test mode */ 40 #define CMD_START 0x4 /* Reset xmit and receive ring ptrs */ 41 #define CMD_BOOT 0x5 /* Boot DEUNA */ 42 #define CMD_PDMD 0x8 /* Polling demand */ 43 #define CMD_TMRO 0x9 /* Sanity timer on */ 44 #define CMD_TMRF 0xa /* Sanity timer off */ 45 #define CMD_RSTT 0xb /* Reset sanity timer */ 46 #define CMD_STOP 0xf /* Suspend operation */ 47 48 /* 49 * PCSR 1 bit descriptions 50 */ 51 #define PCSR1_XPWR 0x8000 /* Transceiver power BAD */ 52 #define PCSR1_ICAB 0x4000 /* Interconnect cabling BAD */ 53 #define PCSR1_STCODE 0x3f00 /* Self test error code */ 54 #define PCSR1_PCTO 0x0080 /* Port command timed out */ 55 #define PCSR1_ILLINT 0x0040 /* Illegal interrupt */ 56 #define PCSR1_TIMEOUT 0x0020 /* Timeout */ 57 #define PCSR1_POWER 0x0010 /* Power fail */ 58 #define PCSR1_RMTC 0x0008 /* Remote console reserved */ 59 #define PCSR1_STMASK 0x0007 /* State */ 60 61 /* bit 0-3 are for STATE */ 62 #define STAT_RESET 0x0 63 #define STAT_PRIMLD 0x1 /* Primary load */ 64 #define STAT_READY 0x2 65 #define STAT_RUN 0x3 66 #define STAT_UHALT 0x5 /* UNIBUS halted */ 67 #define STAT_NIHALT 0x6 /* NI halted */ 68 #define STAT_NIUHALT 0x7 /* NI and UNIBUS Halted */ 69 70 #define PCSR1_BITS "\20\20XPWR\17ICAB\10PCTO\7ILLINT\6TIMEOUT\5POWER\4RMTC" 71 72 /* 73 * Port Control Block Base 74 */ 75 struct de_pcbb { 76 short pcbb0; /* function */ 77 short pcbb2; /* command specific */ 78 short pcbb4; 79 short pcbb6; 80 }; 81 82 /* PCBB function codes */ 83 #define FC_NOOP 0x00 /* NO-OP */ 84 #define FC_LSUADDR 0x01 /* Load and start microaddress */ 85 #define FC_RDDEFAULT 0x02 /* Read default physical address */ 86 #define FC_RDPHYAD 0x04 /* Read physical address */ 87 #define FC_WTPHYAD 0x05 /* Write physical address */ 88 #define FC_RDMULTI 0x06 /* Read multicast address list */ 89 #define FC_WTMULTI 0x07 /* Read multicast address list */ 90 #define FC_RDRING 0x08 /* Read ring format */ 91 #define FC_WTRING 0x09 /* Write ring format */ 92 #define FC_RDCNTS 0x0a /* Read counters */ 93 #define FC_RCCNTS 0x0b /* Read and clear counters */ 94 #define FC_RDMODE 0x0c /* Read mode */ 95 #define FC_WTMODE 0x0d /* Write mode */ 96 #define FC_RDSTATUS 0x0e /* Read port status */ 97 #define FC_RCSTATUS 0x0f /* Read and clear port status */ 98 #define FC_DUMPMEM 0x10 /* Dump internal memory */ 99 #define FC_LOADMEM 0x11 /* Load internal memory */ 100 #define FC_RDSYSID 0x12 /* Read system ID parameters */ 101 #define FC_WTSYSID 0x13 /* Write system ID parameters */ 102 #define FC_RDSERAD 0x14 /* Read load server address */ 103 #define FC_WTSERAD 0x15 /* Write load server address */ 104 105 /* 106 * Unibus Data Block Base (UDBB) for ring buffers 107 */ 108 struct de_udbbuf { 109 short b_tdrbl; /* Transmit desc ring base low 16 bits */ 110 char b_tdrbh; /* Transmit desc ring base high 2 bits */ 111 char b_telen; /* Length of each transmit entry */ 112 short b_trlen; /* Number of entries in the XMIT desc ring */ 113 short b_rdrbl; /* Receive desc ring base low 16 bits */ 114 char b_rdrbh; /* Receive desc ring base high 2 bits */ 115 char b_relen; /* Length of each receive entry */ 116 short b_rrlen; /* Number of entries in the RECV desc ring */ 117 }; 118 119 /* 120 * Transmit/Receive Ring Entry 121 */ 122 struct de_ring { 123 short r_slen; /* Segment length */ 124 short r_segbl; /* Segment address (low 16 bits) */ 125 char r_segbh; /* Segment address (hi 2 bits) */ 126 u_char r_flags; /* Status flags */ 127 u_short r_tdrerr; /* Errors */ 128 #define r_lenerr r_tdrerr 129 short r_rid; /* Request ID */ 130 }; 131 132 #define XFLG_OWN 0x80 /* If 0 then owned by driver */ 133 #define XFLG_ERRS 0x40 /* Error summary */ 134 #define XFLG_MTCH 0x20 /* Address match on xmit request */ 135 #define XFLG_MORE 0x10 /* More than one entry required */ 136 #define XFLG_ONE 0x08 /* One collision encountered */ 137 #define XFLG_DEF 0x04 /* Transmit deferred */ 138 #define XFLG_STP 0x02 /* Start of packet */ 139 #define XFLG_ENP 0x01 /* End of packet */ 140 141 #define XFLG_BITS "\10\10OWN\7ERRS\6MTCH\5MORE\4ONE\3DEF\2STP\1ENP" 142 143 #define XERR_BUFL 0x8000 /* Buffer length error */ 144 #define XERR_UBTO 0x4000 /* UNIBUS tiemout 145 #define XERR_LCOL 0x1000 /* Late collision */ 146 #define XERR_LCAR 0x0800 /* Loss of carrier */ 147 #define XERR_RTRY 0x0400 /* Failed after 16 retries */ 148 #define XERR_TDR 0x03ff /* TDR value */ 149 150 #define XERR_BITS "\20\20BUFL\17UBTO\15LCOL\14LCAR\13RTRY" 151 152 #define RFLG_OWN 0x80 /* If 0 then owned by driver */ 153 #define RFLG_ERRS 0x40 /* Error summary */ 154 #define RFLG_FRAM 0x20 /* Framing error */ 155 #define RFLG_OFLO 0x10 /* Message overflow */ 156 #define RFLG_CRC 0x08 /* CRC error */ 157 #define RFLG_STP 0x02 /* Start of packet */ 158 #define RFLG_ENP 0x01 /* End of packet */ 159 160 #define RFLG_BITS "\10\10OWN\7ERRS\6FRAM\5OFLO\4CRC\2STP\1ENP" 161 162 #define RERR_BUFL 0x8000 /* Buffer length error */ 163 #define RERR_UBTO 0x4000 /* UNIBUS tiemout */ 164 #define RERR_NCHN 0x2000 /* No data chaining */ 165 #define RERR_MLEN 0x0fff /* Message length */ 166 167 #define RERR_BITS "\20\20BUFL\17UBTO\16NCHN" 168 169 /* mode description bits */ 170 #define MOD_HDX 0x0001 /* Half duplex mode */ 171 #define MOD_LOOP 0x0004 /* Enable internal loopback */ 172 #define MOD_DTCR 0x0008 /* Disables CRC generation */ 173 #define MOD_DMNT 0x0200 /* Disable maintenance features */ 174 #define MOD_ECT 0x0400 /* Enable collision test */ 175 #define MOD_TPAD 0x1000 /* Transmit message pad enable */ 176 #define MOD_DRDC 0x2000 /* Disable data chaining */ 177 #define MOD_ENAL 0x4000 /* Enable all multicast */ 178 #define MOD_PROM 0x8000 /* Enable promiscuous mode */ 179 180 struct de_buf { 181 struct ether_header db_head; /* header */ 182 char db_data[ETHERMTU]; /* packet data */ 183 int db_crc; /* CRC - on receive only */ 184 }; 185