1 /* if_dmc.h 4.2 82/02/21 */ 2 3 /* 4 * DMC-11 Interface 5 */ 6 7 struct dmcdevice { 8 union { 9 char b[8]; 10 short w[4]; 11 } un; 12 }; 13 14 #define bsel0 un.b[0] 15 #define bsel1 un.b[1] 16 #define bsel2 un.b[2] 17 #define bsel3 un.b[3] 18 #define bsel4 un.b[4] 19 #define bsel5 un.b[5] 20 #define bsel6 un.b[6] 21 #define bsel7 un.b[7] 22 #define sel0 un.w[0] 23 #define sel2 un.w[1] 24 #define sel4 un.w[2] 25 #define sel6 un.w[3] 26 27 #define DMCMTU (2048) 28 29 #define RDYSCAN 16 /* loop delay for RDYI after RQI */ 30 31 /* defines for bsel0 */ 32 #define DMC_BACCI 0 33 #define DMC_CNTLI 1 34 #define DMC_PERR 2 35 #define DMC_BASEI 3 36 #define DMC_WRITE 0 /* transmit block */ 37 #define DMC_READ 4 /* read block */ 38 #define DMC_RQI 0040 /* port request bit */ 39 #define DMC_IEI 0100 /* enable input interrupts */ 40 #define DMC_RDYI 0200 /* port ready */ 41 42 /* defines for bsel1 */ 43 #define DMC_MCLR 0100 /* DMC11 Master Clear */ 44 #define DMC_RUN 0200 /* clock running */ 45 46 /* defines for bsel2 */ 47 #define DMC_BACCO 0 48 #define DMC_CNTLO 1 49 #define DMC_OUX 0 /* transmit block */ 50 #define DMC_OUR 4 /* read block */ 51 #define DMC_IEO 0100 /* enable output interrupts */ 52 #define DMC_RDYO 0200 /* port available */ 53 54 /* defines for CNTLI mode */ 55 #define DMC_HDPLX 02000 /* half duplex DDCMP operation */ 56 #define DMC_SEC 04000 /* half duplex secondary station */ 57 #define DMC_MAINT 00400 /* enter maintenance mode */ 58 59 /* defines for BACCI/O and BASEI mode */ 60 #define DMC_XMEM 0140000 /* xmem bit position */ 61 #define DMC_CCOUNT 0037777 /* character count mask */ 62 #define DMC_RESUME 0002000 /* resume (BASEI only) */ 63 64 /* defines for CNTLO */ 65 #define DMC_CNTMASK 01777 66 #define DMC_FATAL 01620 67