1 /* 2 * Copyright (c) 1982, 1986 Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms are permitted 6 * provided that the above copyright notice and this paragraph are 7 * duplicated in all such forms and that any documentation, 8 * advertising materials, and other materials related to such 9 * distribution and use acknowledge that the software was developed 10 * by the University of California, Berkeley. The name of the 11 * University may not be used to endorse or promote products derived 12 * from this software without specific prior written permission. 13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 15 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 16 * 17 * @(#)if_ecreg.h 7.2 (Berkeley) 08/04/88 18 */ 19 20 /* 21 * 3Com Ethernet controller registers. 22 */ 23 struct ecdevice { 24 short ec_rcr; /* Receive Control Register */ 25 short ec_xcr; /* Transmit Control Register */ 26 }; 27 28 /* 29 * Control and status bits -- rcr 30 */ 31 #define EC_SPIE 0x8000 /* set parity interrupt enable */ 32 #define EC_ASTEP 0x4000 /* increment address counter */ 33 #define EC_AROM 0x2000 /* 1: Use address ROM, 0: use RAM */ 34 #define EC_PE 0x2000 /* Parity error */ 35 #define EC_AWCLK 0x1000 /* address write clock bit */ 36 #define EC_PIE 0x1000 /* Parity interrupt enable (read) */ 37 #define EC_ADATA 0x0f00 /* address/filtering */ 38 #define EC_RDONE 0x0080 /* receive done */ 39 #define EC_MDISAB 0x0080 /* memory disable */ 40 #define EC_RINTEN 0x0040 /* receive interrupt enable */ 41 #define EC_RCLR 0x0020 /* clear RDONE bit */ 42 #define EC_RWBN 0x0010 /* submit buffer for receive */ 43 #define EC_RBN 0x000f /* buffer number */ 44 45 #define EC_RBITS "\10\16PE\15PIE\10RDONE\7RINTEN" 46 47 /* 48 * Control and status bits -- xcr 49 */ 50 #define EC_JAM 0x8000 /* collision dectected */ 51 #define EC_JINTEN 0x4000 /* collision interrupt enable */ 52 #define EC_JCLR 0x2000 /* clear collision detect */ 53 #define EC_UECLR 0x0100 /* reset controller */ 54 #define EC_XDONE 0x0080 /* transmit done */ 55 #define EC_XINTEN 0x0040 /* transmit interrupt enable */ 56 #define EC_XCLR 0x0020 /* clear XDONE bit */ 57 #define EC_XWBN 0x0010 /* submit buffer for transmit */ 58 #define EC_XBN 0x000f /* buffer number */ 59 60 #define EC_XBITS "\10\20JAM\17JINTEN\10XDONE\7XINTEN" 61 62 /* 63 * Useful combinations 64 */ 65 #define EC_READ (0x600|EC_RINTEN|EC_RWBN) 66 #define EC_WRITE (EC_JINTEN|EC_XINTEN|EC_XWBN) 67 #define EC_CLEAR (EC_JINTEN|EC_XINTEN|EC_JCLR) 68 69 /* 70 * Buffer number definitions 71 */ 72 #define ECTBF 0 /* Buffer for transmit */ 73 #define ECRLBF 1 /* First buffer for receive */ 74 #define ECRHBF 15 /* Last buffer for receive */ 75 76 #define ECRDOFF 528 /* Packet offset in read buffer */ 77