1 /* @(#)if_exreg.h 6.1 (Berkeley) 05/01/85 */ 2 /* from @(#)if_exreg.h 1.2 (Excelan) 84/10/12 */ 3 4 struct exdevice { 5 char xd_porta; /* write on porta resets EXOS */ 6 char xd_pad_a; 7 char xd_portb; /* write on portb interrupts EXOS */ 8 /* read on portb returns status bits */ 9 char xd_pad_b; 10 }; 11 12 /* EXOS I/O PORT A write definitions */ 13 #define EX_RESET 0 /* value doesn't really matter... */ 14 15 /* EXOS I/O PORT B write definitions */ 16 #define EX_NTRUPT 0 17 18 /* EXOS I/O PORT B read definitions */ 19 #define EX_TESTOK 1 /* set when self-diagnostics passed */ 20 #define EX_UNREADY (1<<3) /* set until EXOS ready to read from B */ 21 22 /* message buffer status field definitions */ 23 #define MH_OWNER 1 /* mask for status bit for owner */ 24 #define MH_HOST 0 /* if 0, the host owns the buffer */ 25 #define MH_EXOS 1 /* if 1, the EXOS owns the buffer */ 26 27 /* EXOS Link Level request codes */ 28 #define LLTRANSMIT 0xC /* send a packet */ 29 #define LLRTRANSMIT 0xE /* send a packet, and self-receive */ 30 #define LLRECEIVE 0xD /* receive a packet */ 31 #define LLNET_MODE 0x8 /* read/write mode control objects */ 32 #define LLNET_ADDRS 0x9 /* read/write receive address slots */ 33 #define LLNET_RECV 0xA /* read/alter receive slot enable bit */ 34 #define LLNET_STSTCS 0xB /* read/reset network statistics objects */ 35 36 /* Link Level return codes common to all requests */ 37 #define LL_OK 0 /* successful completion */ 38 #define LLX_MODE 0xA1 /* EXOS not in link level mode (impossible) */ 39 40 /* LLTRANSMIT unique return codes */ 41 #define LLXM_1RTRY 0x1 /* successful xmission, 1 retry */ 42 #define LLXM_RTRYS 0x2 /* successful xmission, more than 1 retry */ 43 #define LLXM_NSQE 0x8 /* successful xmission, no SQE TEST signal */ 44 #define LLXM_CLSN 0x10 /* xmission failed, excess retries */ 45 #define LLXM_NCS 0x20 /* xmission failed, no carrier sense */ 46 #define LLXM_LNGTH 0x40 /* xmission failed, bad packet length */ 47 #define XMIT_BITS "\7\7LENGTH\6CARRIER\5XCLSNS\4SQETST" 48 #define LLXM_ERROR (LLXM_NSQE|LLXM_CLSN|LLXM_NCS|LLXM_LNGTH) 49 50 /* LLRECEIVE unique return codes */ 51 #define LLRC_TRUNC 0x4 /* pkt received, but truncated to fit buffer */ 52 #define LLRC_ALIGN 0x10 /* pkt received, but with alignment error */ 53 #define LLRC_CRC 0x20 /* pkt received, but with CRC error */ 54 #define LLRC_BUFLEN 0x40 /* no pkt received, buffer less than 64 bytes */ 55 /* this should never happen here */ 56 #define RECV_BITS "\7\7BUFLEN\6CRC\5ALIGN\3TRUNC" 57 58 /* LLNET_ADDRS unique return codes */ 59 #define LLNA_BADSLOT 0xD1 /* slot doesn't exist or can't be accessed */ 60 #define LLNA_BADADDR 0xD3 /* invalid address for designated slot */ 61 62 /* LLNET_RECV unique return codes */ 63 #define LLNR_BADSLOT 0xD1 /* slot doesn't exist or can't be accessed */ 64 #define LLNR_BADADDR 0xD2 /* designated slot was empty */ 65 66 /* address slot object indices */ 67 #define NULLSLOT 0 /* the null slot */ 68 #define MINMCSLOT 1 /* minimum multicast slot index */ 69 #define MAXMCSLOT 8 /* default maximum multicast slot index */ 70 #define PHYSSLOT 253 /* physical slot index */ 71 #define UNVRSSLOT 254 /* universal slot index */ 72 #define BROADSLOT 255 /* broadcast slot index */ 73 74 /* request mask bit definitions */ 75 #define WRITE_OBJ 1 /* write the object */ 76 #define READ_OBJ 2 /* read the object */ 77 #define ENABLE_RCV 4 /* enable reception on designated slot */ 78 79 /* NET_MODE options mask bit definitions */ 80 #define OPT_ALIGN 0x10 /* receive packets with alignment errors */ 81 #define OPT_CRC 0x20 /* receive packets with CRC errors */ 82 #define OPT_DSABLE 0x80 /* disconnect controller hardware */ 83 84 /* NET_MODE mode field value definitions */ 85 #define MODE_OFF 0 /* stop transmission and reception */ 86 #define MODE_PERF 1 /* perfect multicast address filtering */ 87 #define MODE_HW 2 /* hardware-only multicast address filtering */ 88 #define MODE_PROM 3 /* promiscuous reception */ 89 90 #define NFRAGMENTS 1 /* number fragments that the EXOS will scatter/gather */ 91 #define EXMAXRBUF 1520 /* per EXOS 101 manual 5.3.7 (maybe 1518 would do) */ 92 93 /* 94 * N.B. Structures below are carefully constructed so that 95 * they correspond to the message formats that NX firmware 96 * defines. None of them should contain any compiler-instigated 97 * padding. Be especially careful about VAX C longword alignment! 98 */ 99 100 struct stat_array { 101 u_long sa_fsent; /* frames sent without errors */ 102 u_long sa_xsclsn; /* frames aborted excess collisions */ 103 u_long sa_nsqe; /* frames subject to heartbeat failure */ 104 u_long sa_undef; /* undefined (TDR on EXOS 101) */ 105 u_long sa_frcvd; /* frames received no errors */ 106 u_long sa_align; /* frames received alignment error */ 107 u_long sa_crc; /* frames received crc error */ 108 u_long sa_flost; /* frames lost */ 109 }; 110 111 struct buf_blk { /* packet/buffer block descriptor */ 112 u_short bb_len; /* length of block, in bytes */ 113 u_short bb_addr[2]; /* address of block */ 114 /* 115 * Array above is really a single u_long field. 116 * We kludge its definition to defeat word-alignment. 117 * Access would look like: 118 * longaddr = *(u_long *)bp->.mb_er.er_blks[0].bb_addr; 119 */ 120 }; 121 122 struct net_mode { /* read/write mode control objects */ 123 /*12*/ u_char nm_rqst; /* request code */ 124 /*13*/ u_char nm_rply; /* reply code */ 125 /*14*/ u_char nm_mask; /* bit-wise switches for read, write */ 126 /*15*/ u_char nm_optn; /* acceptable packet reception errors */ 127 /*16*/ u_char nm_mode; /* EXOS filtering mode */ 128 /*17*/ 129 }; 130 131 struct net_addrs { /* read/write receive address slots */ 132 /*12*/ u_char na_rqst; /* request code */ 133 /*13*/ u_char na_rply; /* reply code */ 134 /*14*/ u_char na_mask; /* bit-wise switches for read, write */ 135 /*15*/ u_char na_slot; /* index of address slot */ 136 /*16*/ u_char na_addrs[6]; /* address read and/or written */ 137 /*22*/ 138 }; 139 140 struct net_recv { /* read/alter receive slot enable bit */ 141 /*12*/ u_char nr_rqst; /* request code */ 142 /*13*/ u_char nr_rply; /* reply code */ 143 /*14*/ u_char nr_mask; /* bit-wise switches for read, write */ 144 /*15*/ u_char nr_slot; /* index of address slot */ 145 /*16*/ 146 }; 147 148 struct net_ststcs { /* read/reset network statistics objects */ 149 /*12*/ u_char ns_rqst; /* request code */ 150 /*13*/ u_char ns_rply; /* reply code */ 151 /*14*/ u_char ns_mask; /* bit-wise switches for read, write */ 152 /*15*/ u_char ns_rsrv; /* reserved for EXOS */ 153 /*16*/ u_short ns_nobj; /* number of objects to work on */ 154 /*18*/ u_short ns_xobj; /* index of first object to work on */ 155 /*20*/ u_long ns_bufp; /* pointer to statistics buffer */ 156 /*24*/ 157 }; 158 159 struct enet_xmit { /* send a packet on the Ethernet */ 160 /*12*/ u_char et_rqst; /* request code */ 161 /*13*/ u_char et_rply; /* reply code */ 162 /*14*/ u_char et_slot; /* address slot matching dest address */ 163 /*15*/ u_char et_nblock; /* number of blocks composing packet */ 164 /*16*/ struct buf_blk et_blks[NFRAGMENTS]; /* array of block descriptors */ 165 /*22-64*/ 166 }; 167 168 struct enet_recv { /* receive a packet on the Ethernet */ 169 /*12*/ u_char er_rqst; /* request code */ 170 /*13*/ u_char er_rply; /* reply code */ 171 /*14*/ u_char er_slot; /* address slot matching dest address */ 172 /*15*/ u_char er_nblock; /* number of blocks composing buffer */ 173 /*16*/ struct buf_blk er_blks[NFRAGMENTS]; /* array of block descriptors */ 174 /*22-64*/ 175 }; 176 177 /* we send requests and receive replys with the EXOS using this structure */ 178 struct ex_msg { 179 /*00*/ u_short mb_link; /* address of next message buffer */ 180 /*02*/ u_char mb_rsrv; /* reserved for use by EXOS */ 181 /*03*/ u_char mb_status; /* used bit-wise for message protocol */ 182 /*04*/ u_short mb_length; /* length, in bytes, of the rest */ 183 /*06*/ short mb_1rsrv; /* reserved for used by EXOS */ 184 /*08*/ long mb_mid; /* available to user */ 185 /*12*/ union mb_all { 186 struct net_mode mb_net_mode; 187 struct net_addrs mb_net_addrs; 188 struct net_recv mb_net_recv; 189 struct net_ststcs mb_net_ststcs; 190 struct enet_xmit mb_enet_xmit; 191 struct enet_recv mb_enet_recv; 192 } mb_all; 193 /* following field is used only by host, not read by board */ 194 struct ex_msg *mb_next; /* host's pointer to next message */ 195 }; 196 #define mb_nm mb_all.mb_net_mode 197 #define mb_na mb_all.mb_net_addrs 198 #define mb_nr mb_all.mb_net_recv 199 #define mb_ns mb_all.mb_net_ststcs 200 #define mb_et mb_all.mb_enet_xmit 201 #define mb_er mb_all.mb_enet_recv 202 #define mb_rqst mb_nm.nm_rqst 203 #define mb_rply mb_nm.nm_rply 204 #define MBDATALEN (sizeof(union mb_all)+6) 205 206 struct confmsg { 207 /*00*/ u_short cm_1rsrv; /* reserved, must be 1 */ 208 /*02*/ char cm_vc[4]; /* returns ASCII version code */ 209 /*06*/ u_char cm_cc; /* returns config completion code */ 210 /*07*/ u_char cm_opmode; /* specifies operation mode */ 211 /*08*/ u_short cm_dfo; /* specifies host data format option */ 212 /*10*/ u_char cm_dcn1; /* reserved, must be 1 */ 213 /*11*/ u_char cm_2rsrv[2]; /* reserved, must be 0 */ 214 /*13*/ u_char cm_ham; /* specifies host address mode */ 215 /*14*/ u_char cm_3rsrv; /* reserved, must be 0 */ 216 /*15*/ u_char cm_mapsiz; /* reserved, must be 0 */ 217 /*16*/ u_char cm_byteptrn[4]; /* host data format option test pattern */ 218 /*20*/ u_short cm_wordptrn[2]; 219 /*24*/ u_long cm_lwordptrn; 220 /*28*/ u_char cm_rsrvd[20]; 221 /*48*/ u_long cm_mba; /* use 0xFFFFFFFF in link level mode */ 222 /*52*/ u_char cm_nproc; /* use 0xFF in link level mode */ 223 /*53*/ u_char cm_nmbox; /* use 0xFF in link level mode */ 224 /*54*/ u_char cm_nmcast; /* use 0xFF in link level mode */ 225 /*55*/ u_char cm_nhost; /* use 1 in link level mode */ 226 227 /* the next five parameters define the request message queue */ 228 /*56*/ u_long cm_h2xba; /* base address of message queue */ 229 /*60*/ u_short cm_h2xhdr; /* address offset of msg Q header */ 230 /*62*/ u_char cm_h2xtyp; /* interrupt type */ 231 /*63*/ u_char cm_h2xval; /* interrupt value (not used) */ 232 /*64*/ u_short cm_h2xaddr; /* interrupt vector */ 233 /*66*/ u_short cm_h2xpad; /* pad out unused portion of vector */ 234 235 /* the next five parameters define the reply message queue */ 236 /*68*/ u_long cm_x2hba; /* base address of message queue */ 237 /*72*/ u_short cm_x2hhdr; /* address offset of msg Q header */ 238 /*74*/ u_char cm_x2htyp; /* interrupt type */ 239 /*75*/ u_char cm_x2hval; /* interrupt value (not used) */ 240 /*76*/ u_short cm_x2haddr; /* interrupt vector */ 241 /*78*/ u_short cm_x2hpad; /* pad out unused portion of vector */ 242 /*80*/ 243 }; 244 245