1 /* @(#)if_hdhreg.h 7.1 (Berkeley) 06/05/86 */ 2 3 4 /* $Header$ */ 5 6 /* 7 * ACC IF-11/HDH interface 8 */ 9 10 struct hdhregs { /* device registers */ 11 u_short csr; /* control and status register */ 12 u_char iochn; /* logical channel */ 13 u_char ioadx; /* address extension (A16,A17) */ 14 u_short ioadl; /* buffer address (A0-A15) */ 15 u_short iocnt; /* byte count */ 16 u_char iofcn; /* UMC funciton code */ 17 u_char iosbf; /* UMC subfunction code */ 18 u_char ioini; /* comm regs valid flag */ 19 u_char staack; /* interrupt acknowledge flag */ 20 u_char ionmi; /* NMI routine active flag */ 21 u_char ioxfrg; /* UMR transfer grant flag */ 22 u_char stachn; /* interrupt channel number */ 23 u_char statyp; /* interrupt type code */ 24 u_char stacc; /* completion function code */ 25 u_char stacs; /* completion subfunction code */ 26 u_short stacnt; /* completion byte count */ 27 }; 28 29 /* defines for CSR */ 30 31 #define HDH_UER 0100000 /* UMC error condition */ 32 #define HDH_NXM 0040000 /* non-existent memory error */ 33 #define HDH_PER 0020000 /* UNIBUS parity error */ 34 #define HDH_ZRUN 0010000 /* Z80 running */ 35 #define HDH_ZGO 0004000 /* Z80 not in wait state */ 36 #define HDH_MBLK 0000200 /* memory swap state (0=main, 1=srv) */ 37 #define HDH_SRV 0000100 /* select UMC service memory */ 38 #define HDH_MAIN 0000040 /* select UMC main memory */ 39 #define HDH_DMA 0000020 /* DMA enable */ 40 #define HDH_WRT 0000010 /* DMA write enable */ 41 #define HDH_IEN 0000004 /* interrupt enable */ 42 #define HDH_RST 0000002 /* reset */ 43 #define HDH_NMI 0000001 /* cause NMI */ 44 45 #define HDH_BITS \ 46 "\10\20UER\17NXM\16PER\15ZRUN\14ZGO\10MBLK\7SRV\6MAIN\5DMA\4WRT\3IEN\2RST\1NMI" 47 48 /* start i/o function code definitions */ 49 50 #define HDHWRT 0 /* write to if-11 */ 51 #define HDHRDB 1 /* read from if-11 */ 52 #define HDHSTR 2 /* stream flag */ 53 #define HDHEOS 6 /* end of stream flag */ 54 #define HDHABT 8 /* abort flag */ 55 #define HDHUMR 16 /* UMR protocol flag */ 56 57 /* interrupt type definitions */ 58 59 #define HDHSACK 0 /* start i/o ack */ 60 #define HDHDONE 1 /* i/o completion */ 61 #define HDHXREQ 2 /* UMR protocol transfer request */ 62 63 /* i/o completion codes */ 64 65 #define HDHIOCOK 0001 /* successful completion */ 66 #define HDHIOCOKP 0002 /* successful completion, more data pending */ 67 #define HDHIOCABT 0361 /* i/o aborted */ 68 #define HDHIOCERR 0321 /* program error */ 69 #define HDHIOCOVR 0363 /* overrun error */ 70 #define HDHIOCUBE 0374 /* non-existant memory or unibus error */ 71 72 /* UMR protocol transfer grant code definitions */ 73 74 #define HDHXEVN 1 /* start with even address */ 75 #define HDHXODD 2 /* start with odd address */ 76 #define HDHNUMR 4 /* non-UMR transfer */ 77 #define HDHXABT 8 /* abort transfer */ 78 79 /* HDH supervisor request code definitions */ 80 #define HDHINIT 0x42 /* SYSINIT opcode */ 81 82 #define HDHSUP 0xf0 /* supervisor HDH status/line control prefix */ 83 #define HDHIMP 0x400 /* IMP line up modifier */ 84 #define HDHREFL 0x800 /* reflect mode modifier */ 85 #define HDHINLB 0x1000 /* internal loopback modifier */ 86 #define HDHEXLP 0x2000 /* external loopback modifier */ 87 #define HDHRQST (HDHSUP+0x0000) /* line status request */ 88 #define HDHRQUP (HDHSUP+0x0100) /* line up request */ 89 #define HDHRQDN (HDHSUP+0x0200) /* line down request */ 90 91 /* HDH supervisor reply code definitions */ 92 93 #define HDHIACK (HDHSUP+0x4200) /* line init ack */ 94 #define HDHLNUP (HDHSUP+0x0100) /* line up reply */ 95 #define HDHLNDN (HDHSUP+0x0200) /* line down reply */ 96 #define HDHLNACK (HDHSUP+0x0300) /* ack line up request (but line is down now) */ 97 #define HDHTIMO (HDHSUP+0x0400) /* line timeout */ 98 #define HDHLOOP (HDHSUP+0x0500) /* loopback message */ 99 #define HDHDTERR (HDHSUP+0x0600) /* host data error detected */ 100 #define HDHSQRCV (HDHSUP+0x0700) /* HDLC sequence error detected by IMP */ 101 #define HDHSQERR (HDHSUP+0x0800) /* HDLC sequence error detected by if-11 */ 102