1 /* 2 * Copyright (c) 1988 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Digital Equipment Corp. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)if_qe.c 7.16 (Berkeley) 06/28/90 11 */ 12 13 /* from @(#)if_qe.c 1.15 (ULTRIX) 4/16/86 */ 14 15 /**************************************************************** 16 * * 17 * Licensed from Digital Equipment Corporation * 18 * Copyright (c) * 19 * Digital Equipment Corporation * 20 * Maynard, Massachusetts * 21 * 1985, 1986 * 22 * All rights reserved. * 23 * * 24 * The Information in this software is subject to change * 25 * without notice and should not be construed as a commitment * 26 * by Digital Equipment Corporation. Digital makes no * 27 * representations about the suitability of this software for * 28 * any purpose. It is supplied "As Is" without expressed or * 29 * implied warranty. * 30 * * 31 * If the Regents of the University of California or its * 32 * licensees modify the software in a manner creating * 33 * derivative copyright rights, appropriate copyright * 34 * legends may be placed on the derivative work in addition * 35 * to that set forth above. * 36 * * 37 ****************************************************************/ 38 /* --------------------------------------------------------------------- 39 * Modification History 40 * 41 * 15-Apr-86 -- afd 42 * Rename "unused_multi" to "qunused_multi" for extending Generic 43 * kernel to MicroVAXen. 44 * 45 * 18-mar-86 -- jaw br/cvec changed to NOT use registers. 46 * 47 * 12 March 86 -- Jeff Chase 48 * Modified to handle the new MCLGET macro 49 * Changed if_qe_data.c to use more receive buffers 50 * Added a flag to poke with adb to log qe_restarts on console 51 * 52 * 19 Oct 85 -- rjl 53 * Changed the watch dog timer from 30 seconds to 3. VMS is using 54 * less than 1 second in their's. Also turned the printf into an 55 * mprintf. 56 * 57 * 09/16/85 -- Larry Cohen 58 * Add 43bsd alpha tape changes for subnet routing 59 * 60 * 1 Aug 85 -- rjl 61 * Panic on a non-existent memory interrupt and the case where a packet 62 * was chained. The first should never happen because non-existant 63 * memory interrupts cause a bus reset. The second should never happen 64 * because we hang 2k input buffers on the device. 65 * 66 * 1 Aug 85 -- rich 67 * Fixed the broadcast loopback code to handle Clusters without 68 * wedging the system. 69 * 70 * 27 Feb. 85 -- ejf 71 * Return default hardware address on ioctl request. 72 * 73 * 12 Feb. 85 -- ejf 74 * Added internal extended loopback capability. 75 * 76 * 27 Dec. 84 -- rjl 77 * Fixed bug that caused every other transmit descriptor to be used 78 * instead of every descriptor. 79 * 80 * 21 Dec. 84 -- rjl 81 * Added watchdog timer to mask hardware bug that causes device lockup. 82 * 83 * 18 Dec. 84 -- rjl 84 * Reworked driver to use q-bus mapping routines. MicroVAX-I now does 85 * copying instead of m-buf shuffleing. 86 * A number of deficencies in the hardware/firmware were compensated 87 * for. See comments in qestart and qerint. 88 * 89 * 14 Nov. 84 -- jf 90 * Added usage counts for multicast addresses. 91 * Updated general protocol support to allow access to the Ethernet 92 * header. 93 * 94 * 04 Oct. 84 -- jf 95 * Added support for new ioctls to add and delete multicast addresses 96 * and set the physical address. 97 * Add support for general protocols. 98 * 99 * 14 Aug. 84 -- rjl 100 * Integrated Shannon changes. (allow arp above 1024 and ? ) 101 * 102 * 13 Feb. 84 -- rjl 103 * 104 * Initial version of driver. derived from IL driver. 105 * 106 * --------------------------------------------------------------------- 107 */ 108 109 #include "qe.h" 110 #if NQE > 0 111 /* 112 * Digital Q-BUS to NI Adapter 113 */ 114 #include "param.h" 115 #include "systm.h" 116 #include "mbuf.h" 117 #include "buf.h" 118 #include "protosw.h" 119 #include "socket.h" 120 #include "vmmac.h" 121 #include "ioctl.h" 122 #include "errno.h" 123 #include "syslog.h" 124 #include "time.h" 125 #include "kernel.h" 126 127 #include "../net/if.h" 128 #include "../net/netisr.h" 129 #include "../net/route.h" 130 131 #ifdef INET 132 #include "../netinet/in.h" 133 #include "../netinet/in_systm.h" 134 #include "../netinet/in_var.h" 135 #include "../netinet/ip.h" 136 #include "../netinet/if_ether.h" 137 #endif 138 139 #ifdef NS 140 #include "../netns/ns.h" 141 #include "../netns/ns_if.h" 142 #endif 143 144 #ifdef ISO 145 #include "../netiso/iso.h" 146 #include "../netiso/iso_var.h" 147 extern char all_es_snpa[], all_is_snpa[]; 148 #endif 149 150 #include "../vax/pte.h" 151 #include "../vax/cpu.h" 152 #include "../vax/mtpr.h" 153 #include "if_qereg.h" 154 #include "if_uba.h" 155 #include "../vaxuba/ubareg.h" 156 #include "../vaxuba/ubavar.h" 157 158 #if NQE == 1 && !defined(QNIVERT) 159 #define NRCV 15 /* Receive descriptors */ 160 #else 161 #define NRCV 10 /* Receive descriptors */ 162 #endif 163 #define NXMT 5 /* Transmit descriptors */ 164 #define NTOT (NXMT + NRCV) 165 166 #define QETIMEOUT 2 /* transmit timeout, must be > 1 */ 167 #define QESLOWTIMEOUT 40 /* timeout when no xmits in progress */ 168 169 /* 170 * This constant should really be 60 because the qna adds 4 bytes of crc. 171 * However when set to 60 our packets are ignored by deuna's , 3coms are 172 * okay ?????????????????????????????????????????? 173 */ 174 #define MINDATA 64 175 176 /* 177 * Ethernet software status per interface. 178 * 179 * Each interface is referenced by a network interface structure, 180 * qe_if, which the routing code uses to locate the interface. 181 * This structure contains the output queue for the interface, its address, ... 182 */ 183 struct qe_softc { 184 struct arpcom qe_ac; /* Ethernet common part */ 185 #define qe_if qe_ac.ac_if /* network-visible interface */ 186 #define qe_addr qe_ac.ac_enaddr /* hardware Ethernet address */ 187 struct ifubinfo qe_uba; /* Q-bus resources */ 188 struct ifrw qe_ifr[NRCV]; /* for receive buffers; */ 189 struct ifxmt qe_ifw[NXMT]; /* for xmit buffers; */ 190 int qe_flags; /* software state */ 191 #define QEF_RUNNING 0x01 192 #define QEF_SETADDR 0x02 193 #define QEF_FASTTIMEO 0x04 194 int setupaddr; /* mapping info for setup pkts */ 195 int ipl; /* interrupt priority */ 196 struct qe_ring *rringaddr; /* mapping info for rings */ 197 struct qe_ring *tringaddr; /* "" */ 198 struct qe_ring rring[NRCV+1]; /* Receive ring descriptors */ 199 struct qe_ring tring[NXMT+1]; /* Transmit ring descriptors */ 200 u_char setup_pkt[16][8]; /* Setup packet */ 201 int rindex; /* Receive index */ 202 int tindex; /* Transmit index */ 203 int otindex; /* Old transmit index */ 204 int qe_intvec; /* Interrupt vector */ 205 struct qedevice *addr; /* device addr */ 206 int setupqueued; /* setup packet queued */ 207 int nxmit; /* Transmits in progress */ 208 int qe_restarts; /* timeouts */ 209 } qe_softc[NQE]; 210 211 struct uba_device *qeinfo[NQE]; 212 213 extern struct timeval time; 214 215 int qeprobe(), qeattach(), qeintr(), qetimeout(); 216 int qeinit(), qeioctl(), qereset(), qestart(); 217 218 u_short qestd[] = { 0 }; 219 struct uba_driver qedriver = 220 { qeprobe, 0, qeattach, 0, qestd, "qe", qeinfo }; 221 222 #define QEUNIT(x) minor(x) 223 /* 224 * The deqna shouldn't receive more than ETHERMTU + sizeof(struct ether_header) 225 * but will actually take in up to 2048 bytes. To guard against the receiver 226 * chaining buffers (which we aren't prepared to handle) we allocate 2kb 227 * size buffers. 228 */ 229 #define MAXPACKETSIZE 2048 /* Should really be ETHERMTU */ 230 /* 231 * Probe the QNA to see if it's there 232 */ 233 qeprobe(reg, ui) 234 caddr_t reg; 235 struct uba_device *ui; 236 { 237 register int br, cvec; /* r11, r10 value-result */ 238 register struct qedevice *addr = (struct qedevice *)reg; 239 register struct qe_ring *rp; 240 register struct qe_ring *prp; /* physical rp */ 241 register int i; 242 register struct qe_softc *sc = &qe_softc[ui->ui_unit]; 243 244 #ifdef lint 245 br = 0; cvec = br; br = cvec; 246 qeintr(0); 247 #endif 248 249 /* 250 * The QNA interrupts on i/o operations. To do an I/O operation 251 * we have to setup the interface by transmitting a setup packet. 252 */ 253 addr->qe_csr = QE_RESET; 254 addr->qe_csr &= ~QE_RESET; 255 addr->qe_vector = (uba_hd[numuba].uh_lastiv -= 4); 256 257 /* 258 * Map the communications area and the setup packet. 259 */ 260 sc->setupaddr = 261 uballoc(0, (caddr_t)sc->setup_pkt, sizeof(sc->setup_pkt), 0); 262 sc->rringaddr = (struct qe_ring *) uballoc(0, (caddr_t)sc->rring, 263 sizeof(struct qe_ring) * (NTOT+2), 0); 264 prp = (struct qe_ring *)UBAI_ADDR((int)sc->rringaddr); 265 266 /* 267 * The QNA will loop the setup packet back to the receive ring 268 * for verification, therefore we initialize the first 269 * receive & transmit ring descriptors and link the setup packet 270 * to them. 271 */ 272 qeinitdesc(sc->tring, (caddr_t)UBAI_ADDR(sc->setupaddr), 273 sizeof(sc->setup_pkt)); 274 qeinitdesc(sc->rring, (caddr_t)UBAI_ADDR(sc->setupaddr), 275 sizeof(sc->setup_pkt)); 276 277 rp = (struct qe_ring *)sc->tring; 278 rp->qe_setup = 1; 279 rp->qe_eomsg = 1; 280 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 281 rp->qe_valid = 1; 282 283 rp = (struct qe_ring *)sc->rring; 284 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 285 rp->qe_valid = 1; 286 287 /* 288 * Get the addr off of the interface and place it into the setup 289 * packet. This code looks strange due to the fact that the address 290 * is placed in the setup packet in col. major order. 291 */ 292 for( i = 0 ; i < 6 ; i++ ) 293 sc->setup_pkt[i][1] = addr->qe_sta_addr[i]; 294 295 qesetup( sc ); 296 /* 297 * Start the interface and wait for the packet. 298 */ 299 (void) spl6(); 300 addr->qe_csr = QE_INT_ENABLE | QE_XMIT_INT | QE_RCV_INT; 301 addr->qe_rcvlist_lo = (short)prp; 302 addr->qe_rcvlist_hi = (short)((int)prp >> 16); 303 prp += NRCV+1; 304 addr->qe_xmtlist_lo = (short)prp; 305 addr->qe_xmtlist_hi = (short)((int)prp >> 16); 306 DELAY(10000); 307 /* 308 * All done with the bus resources. 309 */ 310 ubarelse(0, &sc->setupaddr); 311 ubarelse(0, (int *)&sc->rringaddr); 312 sc->ipl = br = qbgetpri(); 313 return( sizeof(struct qedevice) ); 314 } 315 316 /* 317 * Interface exists: make available by filling in network interface 318 * record. System will initialize the interface when it is ready 319 * to accept packets. 320 */ 321 qeattach(ui) 322 struct uba_device *ui; 323 { 324 register struct qe_softc *sc = &qe_softc[ui->ui_unit]; 325 register struct ifnet *ifp = &sc->qe_if; 326 register struct qedevice *addr = (struct qedevice *)ui->ui_addr; 327 register int i; 328 329 ifp->if_unit = ui->ui_unit; 330 ifp->if_name = "qe"; 331 ifp->if_mtu = ETHERMTU; 332 ifp->if_flags = IFF_BROADCAST; 333 334 /* 335 * Read the address from the prom and save it. 336 */ 337 for( i=0 ; i<6 ; i++ ) 338 sc->setup_pkt[i][1] = sc->qe_addr[i] = addr->qe_sta_addr[i] & 0xff; 339 addr->qe_vector |= 1; 340 printf("qe%d: %s, hardware address %s\n", ui->ui_unit, 341 addr->qe_vector&01 ? "delqa":"deqna", 342 ether_sprintf(sc->qe_addr)); 343 addr->qe_vector &= ~1; 344 345 /* 346 * Save the vector for initialization at reset time. 347 */ 348 sc->qe_intvec = addr->qe_vector; 349 350 ifp->if_init = qeinit; 351 ifp->if_output = ether_output; 352 ifp->if_start = qestart; 353 ifp->if_ioctl = qeioctl; 354 ifp->if_reset = qereset; 355 ifp->if_watchdog = qetimeout; 356 sc->qe_uba.iff_flags = UBA_CANTWAIT; 357 if_attach(ifp); 358 } 359 360 /* 361 * Reset of interface after UNIBUS reset. 362 * If interface is on specified uba, reset its state. 363 */ 364 qereset(unit, uban) 365 int unit, uban; 366 { 367 register struct uba_device *ui; 368 369 if (unit >= NQE || (ui = qeinfo[unit]) == 0 || ui->ui_alive == 0 || 370 ui->ui_ubanum != uban) 371 return; 372 printf(" qe%d", unit); 373 qe_softc[unit].qe_if.if_flags &= ~IFF_RUNNING; 374 qeinit(unit); 375 } 376 377 /* 378 * Initialization of interface. 379 */ 380 qeinit(unit) 381 int unit; 382 { 383 register struct qe_softc *sc = &qe_softc[unit]; 384 register struct uba_device *ui = qeinfo[unit]; 385 register struct qedevice *addr = (struct qedevice *)ui->ui_addr; 386 register struct ifnet *ifp = &sc->qe_if; 387 register i; 388 int s; 389 390 /* address not known */ 391 if (ifp->if_addrlist == (struct ifaddr *)0) 392 return; 393 if (sc->qe_flags & QEF_RUNNING) 394 return; 395 396 if ((ifp->if_flags & IFF_RUNNING) == 0) { 397 /* 398 * map the communications area onto the device 399 */ 400 i = uballoc(0, (caddr_t)sc->rring, 401 sizeof(struct qe_ring) * (NTOT+2), 0); 402 if (i == 0) 403 goto fail; 404 sc->rringaddr = (struct qe_ring *)UBAI_ADDR(i); 405 sc->tringaddr = sc->rringaddr + NRCV + 1; 406 i = uballoc(0, (caddr_t)sc->setup_pkt, 407 sizeof(sc->setup_pkt), 0); 408 if (i == 0) 409 goto fail; 410 sc->setupaddr = UBAI_ADDR(i); 411 /* 412 * init buffers and maps 413 */ 414 if (if_ubaminit(&sc->qe_uba, ui->ui_ubanum, 415 sizeof (struct ether_header), (int)btoc(MAXPACKETSIZE), 416 sc->qe_ifr, NRCV, sc->qe_ifw, NXMT) == 0) { 417 fail: 418 printf("qe%d: can't allocate uba resources\n", unit); 419 sc->qe_if.if_flags &= ~IFF_UP; 420 return; 421 } 422 } 423 /* 424 * Init the buffer descriptors and indexes for each of the lists and 425 * loop them back to form a ring. 426 */ 427 for (i = 0; i < NRCV; i++) { 428 qeinitdesc( &sc->rring[i], 429 (caddr_t)UBAI_ADDR(sc->qe_ifr[i].ifrw_info), MAXPACKETSIZE); 430 sc->rring[i].qe_flag = sc->rring[i].qe_status1 = QE_NOTYET; 431 sc->rring[i].qe_valid = 1; 432 } 433 qeinitdesc(&sc->rring[i], (caddr_t)NULL, 0); 434 435 sc->rring[i].qe_addr_lo = (short)sc->rringaddr; 436 sc->rring[i].qe_addr_hi = (short)((int)sc->rringaddr >> 16); 437 sc->rring[i].qe_chain = 1; 438 sc->rring[i].qe_flag = sc->rring[i].qe_status1 = QE_NOTYET; 439 sc->rring[i].qe_valid = 1; 440 441 for( i = 0 ; i <= NXMT ; i++ ) 442 qeinitdesc(&sc->tring[i], (caddr_t)NULL, 0); 443 i--; 444 445 sc->tring[i].qe_addr_lo = (short)sc->tringaddr; 446 sc->tring[i].qe_addr_hi = (short)((int)sc->tringaddr >> 16); 447 sc->tring[i].qe_chain = 1; 448 sc->tring[i].qe_flag = sc->tring[i].qe_status1 = QE_NOTYET; 449 sc->tring[i].qe_valid = 1; 450 451 sc->nxmit = sc->otindex = sc->tindex = sc->rindex = 0; 452 453 /* 454 * Take the interface out of reset, program the vector, 455 * enable interrupts, and tell the world we are up. 456 */ 457 s = splimp(); 458 addr->qe_vector = sc->qe_intvec; 459 sc->addr = addr; 460 addr->qe_csr = QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT | 461 QE_RCV_INT | QE_ILOOP; 462 addr->qe_rcvlist_lo = (short)sc->rringaddr; 463 addr->qe_rcvlist_hi = (short)((int)sc->rringaddr >> 16); 464 ifp->if_flags |= IFF_UP | IFF_RUNNING; 465 sc->qe_flags |= QEF_RUNNING; 466 qesetup( sc ); 467 (void) qestart( ifp ); 468 sc->qe_if.if_timer = QESLOWTIMEOUT; /* Start watchdog */ 469 splx( s ); 470 } 471 472 /* 473 * Start output on interface. 474 * 475 */ 476 qestart(ifp) 477 struct ifnet *ifp; 478 { 479 int unit = ifp->if_unit; 480 struct uba_device *ui = qeinfo[unit]; 481 register struct qe_softc *sc = &qe_softc[unit]; 482 register struct qedevice *addr; 483 register struct qe_ring *rp; 484 register index; 485 struct mbuf *m; 486 int buf_addr, len, s; 487 488 489 s = splimp(); 490 addr = (struct qedevice *)ui->ui_addr; 491 /* 492 * The deqna doesn't look at anything but the valid bit 493 * to determine if it should transmit this packet. If you have 494 * a ring and fill it the device will loop indefinately on the 495 * packet and continue to flood the net with packets until you 496 * break the ring. For this reason we never queue more than n-1 497 * packets in the transmit ring. 498 * 499 * The microcoders should have obeyed their own defination of the 500 * flag and status words, but instead we have to compensate. 501 */ 502 for( index = sc->tindex; 503 sc->tring[index].qe_valid == 0 && sc->nxmit < (NXMT-1) ; 504 sc->tindex = index = ++index % NXMT){ 505 rp = &sc->tring[index]; 506 if( sc->setupqueued ) { 507 buf_addr = sc->setupaddr; 508 len = 128; 509 rp->qe_setup = 1; 510 sc->setupqueued = 0; 511 } else { 512 IF_DEQUEUE(&sc->qe_if.if_snd, m); 513 if( m == 0 ){ 514 splx(s); 515 return (0); 516 } 517 buf_addr = sc->qe_ifw[index].ifw_info; 518 len = if_ubaput(&sc->qe_uba, &sc->qe_ifw[index], m); 519 } 520 /* 521 * Does buffer end on odd byte ? 522 */ 523 if( len & 1 ) { 524 len++; 525 rp->qe_odd_end = 1; 526 } 527 if( len < MINDATA ) 528 len = MINDATA; 529 rp->qe_buf_len = -(len/2); 530 buf_addr = UBAI_ADDR(buf_addr); 531 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 532 rp->qe_addr_lo = (short)buf_addr; 533 rp->qe_addr_hi = (short)(buf_addr >> 16); 534 rp->qe_eomsg = 1; 535 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 536 rp->qe_valid = 1; 537 if (sc->nxmit++ == 0) { 538 sc->qe_flags |= QEF_FASTTIMEO; 539 sc->qe_if.if_timer = QETIMEOUT; 540 } 541 542 /* 543 * See if the xmit list is invalid. 544 */ 545 if( addr->qe_csr & QE_XL_INVALID ) { 546 buf_addr = (int)(sc->tringaddr+index); 547 addr->qe_xmtlist_lo = (short)buf_addr; 548 addr->qe_xmtlist_hi = (short)(buf_addr >> 16); 549 } 550 } 551 splx( s ); 552 return (0); 553 } 554 555 /* 556 * Ethernet interface interrupt processor 557 */ 558 qeintr(unit) 559 int unit; 560 { 561 register struct qe_softc *sc = &qe_softc[unit]; 562 struct qedevice *addr = (struct qedevice *)qeinfo[unit]->ui_addr; 563 int buf_addr, csr; 564 565 #ifdef notdef 566 splx(sc->ipl); 567 #else 568 (void) splimp(); 569 #endif 570 if (!(sc->qe_flags & QEF_FASTTIMEO)) 571 sc->qe_if.if_timer = QESLOWTIMEOUT; /* Restart timer clock */ 572 csr = addr->qe_csr; 573 addr->qe_csr = QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT | QE_RCV_INT | QE_ILOOP; 574 if( csr & QE_RCV_INT ) 575 qerint( unit ); 576 if( csr & QE_XMIT_INT ) 577 qetint( unit ); 578 if( csr & QE_NEX_MEM_INT ) 579 printf("qe%d: Nonexistent memory interrupt\n", unit); 580 581 if( addr->qe_csr & QE_RL_INVALID && sc->rring[sc->rindex].qe_status1 == QE_NOTYET ) { 582 buf_addr = (int)&sc->rringaddr[sc->rindex]; 583 addr->qe_rcvlist_lo = (short)buf_addr; 584 addr->qe_rcvlist_hi = (short)(buf_addr >> 16); 585 } 586 } 587 588 /* 589 * Ethernet interface transmit interrupt. 590 */ 591 592 qetint(unit) 593 int unit; 594 { 595 register struct qe_softc *sc = &qe_softc[unit]; 596 register struct qe_ring *rp; 597 register struct ifxmt *ifxp; 598 int status1, setupflag; 599 short len; 600 601 602 while( sc->otindex != sc->tindex && sc->tring[sc->otindex].qe_status1 != QE_NOTYET && sc->nxmit > 0 ) { 603 /* 604 * Save the status words from the descriptor so that it can 605 * be released. 606 */ 607 rp = &sc->tring[sc->otindex]; 608 status1 = rp->qe_status1; 609 setupflag = rp->qe_setup; 610 len = (-rp->qe_buf_len) * 2; 611 if( rp->qe_odd_end ) 612 len++; 613 /* 614 * Init the buffer descriptor 615 */ 616 bzero((caddr_t)rp, sizeof(struct qe_ring)); 617 if( --sc->nxmit == 0 ) { 618 sc->qe_flags &= ~QEF_FASTTIMEO; 619 sc->qe_if.if_timer = QESLOWTIMEOUT; 620 } 621 if( !setupflag ) { 622 /* 623 * Do some statistics. 624 */ 625 sc->qe_if.if_opackets++; 626 sc->qe_if.if_collisions += ( status1 & QE_CCNT ) >> 4; 627 if (status1 & QE_ERROR) 628 sc->qe_if.if_oerrors++; 629 /* 630 * If this was a broadcast packet loop it 631 * back because the hardware can't hear its own 632 * transmits. 633 */ 634 ifxp = &sc->qe_ifw[sc->otindex]; 635 if (bcmp((caddr_t)((struct ether_header *)ifxp->ifw_addr)->ether_dhost, 636 (caddr_t)etherbroadcastaddr, 637 sizeof(etherbroadcastaddr)) == 0) 638 qeread(sc, &ifxp->ifrw, 639 len - sizeof(struct ether_header)); 640 if (ifxp->ifw_xtofree) { 641 m_freem(ifxp->ifw_xtofree); 642 ifxp->ifw_xtofree = 0; 643 } 644 } 645 sc->otindex = ++sc->otindex % NXMT; 646 } 647 (void) qestart( &sc->qe_if ); 648 } 649 650 /* 651 * Ethernet interface receiver interrupt. 652 * If can't determine length from type, then have to drop packet. 653 * Othewise decapsulate packet based on type and pass to type specific 654 * higher-level input routine. 655 */ 656 qerint(unit) 657 int unit; 658 { 659 register struct qe_softc *sc = &qe_softc[unit]; 660 register struct qe_ring *rp; 661 int len, status1, status2; 662 int bufaddr; 663 664 /* 665 * Traverse the receive ring looking for packets to pass back. 666 * The search is complete when we find a descriptor not in use. 667 * 668 * As in the transmit case the deqna doesn't honor it's own protocols 669 * so there exists the possibility that the device can beat us around 670 * the ring. The proper way to guard against this is to insure that 671 * there is always at least one invalid descriptor. We chose instead 672 * to make the ring large enough to minimize the problem. With a ring 673 * size of 4 we haven't been able to see the problem. To be safe we 674 * doubled that to 8. 675 * 676 */ 677 for( ; sc->rring[sc->rindex].qe_status1 != QE_NOTYET ; sc->rindex = ++sc->rindex % NRCV ){ 678 rp = &sc->rring[sc->rindex]; 679 status1 = rp->qe_status1; 680 status2 = rp->qe_status2; 681 bzero((caddr_t)rp, sizeof(struct qe_ring)); 682 if( (status1 & QE_MASK) == QE_MASK ) 683 panic("qe: chained packet"); 684 len = ((status1 & QE_RBL_HI) | (status2 & QE_RBL_LO)) + 60; 685 sc->qe_if.if_ipackets++; 686 687 if (status1 & QE_ERROR) { 688 if ((status1 & QE_RUNT) == 0) 689 sc->qe_if.if_ierrors++; 690 } else { 691 /* 692 * We don't process setup packets. 693 */ 694 if( !(status1 & QE_ESETUP) ) 695 qeread(sc, &sc->qe_ifr[sc->rindex], 696 len - sizeof(struct ether_header)); 697 } 698 /* 699 * Return the buffer to the ring 700 */ 701 bufaddr = (int)UBAI_ADDR(sc->qe_ifr[sc->rindex].ifrw_info); 702 rp->qe_buf_len = -((MAXPACKETSIZE)/2); 703 rp->qe_addr_lo = (short)bufaddr; 704 rp->qe_addr_hi = (short)((int)bufaddr >> 16); 705 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 706 rp->qe_valid = 1; 707 } 708 } 709 710 /* 711 * Process an ioctl request. 712 */ 713 qeioctl(ifp, cmd, data) 714 register struct ifnet *ifp; 715 int cmd; 716 caddr_t data; 717 { 718 struct qe_softc *sc = &qe_softc[ifp->if_unit]; 719 struct ifaddr *ifa = (struct ifaddr *)data; 720 int s = splimp(), error = 0; 721 722 switch (cmd) { 723 724 case SIOCSIFADDR: 725 ifp->if_flags |= IFF_UP; 726 qeinit(ifp->if_unit); 727 switch(ifa->ifa_addr->sa_family) { 728 #ifdef INET 729 case AF_INET: 730 ((struct arpcom *)ifp)->ac_ipaddr = 731 IA_SIN(ifa)->sin_addr; 732 arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr); 733 break; 734 #endif 735 #ifdef NS 736 case AF_NS: 737 { 738 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr); 739 740 if (ns_nullhost(*ina)) 741 ina->x_host = *(union ns_host *)(sc->qe_addr); 742 else 743 qe_setaddr(ina->x_host.c_host, ifp->if_unit); 744 break; 745 } 746 #endif 747 } 748 break; 749 750 case SIOCSIFFLAGS: 751 if ((ifp->if_flags & IFF_UP) == 0 && 752 sc->qe_flags & QEF_RUNNING) { 753 ((struct qedevice *) 754 (qeinfo[ifp->if_unit]->ui_addr))->qe_csr = QE_RESET; 755 sc->qe_flags &= ~QEF_RUNNING; 756 } else if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == 757 IFF_RUNNING && (sc->qe_flags & QEF_RUNNING) == 0) 758 qerestart(sc); 759 break; 760 761 default: 762 error = EINVAL; 763 764 } 765 splx(s); 766 return (error); 767 } 768 769 /* 770 * set ethernet address for unit 771 */ 772 qe_setaddr(physaddr, unit) 773 u_char *physaddr; 774 int unit; 775 { 776 register struct qe_softc *sc = &qe_softc[unit]; 777 register int i; 778 779 for (i = 0; i < 6; i++) 780 sc->setup_pkt[i][1] = sc->qe_addr[i] = physaddr[i]; 781 sc->qe_flags |= QEF_SETADDR; 782 if (sc->qe_if.if_flags & IFF_RUNNING) 783 qesetup(sc); 784 qeinit(unit); 785 } 786 787 788 /* 789 * Initialize a ring descriptor with mbuf allocation side effects 790 */ 791 qeinitdesc(rp, addr, len) 792 register struct qe_ring *rp; 793 caddr_t addr; /* mapped address */ 794 int len; 795 { 796 /* 797 * clear the entire descriptor 798 */ 799 bzero((caddr_t)rp, sizeof(struct qe_ring)); 800 801 if( len ) { 802 rp->qe_buf_len = -(len/2); 803 rp->qe_addr_lo = (short)addr; 804 rp->qe_addr_hi = (short)((int)addr >> 16); 805 } 806 } 807 /* 808 * Build a setup packet - the physical address will already be present 809 * in first column. 810 */ 811 qesetup( sc ) 812 struct qe_softc *sc; 813 { 814 register i, j; 815 816 /* 817 * Copy the target address to the rest of the entries in this row. 818 */ 819 for ( j = 0; j < 6 ; j++ ) 820 for ( i = 2 ; i < 8 ; i++ ) 821 sc->setup_pkt[j][i] = sc->setup_pkt[j][1]; 822 /* 823 * Duplicate the first half. 824 */ 825 bcopy((caddr_t)sc->setup_pkt[0], (caddr_t)sc->setup_pkt[8], 64); 826 /* 827 * Fill in the broadcast (and ISO multicast) address(es). 828 */ 829 for ( i = 0; i < 6 ; i++ ) { 830 sc->setup_pkt[i][2] = 0xff; 831 #ifdef ISO 832 sc->setup_pkt[i][3] = all_es_snpa[i]; 833 sc->setup_pkt[i][4] = all_is_snpa[i]; 834 #endif 835 } 836 sc->setupqueued++; 837 } 838 839 /* 840 * Pass a packet to the higher levels. 841 * We deal with the trailer protocol here. 842 */ 843 qeread(sc, ifrw, len) 844 register struct qe_softc *sc; 845 struct ifrw *ifrw; 846 int len; 847 { 848 struct ether_header *eh; 849 struct mbuf *m; 850 int off, resid, s; 851 struct ifqueue *inq; 852 853 /* 854 * Deal with trailer protocol: if type is INET trailer 855 * get true type from first 16-bit word past data. 856 * Remember that type was trailer by setting off. 857 */ 858 859 eh = (struct ether_header *)ifrw->ifrw_addr; 860 eh->ether_type = ntohs((u_short)eh->ether_type); 861 #define qedataaddr(eh, off, type) ((type)(((caddr_t)((eh)+1)+(off)))) 862 if (eh->ether_type >= ETHERTYPE_TRAIL && 863 eh->ether_type < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) { 864 off = (eh->ether_type - ETHERTYPE_TRAIL) * 512; 865 if (off >= ETHERMTU) 866 return; /* sanity */ 867 eh->ether_type = ntohs(*qedataaddr(eh,off, u_short *)); 868 resid = ntohs(*(qedataaddr(eh, off+2, u_short *))); 869 if (off + resid > len) 870 return; /* sanity */ 871 len = off + resid; 872 } else 873 off = 0; 874 if (len == 0) 875 return; 876 877 /* 878 * Pull packet off interface. Off is nonzero if packet 879 * has trailing header; qeget will then force this header 880 * information to be at the front, but we still have to drop 881 * the type and length which are at the front of any trailer data. 882 */ 883 m = if_ubaget(&sc->qe_uba, ifrw, len, off, &sc->qe_if); 884 885 if (m) 886 ether_input(&sc->qe_if, eh, m); 887 } 888 889 /* 890 * Watchdog timeout routine. There is a condition in the hardware that 891 * causes the board to lock up under heavy load. This routine detects 892 * the hang up and restarts the device. 893 */ 894 qetimeout(unit) 895 int unit; 896 { 897 register struct qe_softc *sc; 898 899 sc = &qe_softc[unit]; 900 #ifdef notdef 901 log(LOG_ERR, "qe%d: transmit timeout, restarted %d\n", 902 unit, sc->qe_restarts++); 903 #endif 904 qerestart(sc); 905 } 906 /* 907 * Restart for board lockup problem. 908 */ 909 qerestart(sc) 910 register struct qe_softc *sc; 911 { 912 register struct ifnet *ifp = &sc->qe_if; 913 register struct qedevice *addr = sc->addr; 914 register struct qe_ring *rp; 915 register i; 916 917 addr->qe_csr = QE_RESET; 918 addr->qe_csr &= ~QE_RESET; 919 qesetup( sc ); 920 for (i = 0, rp = sc->tring; i < NXMT; rp++, i++) { 921 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 922 rp->qe_valid = 0; 923 } 924 sc->nxmit = sc->otindex = sc->tindex = sc->rindex = 0; 925 addr->qe_csr = QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT | 926 QE_RCV_INT | QE_ILOOP; 927 addr->qe_rcvlist_lo = (short)sc->rringaddr; 928 addr->qe_rcvlist_hi = (short)((int)sc->rringaddr >> 16); 929 sc->qe_flags |= QEF_RUNNING; 930 (void) qestart(ifp); 931 } 932 #endif 933