1 /* 2 * Copyright (c) 1988 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Digital Equipment Corp. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)if_qereg.h 7.3 (Berkeley) 06/28/90 11 */ 12 13 /* @(#)if_qereg.h 1.2 (ULTRIX) 1/3/85 */ 14 15 /**************************************************************** 16 * * 17 * Licensed from Digital Equipment Corporation * 18 * Copyright (c) * 19 * Digital Equipment Corporation * 20 * Maynard, Massachusetts * 21 * 1985, 1986 * 22 * All rights reserved. * 23 * * 24 * The Information in this software is subject to change * 25 * without notice and should not be construed as a commitment * 26 * by Digital Equipment Corporation. Digital makes no * 27 * representations about the suitability of this software for * 28 * any purpose. It is supplied "As Is" without expressed or * 29 * implied warranty. * 30 * * 31 * If the Regents of the University of California or its * 32 * licensees modify the software in a manner creating * 33 * diriviative copyright rights, appropriate copyright * 34 * legends may be placed on the drivative work in addition * 35 * to that set forth above. * 36 * * 37 ****************************************************************/ 38 /* --------------------------------------------------------------------- 39 * Modification History 40 * 41 * 13 Feb. 84 -- rjl 42 * 43 * Initial version of driver. derived from IL driver. 44 * 45 * --------------------------------------------------------------------- 46 */ 47 48 /* 49 * Digital Q-BUS to NI Adapter 50 */ 51 struct qedevice { 52 u_short qe_sta_addr[2]; /* Station address (actually 6 */ 53 u_short qe_rcvlist_lo; /* Receive list lo address */ 54 u_short qe_rcvlist_hi; /* Receive list hi address */ 55 u_short qe_xmtlist_lo; /* Transmit list lo address */ 56 u_short qe_xmtlist_hi; /* Transmit list hi address */ 57 u_short qe_vector; /* Interrupt vector */ 58 u_short qe_csr; /* Command and Status Register */ 59 }; 60 61 /* 62 * Command and status bits (csr) 63 */ 64 #define QE_RCV_ENABLE 0x0001 /* Receiver enable */ 65 #define QE_RESET 0x0002 /* Software reset */ 66 #define QE_NEX_MEM_INT 0x0004 /* Non existant mem interrupt */ 67 #define QE_LOAD_ROM 0x0008 /* Load boot/diag from rom */ 68 #define QE_XL_INVALID 0x0010 /* Transmit list invalid */ 69 #define QE_RL_INVALID 0x0020 /* Receive list invalid */ 70 #define QE_INT_ENABLE 0x0040 /* Interrupt enable */ 71 #define QE_XMIT_INT 0x0080 /* Transmit interrupt */ 72 #define QE_ILOOP 0x0100 /* Internal loopback */ 73 #define QE_ELOOP 0x0200 /* External loopback */ 74 #define QE_STIM_ENABLE 0x0400 /* Sanity timer enable */ 75 #define QE_POWERUP 0x1000 /* Tranceiver power on */ 76 #define QE_CARRIER 0x2000 /* Carrier detect */ 77 #define QE_RCV_INT 0x8000 /* Receiver interrupt */ 78 79 /* 80 * Transmit and receive ring discriptor --------------------------- 81 * 82 * The QNA uses the flag, status1 and the valid bit as a handshake/semiphore 83 * mechinism. 84 * 85 * The flag word is written on ( bits 15,15 set to 1 ) when it reads the 86 * descriptor. If the valid bit is set it considers the address to be valid. 87 * When it uses the buffer pointed to by the valid address it sets status word 88 * one. 89 */ 90 struct qe_ring { 91 u_short qe_flag; /* Buffer utilization flags */ 92 u_short qe_addr_hi:6, /* Hi order bits of buffer addr */ 93 qe_odd_begin:1, /* Odd byte begin and end (xmit)*/ 94 qe_odd_end:1, 95 qe_fill1:4, 96 qe_setup:1, /* Setup packet */ 97 qe_eomsg:1, /* End of message flag */ 98 qe_chain:1, /* Chain address instead of buf */ 99 qe_valid:1; /* Address field is valid */ 100 u_short qe_addr_lo; /* Low order bits of address */ 101 short qe_buf_len; /* Negative buffer length */ 102 u_short qe_status1; /* Status word one */ 103 u_short qe_status2; /* Status word two */ 104 }; 105 106 /* 107 * Status word definations (receive) 108 * word1 109 */ 110 #define QE_OVF 0x0001 /* Receiver overflow */ 111 #define QE_CRCERR 0x0002 /* CRC error */ 112 #define QE_FRAME 0x0004 /* Framing alignment error */ 113 #define QE_SHORT 0x0008 /* Packet size < 10 bytes */ 114 #define QE_RBL_HI 0x0700 /* Hi bits of receive len */ 115 #define QE_RUNT 0x0800 /* Runt packet */ 116 #define QE_DISCARD 0x1000 /* Discard the packet */ 117 #define QE_ESETUP 0x2000 /* Looped back setup or eloop */ 118 #define QE_ERROR 0x4000 /* Receiver error */ 119 #define QE_LASTNOT 0x8000 /* Not the last in the packet */ 120 /* word2 */ 121 #define QE_RBL_LO 0x00ff /* Low bits of receive len */ 122 123 /* 124 * Status word definations (transmit) 125 * word1 126 */ 127 #define QE_CCNT 0x00f0 /* Collision count this packet */ 128 #define QE_FAIL 0x0100 /* Heart beat check failure */ 129 #define QE_ABORT 0x0200 /* Transmission abort */ 130 #define QE_STE16 0x0400 /* Sanity timer default on */ 131 #define QE_NOCAR 0x0800 /* No carrier */ 132 #define QE_LOSS 0x1000 /* Loss of carrier while xmit */ 133 /* word2 */ 134 #define QE_TDR 0x3fff /* Time domain reflectometry */ 135 136 /* 137 * General constant definations 138 */ 139 #define QEALLOC 0 /* Allocate an mbuf */ 140 #define QENOALLOC 1 /* No mbuf allocation */ 141 #define QEDEALLOC 2 /* Release an mbuf chain */ 142 143 #define QE_NOTYET 0x8000 /* Descriptor not in use yet */ 144 #define QE_INUSE 0x4000 /* Descriptor being used by QNA */ 145 #define QE_MASK 0xc000 /* Lastnot/error/used mask */ 146