1 /* dh.c 4.34 81/05/18 */ 2 3 #include "dh.h" 4 #if NDH > 0 5 /* 6 * DH-11/DM-11 driver 7 */ 8 #include "bk.h" 9 #include "../h/param.h" 10 #include "../h/conf.h" 11 #include "../h/dir.h" 12 #include "../h/user.h" 13 #include "../h/tty.h" 14 #include "../h/map.h" 15 #include "../h/pte.h" 16 #include "../h/buf.h" 17 #include "../h/vm.h" 18 #include "../h/ubareg.h" 19 #include "../h/ubavar.h" 20 #include "../h/bk.h" 21 #include "../h/clist.h" 22 #include "../h/mx.h" 23 #include "../h/file.h" 24 25 /* 26 * Definition of the driver for the auto-configuration program. 27 * There is one definition for the dh and one for the dm. 28 */ 29 int dhprobe(), dhattach(), dhrint(), dhxint(); 30 struct uba_device *dhinfo[NDH]; 31 u_short dhstd[] = { 0 }; 32 struct uba_driver dhdriver = 33 { dhprobe, 0, dhattach, 0, dhstd, "dh", dhinfo }; 34 35 int dmprobe(), dmattach(), dmintr(); 36 struct uba_device *dminfo[NDH]; 37 u_short dmstd[] = { 0 }; 38 struct uba_driver dmdriver = 39 { dmprobe, 0, dmattach, 0, dmstd, "dm", dminfo }; 40 41 struct dhdevice 42 { 43 union { 44 short dhcsr; /* control-status register */ 45 char dhcsrl; /* low byte for line select */ 46 } un; 47 short dhrcr; /* receive character register */ 48 short dhlpr; /* line parameter register */ 49 u_short dhcar; /* current address register */ 50 short dhbcr; /* byte count register */ 51 u_short dhbar; /* buffer active register */ 52 short dhbreak; /* break control register */ 53 short dhsilo; /* silo status register */ 54 }; 55 56 /* Bits in dhcsr */ 57 #define DH_TI 0100000 /* transmit interrupt */ 58 #define DH_SI 0040000 /* storage interrupt */ 59 #define DH_TIE 0020000 /* transmit interrupt enable */ 60 #define DH_SIE 0010000 /* storage interrupt enable */ 61 #define DH_MC 0004000 /* master clear */ 62 #define DH_NXM 0002000 /* non-existant memory */ 63 #define DH_MM 0001000 /* maintenance mode */ 64 #define DH_CNI 0000400 /* clear non-existant memory interrupt */ 65 #define DH_RI 0000200 /* receiver interrupt */ 66 #define DH_RIE 0000100 /* receiver interrupt enable */ 67 68 /* Bits in dhlpr */ 69 #define BITS6 01 70 #define BITS7 02 71 #define BITS8 03 72 #define TWOSB 04 73 #define PENABLE 020 74 /* DEC manuals incorrectly say this bit causes generation of even parity. */ 75 #define OPAR 040 76 #define HDUPLX 040000 77 78 #if NBK == 0 79 #define DH_IE (DH_TIE|DH_RIE) 80 #else 81 #define DH_IE (DH_TIE|DH_SIE|DH_RIE) 82 #endif 83 84 /* Bits in dhrcr */ 85 #define DH_PE 0010000 /* parity error */ 86 #define DH_FE 0020000 /* framing error */ 87 #define DH_DO 0040000 /* data overrun */ 88 89 struct dmdevice 90 { 91 short dmcsr; /* control status register */ 92 short dmlstat; /* line status register */ 93 short dmpad1[2]; 94 }; 95 96 /* bits in dm csr */ 97 #define DM_RF 0100000 /* ring flag */ 98 #define DM_CF 0040000 /* carrier flag */ 99 #define DM_CTS 0020000 /* clear to send */ 100 #define DM_SRF 0010000 /* secondary receive flag */ 101 #define DM_CS 0004000 /* clear scan */ 102 #define DM_CM 0002000 /* clear multiplexor */ 103 #define DM_MM 0001000 /* maintenance mode */ 104 #define DM_STP 0000400 /* step */ 105 #define DM_DONE 0000200 /* scanner is done */ 106 #define DM_IE 0000100 /* interrupt enable */ 107 #define DM_SE 0000040 /* scan enable */ 108 #define DM_BUSY 0000020 /* scan busy */ 109 110 /* bits in dm lsr */ 111 #define DML_RNG 0000200 /* ring */ 112 #define DML_CAR 0000100 /* carrier detect */ 113 #define DML_CTS 0000040 /* clear to send */ 114 #define DML_SR 0000020 /* secondary receive */ 115 #define DML_ST 0000010 /* secondary transmit */ 116 #define DML_RTS 0000004 /* request to send */ 117 #define DML_DTR 0000002 /* data terminal ready */ 118 #define DML_LE 0000001 /* line enable */ 119 120 #define DML_ON (DML_DTR|DML_RTS|DML_LE) 121 #define DML_OFF (DML_LE) 122 123 /* 124 * Local variables for the driver 125 */ 126 short dhsar[NDH]; /* software copy of last bar */ 127 short dhsoftCAR[NDH]; 128 129 struct tty dh11[NDH*16]; 130 int ndh11 = NDH*16; 131 int dhact; /* mask of active dh's */ 132 int dhstart(), ttrstrt(); 133 134 /* 135 * The clist space is mapped by the driver onto each UNIBUS. 136 * The UBACVT macro converts a clist space address for unibus uban 137 * into an i/o space address for the DMA routine. 138 */ 139 int dh_ubinfo[MAXNUBA]; /* info about allocated unibus map */ 140 int cbase[MAXNUBA]; /* base address in unibus map */ 141 #define UBACVT(x, uban) (cbase[uban] + ((x)-(char *)cfree)) 142 143 /* 144 * Routine for configuration to force a dh to interrupt. 145 * Set to transmit at 9600 baud, and cause a transmitter interrupt. 146 */ 147 /*ARGSUSED*/ 148 dhprobe(reg) 149 caddr_t reg; 150 { 151 register int br, cvec; /* these are ``value-result'' */ 152 register struct dhdevice *dhaddr = (struct dhdevice *)reg; 153 154 #ifdef lint 155 br = 0; cvec = br; br = cvec; 156 #endif 157 #ifndef notdef 158 dhaddr->un.dhcsr = DH_RIE|DH_MM|DH_RI; 159 DELAY(25); 160 dhaddr->un.dhcsr = 0; 161 #else 162 dhaddr->un.dhcsr = DH_TIE; 163 DELAY(5); 164 dhaddr->dhlpr = (B9600 << 10) | (B9600 << 6) | BITS7|PENABLE; 165 dhaddr->dhbcr = -1; 166 dhaddr->dhcar = 0; 167 dhaddr->dhbar = 1; 168 DELAY(100000); /* wait 1/10'th of a sec for interrupt */ 169 dhaddr->un.dhcsr = 0; 170 if (cvec && cvec != 0x200) 171 cvec -= 4; /* transmit -> receive */ 172 #endif 173 return (1); 174 } 175 176 /* 177 * Routine called to attach a dh. 178 */ 179 dhattach(ui) 180 struct uba_device *ui; 181 { 182 183 dhsoftCAR[ui->ui_unit] = ui->ui_flags; 184 } 185 186 /* 187 * Configuration routine to cause a dm to interrupt. 188 */ 189 dmprobe(reg) 190 caddr_t reg; 191 { 192 register int br, vec; /* value-result */ 193 register struct dmdevice *dmaddr = (struct dmdevice *)reg; 194 195 #ifdef lint 196 br = 0; vec = br; br = vec; 197 #endif 198 dmaddr->dmcsr = DM_DONE|DM_IE; 199 DELAY(20); 200 dmaddr->dmcsr = 0; 201 return (1); 202 } 203 204 /*ARGSUSED*/ 205 dmattach(ui) 206 struct uba_device *ui; 207 { 208 209 /* no local state to set up */ 210 } 211 212 /* 213 * Open a DH11 line, mapping the clist onto the uba if this 214 * is the first dh on this uba. Turn on this dh if this is 215 * the first use of it. Also do a dmopen to wait for carrier. 216 */ 217 /*ARGSUSED*/ 218 dhopen(dev, flag) 219 dev_t dev; 220 { 221 register struct tty *tp; 222 register int unit, dh; 223 register struct dhdevice *addr; 224 register struct uba_device *ui; 225 int s; 226 227 unit = minor(dev); 228 dh = unit >> 4; 229 if (unit >= NDH*16 || (ui = dhinfo[dh])== 0 || ui->ui_alive == 0) { 230 u.u_error = ENXIO; 231 return; 232 } 233 tp = &dh11[unit]; 234 if (tp->t_state&XCLUDE && u.u_uid!=0) { 235 u.u_error = EBUSY; 236 return; 237 } 238 addr = (struct dhdevice *)ui->ui_addr; 239 tp->t_addr = (caddr_t)addr; 240 tp->t_oproc = dhstart; 241 tp->t_iproc = NULL; 242 tp->t_state |= WOPEN; 243 /* 244 * While setting up state for this uba and this dh, 245 * block uba resets which can clear the state. 246 */ 247 s = spl5(); 248 if (dh_ubinfo[ui->ui_ubanum] == 0) { 249 /* 512+ is a kludge to try to get around a hardware problem */ 250 dh_ubinfo[ui->ui_ubanum] = 251 uballoc(ui->ui_ubanum, (caddr_t)cfree, 252 512+nclist*sizeof(struct cblock), 0); 253 cbase[ui->ui_ubanum] = dh_ubinfo[ui->ui_ubanum]&0x3ffff; 254 } 255 if ((dhact&(1<<dh)) == 0) { 256 addr->un.dhcsr |= DH_IE; 257 dhact |= (1<<dh); 258 addr->dhsilo = 16; 259 } 260 splx(s); 261 /* 262 * If this is first open, initialze tty state to default. 263 */ 264 if ((tp->t_state&ISOPEN) == 0) { 265 ttychars(tp); 266 if (tp->t_ispeed == 0) { 267 tp->t_ispeed = B300; 268 tp->t_ospeed = B300; 269 tp->t_flags = ODDP|EVENP|ECHO; 270 } 271 dhparam(unit); 272 } 273 /* 274 * Wait for carrier, then process line discipline specific open. 275 */ 276 dmopen(dev); 277 (*linesw[tp->t_line].l_open)(dev, tp); 278 } 279 280 /* 281 * Close a DH11 line, turning off the DM11. 282 */ 283 /*ARGSUSED*/ 284 dhclose(dev, flag) 285 dev_t dev; 286 int flag; 287 { 288 register struct tty *tp; 289 register unit; 290 291 unit = minor(dev); 292 tp = &dh11[unit]; 293 (*linesw[tp->t_line].l_close)(tp); 294 ((struct dhdevice *)(tp->t_addr))->dhbreak &= ~(1<<(unit&017)); 295 if (tp->t_state&HUPCLS || (tp->t_state&ISOPEN)==0) 296 dmctl(unit, DML_OFF, DMSET); 297 ttyclose(tp); 298 } 299 300 dhread(dev) 301 dev_t dev; 302 { 303 register struct tty *tp; 304 305 tp = &dh11[minor(dev)]; 306 (*linesw[tp->t_line].l_read)(tp); 307 } 308 309 dhwrite(dev) 310 dev_t dev; 311 { 312 register struct tty *tp; 313 314 tp = &dh11[minor(dev)]; 315 (*linesw[tp->t_line].l_write)(tp); 316 } 317 318 /* 319 * DH11 receiver interrupt. 320 */ 321 dhrint(dh) 322 int dh; 323 { 324 register struct tty *tp; 325 register c; 326 register struct dhdevice *addr; 327 register struct tty *tp0; 328 register struct uba_device *ui; 329 int overrun = 0; 330 331 ui = dhinfo[dh]; 332 if (ui == 0 || ui->ui_alive == 0) 333 return; 334 addr = (struct dhdevice *)ui->ui_addr; 335 tp0 = &dh11[dh<<4]; 336 /* 337 * Loop fetching characters from the silo for this 338 * dh until there are no more in the silo. 339 */ 340 while ((c = addr->dhrcr) < 0) { 341 tp = tp0 + ((c>>8)&0xf); 342 if ((tp->t_state&ISOPEN)==0) { 343 wakeup((caddr_t)tp); 344 continue; 345 } 346 if (c & DH_PE) 347 if ((tp->t_flags&(EVENP|ODDP))==EVENP 348 || (tp->t_flags&(EVENP|ODDP))==ODDP ) 349 continue; 350 if ((c & DH_DO) && overrun == 0) { 351 printf("dh%d: silo overflow\n", dh); 352 overrun = 1; 353 } 354 if (c & DH_FE) 355 /* 356 * At framing error (break) generate 357 * a null (in raw mode, for getty), or a 358 * interrupt (in cooked/cbreak mode). 359 */ 360 if (tp->t_flags&RAW) 361 c = 0; 362 else 363 c = tun.t_intrc; 364 #if NBK > 0 365 if (tp->t_line == NETLDISC) { 366 c &= 0177; 367 BKINPUT(c, tp); 368 } else 369 #endif 370 (*linesw[tp->t_line].l_rint)(c, tp); 371 } 372 } 373 374 /* 375 * Ioctl for DH11. 376 */ 377 /*ARGSUSED*/ 378 dhioctl(dev, cmd, addr, flag) 379 caddr_t addr; 380 { 381 register struct tty *tp; 382 register unit = minor(dev); 383 384 tp = &dh11[unit]; 385 cmd = (*linesw[tp->t_line].l_ioctl)(tp, cmd, addr); 386 if (cmd == 0) 387 return; 388 if (ttioctl(tp, cmd, addr, flag)) { 389 if (cmd==TIOCSETP || cmd==TIOCSETN) 390 dhparam(unit); 391 } else switch(cmd) { 392 case TIOCSBRK: 393 ((struct dhdevice *)(tp->t_addr))->dhbreak |= 1<<(unit&017); 394 break; 395 case TIOCCBRK: 396 ((struct dhdevice *)(tp->t_addr))->dhbreak &= ~(1<<(unit&017)); 397 break; 398 case TIOCSDTR: 399 dmctl(unit, DML_DTR|DML_RTS, DMBIS); 400 break; 401 case TIOCCDTR: 402 dmctl(unit, DML_DTR|DML_RTS, DMBIC); 403 break; 404 default: 405 u.u_error = ENOTTY; 406 } 407 } 408 409 /* 410 * Set parameters from open or stty into the DH hardware 411 * registers. 412 */ 413 dhparam(unit) 414 register int unit; 415 { 416 register struct tty *tp; 417 register struct dhdevice *addr; 418 register int lpar; 419 int s; 420 421 tp = &dh11[unit]; 422 addr = (struct dhdevice *)tp->t_addr; 423 /* 424 * Block interrupts so parameters will be set 425 * before the line interrupts. 426 */ 427 s = spl5(); 428 addr->un.dhcsrl = (unit&0xf) | DH_IE; 429 if ((tp->t_ispeed)==0) { 430 tp->t_state |= HUPCLS; 431 dmctl(unit, DML_OFF, DMSET); 432 return; 433 } 434 lpar = ((tp->t_ospeed)<<10) | ((tp->t_ispeed)<<6); 435 if ((tp->t_ispeed) == B134) 436 lpar |= BITS6|PENABLE|HDUPLX; 437 else if ((tp->t_flags&RAW) || (tp->t_local&LLITOUT)) 438 lpar |= BITS8; 439 else 440 lpar |= BITS7|PENABLE; 441 if ((tp->t_flags&EVENP) == 0) 442 lpar |= OPAR; 443 if ((tp->t_ospeed) == B110) 444 lpar |= TWOSB; 445 addr->dhlpr = lpar; 446 splx(s); 447 } 448 449 /* 450 * DH11 transmitter interrupt. 451 * Restart each line which used to be active but has 452 * terminated transmission since the last interrupt. 453 */ 454 dhxint(dh) 455 int dh; 456 { 457 register struct tty *tp; 458 register struct dhdevice *addr; 459 short ttybit, bar, *sbar; 460 register struct uba_device *ui; 461 register int unit; 462 u_short cntr; 463 464 ui = dhinfo[dh]; 465 addr = (struct dhdevice *)ui->ui_addr; 466 if (addr->un.dhcsr & DH_NXM) { 467 addr->un.dhcsr |= DH_CNI; 468 printf("dh%d: NXM\n", dh); 469 } 470 sbar = &dhsar[dh]; 471 bar = *sbar & ~addr->dhbar; 472 unit = dh * 16; ttybit = 1; 473 addr->un.dhcsr &= (short)~DH_TI; 474 for (; bar; unit++, ttybit <<= 1) { 475 if (bar & ttybit) { 476 *sbar &= ~ttybit; 477 bar &= ~ttybit; 478 tp = &dh11[unit]; 479 tp->t_state &= ~BUSY; 480 if (tp->t_state&FLUSH) 481 tp->t_state &= ~FLUSH; 482 else { 483 addr->un.dhcsrl = (unit&017)|DH_IE; 484 /* 485 * Do arithmetic in a short to make up 486 * for lost 16&17 bits. 487 */ 488 cntr = addr->dhcar - 489 UBACVT(tp->t_outq.c_cf, ui->ui_ubanum); 490 ndflush(&tp->t_outq, (int)cntr); 491 } 492 if (tp->t_line) 493 (*linesw[tp->t_line].l_start)(tp); 494 else 495 dhstart(tp); 496 } 497 } 498 } 499 500 /* 501 * Start (restart) transmission on the given DH11 line. 502 */ 503 dhstart(tp) 504 register struct tty *tp; 505 { 506 register struct dhdevice *addr; 507 register int car, dh, unit, nch; 508 int s; 509 510 unit = minor(tp->t_dev); 511 dh = unit >> 4; 512 unit &= 0xf; 513 addr = (struct dhdevice *)tp->t_addr; 514 515 /* 516 * Must hold interrupts in following code to prevent 517 * state of the tp from changing. 518 */ 519 s = spl5(); 520 /* 521 * If it's currently active, or delaying, no need to do anything. 522 */ 523 if (tp->t_state&(TIMEOUT|BUSY|TTSTOP)) 524 goto out; 525 /* 526 * If there are sleepers, and output has drained below low 527 * water mark, wake up the sleepers. 528 */ 529 if ((tp->t_state&ASLEEP) && tp->t_outq.c_cc<=TTLOWAT(tp)) { 530 tp->t_state &= ~ASLEEP; 531 if (tp->t_chan) 532 mcstart(tp->t_chan, (caddr_t)&tp->t_outq); 533 else 534 wakeup((caddr_t)&tp->t_outq); 535 } 536 /* 537 * Now restart transmission unless the output queue is 538 * empty. 539 */ 540 if (tp->t_outq.c_cc == 0) 541 goto out; 542 if (tp->t_flags&RAW || tp->t_local&LLITOUT) 543 nch = ndqb(&tp->t_outq, 0); 544 else { 545 nch = ndqb(&tp->t_outq, 0200); 546 /* 547 * If first thing on queue is a delay process it. 548 */ 549 if (nch == 0) { 550 nch = getc(&tp->t_outq); 551 timeout(ttrstrt, (caddr_t)tp, (nch&0x7f)+6); 552 tp->t_state |= TIMEOUT; 553 goto out; 554 } 555 } 556 /* 557 * If characters to transmit, restart transmission. 558 */ 559 if (nch) { 560 car = UBACVT(tp->t_outq.c_cf, dhinfo[dh]->ui_ubanum); 561 addr->un.dhcsrl = unit|((car>>12)&0x30)|DH_IE; 562 /* 563 * The following nonsense with short word 564 * is to make sure the dhbar |= word below 565 * is done with an interlocking bisw2 instruction. 566 */ 567 { short word = 1 << unit; 568 dhsar[dh] |= word; 569 addr->dhcar = car; 570 addr->dhbcr = -nch; 571 addr->dhbar |= word; 572 } 573 tp->t_state |= BUSY; 574 } 575 out: 576 splx(s); 577 } 578 579 /* 580 * Stop output on a line, e.g. for ^S/^Q or output flush. 581 */ 582 /*ARGSUSED*/ 583 dhstop(tp, flag) 584 register struct tty *tp; 585 { 586 register struct dhdevice *addr; 587 register int unit, s; 588 589 addr = (struct dhdevice *)tp->t_addr; 590 /* 591 * Block input/output interrupts while messing with state. 592 */ 593 s = spl5(); 594 if (tp->t_state & BUSY) { 595 /* 596 * Device is transmitting; stop output 597 * by selecting the line and setting the byte 598 * count to -1. We will clean up later 599 * by examining the address where the dh stopped. 600 */ 601 unit = minor(tp->t_dev); 602 addr->un.dhcsrl = (unit&017) | DH_IE; 603 if ((tp->t_state&TTSTOP)==0) 604 tp->t_state |= FLUSH; 605 addr->dhbcr = -1; 606 } 607 splx(s); 608 } 609 610 /* 611 * Reset state of driver if UBA reset was necessary. 612 * Reset the csrl and lpr registers on open lines, and 613 * restart transmitters. 614 */ 615 dhreset(uban) 616 int uban; 617 { 618 register int dh, unit; 619 register struct tty *tp; 620 register struct uba_device *ui; 621 int i; 622 623 if (dh_ubinfo[uban] == 0) 624 return; 625 ubarelse(uban, &dh_ubinfo[uban]); 626 dh_ubinfo[uban] = uballoc(uban, (caddr_t)cfree, 627 512+nclist*sizeof (struct cblock), 0); 628 cbase[uban] = dh_ubinfo[uban]&0x3ffff; 629 dh = 0; 630 for (dh = 0; dh < NDH; dh++) { 631 ui = dhinfo[dh]; 632 if (ui == 0 || ui->ui_alive == 0 || ui->ui_ubanum != uban) 633 continue; 634 printf(" dh%d", dh); 635 ((struct dhdevice *)ui->ui_addr)->un.dhcsr |= DH_IE; 636 ((struct dhdevice *)ui->ui_addr)->dhsilo = 16; 637 unit = dh * 16; 638 for (i = 0; i < 16; i++) { 639 tp = &dh11[unit]; 640 if (tp->t_state & (ISOPEN|WOPEN)) { 641 dhparam(unit); 642 dmctl(unit, DML_ON, DMSET); 643 tp->t_state &= ~BUSY; 644 dhstart(tp); 645 } 646 unit++; 647 } 648 } 649 dhtimer(); 650 } 651 652 /* 653 * At software clock interrupt time or after a UNIBUS reset 654 * empty all the dh silos. 655 */ 656 dhtimer() 657 { 658 register int dh; 659 660 for (dh = 0; dh < NDH; dh++) 661 dhrint(dh); 662 } 663 664 /* 665 * Turn on the line associated with dh dev. 666 */ 667 dmopen(dev) 668 dev_t dev; 669 { 670 register struct tty *tp; 671 register struct dmdevice *addr; 672 register struct uba_device *ui; 673 register int unit; 674 register int dm; 675 int s; 676 677 unit = minor(dev); 678 dm = unit >> 4; 679 tp = &dh11[unit]; 680 unit &= 0xf; 681 if (dm >= NDH || (ui = dminfo[dm]) == 0 || ui->ui_alive == 0 || 682 (dhsoftCAR[dm]&(1<<unit))) { 683 tp->t_state |= CARR_ON; 684 return; 685 } 686 addr = (struct dmdevice *)ui->ui_addr; 687 s = spl5(); 688 addr->dmcsr &= ~DM_SE; 689 while (addr->dmcsr & DM_BUSY) 690 ; 691 addr->dmcsr = unit; 692 addr->dmlstat = DML_ON; 693 if (addr->dmlstat&DML_CAR) 694 tp->t_state |= CARR_ON; 695 addr->dmcsr = DM_IE|DM_SE; 696 while ((tp->t_state&CARR_ON)==0) 697 sleep((caddr_t)&tp->t_rawq, TTIPRI); 698 splx(s); 699 } 700 701 /* 702 * Dump control bits into the DM registers. 703 */ 704 dmctl(dev, bits, how) 705 dev_t dev; 706 int bits, how; 707 { 708 register struct uba_device *ui; 709 register struct dmdevice *addr; 710 register int unit, s; 711 int dm; 712 713 unit = minor(dev); 714 dm = unit >> 4; 715 if ((ui = dminfo[dm]) == 0 || ui->ui_alive == 0) 716 return; 717 addr = (struct dmdevice *)ui->ui_addr; 718 s = spl5(); 719 addr->dmcsr &= ~DM_SE; 720 while (addr->dmcsr & DM_BUSY) 721 ; 722 addr->dmcsr = unit & 0xf; 723 switch(how) { 724 case DMSET: 725 addr->dmlstat = bits; 726 break; 727 case DMBIS: 728 addr->dmlstat |= bits; 729 break; 730 case DMBIC: 731 addr->dmlstat &= ~bits; 732 break; 733 } 734 addr->dmcsr = DM_IE|DM_SE; 735 splx(s); 736 } 737 738 /* 739 * DM11 interrupt; deal with carrier transitions. 740 */ 741 dmintr(dm) 742 register int dm; 743 { 744 register struct uba_device *ui; 745 register struct tty *tp; 746 register struct dmdevice *addr; 747 748 ui = dminfo[dm]; 749 if (ui == 0) 750 return; 751 addr = (struct dmdevice *)ui->ui_addr; 752 if (addr->dmcsr&DM_DONE && addr->dmcsr&DM_CF) { 753 tp = &dh11[(dm<<4)+(addr->dmcsr&0xf)]; 754 wakeup((caddr_t)&tp->t_rawq); 755 if ((tp->t_state&WOPEN)==0 && 756 (tp->t_local&LMDMBUF)) { 757 if (addr->dmlstat & DML_CAR) { 758 tp->t_state &= ~TTSTOP; 759 ttstart(tp); 760 } else if ((tp->t_state&TTSTOP) == 0) { 761 tp->t_state |= TTSTOP; 762 dhstop(tp, 0); 763 } 764 } else if ((addr->dmlstat&DML_CAR)==0) { 765 if ((tp->t_state&WOPEN)==0 && 766 (tp->t_local&LNOHANG)==0) { 767 gsignal(tp->t_pgrp, SIGHUP); 768 gsignal(tp->t_pgrp, SIGCONT); 769 addr->dmlstat = 0; 770 flushtty(tp, FREAD|FWRITE); 771 } 772 tp->t_state &= ~CARR_ON; 773 } else 774 tp->t_state |= CARR_ON; 775 } 776 addr->dmcsr = DM_IE|DM_SE; 777 } 778 #endif 779