1 /* dz.c 4.35 82/03/13 */ 2 3 #include "dz.h" 4 #if NDZ > 0 5 /* 6 * DZ-11 and DZ32 Driver 7 * 8 * This driver mimics dh.c; see it for explanation of common code. 9 */ 10 #include "bk.h" 11 #include "../h/param.h" 12 #include "../h/systm.h" 13 #include "../h/tty.h" 14 #include "../h/dir.h" 15 #include "../h/user.h" 16 #include "../h/proc.h" 17 #include "../h/map.h" 18 #include "../h/pte.h" 19 #include "../h/buf.h" 20 #include "../h/vm.h" 21 #include "../h/ubavar.h" 22 #include "../h/conf.h" 23 #include "../h/pdma.h" 24 #include "../h/bk.h" 25 #include "../h/file.h" 26 27 /* 28 * Driver information for auto-configuration stuff. 29 */ 30 int dzprobe(), dzattach(), dzrint(); 31 struct uba_device *dzinfo[NDZ]; 32 u_short dzstd[] = { 0 }; 33 struct uba_driver dzdriver = 34 { dzprobe, 0, dzattach, 0, dzstd, "dz", dzinfo }; 35 36 #define NDZLINE (NDZ*8) 37 38 /* 39 * Registers and bits 40 */ 41 42 /* bits in dzlpr */ 43 #define BITS7 0020 44 #define BITS8 0030 45 #define TWOSB 0040 46 #define PENABLE 0100 47 #define OPAR 0200 48 49 /* bits in dzrbuf */ 50 #define DZ_PE 010000 51 #define DZ_FE 020000 52 #define DZ_DO 040000 53 54 /* bits in dzcsr */ 55 #define DZ_32 000001 /* DZ32 mode */ 56 #define DZ_MIE 000002 /* Modem Interrupt Enable */ 57 #define DZ_CLR 000020 /* Reset dz */ 58 #define DZ_MSE 000040 /* Master Scan Enable */ 59 #define DZ_RIE 000100 /* Receiver Interrupt Enable */ 60 #define DZ_MSC 004000 /* Modem Status Change */ 61 #define DZ_SAE 010000 /* Silo Alarm Enable */ 62 #define DZ_TIE 040000 /* Transmit Interrupt Enable */ 63 #define DZ_IEN (DZ_32|DZ_MIE|DZ_MSE|DZ_RIE|DZ_TIE|DZ_SAE) 64 65 /* flags for modem-control */ 66 #define DZ_ON DZ_DTR 67 #define DZ_OFF 0 68 69 /* bits in dzlcs */ 70 #define DZ_ACK 0100000 /* ACK bit in dzlcs */ 71 #define DZ_RTS 0010000 /* Request To Send */ 72 #define DZ_ST 0004000 /* Secondary Transmit */ 73 #define DZ_BRK 0002000 /* Break */ 74 #define DZ_DTR 0001000 /* Data Terminal Ready */ 75 #define DZ_LE 0000400 /* Line Enable */ 76 #define DZ_DSR 0000200 /* Data Set Ready */ 77 #define DZ_RI 0000100 /* Ring Indicate */ 78 #define DZ_CD 0000040 /* Carrier Detect */ 79 #define DZ_CTS 0000020 /* Clear To Send */ 80 #define DZ_SR 0000010 /* Secondary Receive */ 81 82 /* bits in dm lsr, copied from dh.c */ 83 #define DML_DSR 0000400 /* data set ready, not a real DM bit */ 84 #define DML_RNG 0000200 /* ring */ 85 #define DML_CAR 0000100 /* carrier detect */ 86 #define DML_CTS 0000040 /* clear to send */ 87 #define DML_SR 0000020 /* secondary receive */ 88 #define DML_ST 0000010 /* secondary transmit */ 89 #define DML_RTS 0000004 /* request to send */ 90 #define DML_DTR 0000002 /* data terminal ready */ 91 #define DML_LE 0000001 /* line enable */ 92 93 int dzstart(), dzxint(), dzdma(); 94 int ttrstrt(); 95 struct tty dz_tty[NDZLINE]; 96 int dz_cnt = { NDZLINE }; 97 int dzact; 98 99 struct device { 100 short dzcsr; 101 short dzrbuf; 102 union { 103 struct { 104 char dztcr0; 105 char dzdtr0; 106 char dztbuf0; 107 char dzbrk0; 108 } dz11; 109 struct { 110 short dzlcs0; 111 char dztbuf0; 112 char dzlnen0; 113 } dz32; 114 } dzun; 115 }; 116 117 #define dzlpr dzrbuf 118 #define dzmsr dzun.dz11.dzbrk0 119 #define dztcr dzun.dz11.dztcr0 120 #define dzdtr dzun.dz11.dzdtr0 121 #define dztbuf dzun.dz11.dztbuf0 122 #define dzlcs dzun.dz32.dzlcs0 123 #define dzbrk dzmsr 124 #define dzlnen dzun.dz32.dzlnen0 125 #define dzmtsr dzun.dz32.dztbuf0; 126 127 #define dzwait(x) while (((x)->dzlcs & DZ_ACK) == 0) 128 129 /* 130 * Software copy of dzbrk since it isn't readable 131 */ 132 char dz_brk[NDZ]; 133 char dzsoftCAR[NDZ]; 134 char dz_lnen[NDZ]; /* saved line enable bits for DZ32 */ 135 136 /* 137 * The dz11 doesn't interrupt on carrier transitions, so 138 * we have to use a timer to watch it. 139 */ 140 char dz_timer; /* timer started? */ 141 142 /* 143 * Pdma structures for fast output code 144 */ 145 struct pdma dzpdma[NDZLINE]; 146 147 char dz_speeds[] = 148 { 0,020,021,022,023,024,0,025,026,027,030,032,034,036,0,0 }; 149 150 dzprobe(reg) 151 caddr_t reg; 152 { 153 register int br, cvec; 154 register struct device *dzaddr = (struct device *)reg; 155 156 #ifdef lint 157 br = 0; cvec = br; br = cvec; 158 dzrint(0); dzxint((struct tty *)0); 159 #endif 160 dzaddr->dzcsr = DZ_TIE|DZ_MSE|DZ_32; 161 if (dzaddr->dzcsr & DZ_32) 162 dzaddr->dzlnen = 1; 163 else 164 dzaddr->dztcr = 1; /* enable any line */ 165 DELAY(100000); 166 dzaddr->dzcsr = DZ_CLR|DZ_32; /* reset everything */ 167 if (cvec && cvec != 0x200) 168 cvec -= 4; 169 return (1); 170 } 171 172 dzattach(ui) 173 register struct uba_device *ui; 174 { 175 register struct pdma *pdp = &dzpdma[ui->ui_unit*8]; 176 register struct tty *tp = &dz_tty[ui->ui_unit*8]; 177 register int cntr; 178 extern dzscan(); 179 180 for (cntr = 0; cntr < 8; cntr++) { 181 pdp->p_addr = (struct device *)ui->ui_addr; 182 pdp->p_arg = (int)tp; 183 pdp->p_fcn = dzxint; 184 pdp++, tp++; 185 } 186 dzsoftCAR[ui->ui_unit] = ui->ui_flags; 187 if (dz_timer == 0) { 188 dz_timer++; 189 timeout(dzscan, (caddr_t)0, hz); 190 } 191 } 192 193 /*ARGSUSED*/ 194 dzopen(dev, flag) 195 dev_t dev; 196 { 197 register struct tty *tp; 198 register int unit; 199 200 unit = minor(dev); 201 if (unit >= dz_cnt || dzpdma[unit].p_addr == 0) { 202 u.u_error = ENXIO; 203 return; 204 } 205 tp = &dz_tty[unit]; 206 tp->t_addr = (caddr_t)&dzpdma[unit]; 207 tp->t_oproc = dzstart; 208 tp->t_state |= TS_WOPEN; 209 if ((tp->t_state & TS_ISOPEN) == 0) { 210 ttychars(tp); 211 tp->t_ospeed = tp->t_ispeed = B300; 212 tp->t_flags = ODDP|EVENP|ECHO; 213 /* tp->t_state |= TS_HUPCLS; */ 214 dzparam(unit); 215 } else if (tp->t_state&TS_XCLUDE && u.u_uid != 0) { 216 u.u_error = EBUSY; 217 return; 218 } 219 (void) dzmctl(dev, DZ_ON, DMSET); 220 (void) spl5(); 221 while ((tp->t_state & TS_CARR_ON) == 0) { 222 tp->t_state |= TS_WOPEN; 223 sleep((caddr_t)&tp->t_rawq, TTIPRI); 224 } 225 (void) spl0(); 226 (*linesw[tp->t_line].l_open)(dev, tp); 227 } 228 229 /*ARGSUSED*/ 230 dzclose(dev, flag) 231 dev_t dev; 232 { 233 register struct tty *tp; 234 register int unit; 235 register struct device *dzaddr; 236 int dz; 237 238 unit = minor(dev); 239 dz = unit >> 3; 240 tp = &dz_tty[unit]; 241 (*linesw[tp->t_line].l_close)(tp); 242 dzaddr = dzpdma[unit].p_addr; 243 if (dzaddr->dzcsr&DZ_32) 244 (void) dzmctl(dev, DZ_BRK, DMBIC); 245 else 246 dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07))); 247 if ((tp->t_state&TS_HUPCLS) || (tp->t_state&TS_ISOPEN) == 0) 248 (void) dzmctl(dev, DZ_OFF, DMSET); 249 ttyclose(tp); 250 } 251 252 dzread(dev) 253 dev_t dev; 254 { 255 register struct tty *tp; 256 257 tp = &dz_tty[minor(dev)]; 258 (*linesw[tp->t_line].l_read)(tp); 259 } 260 261 dzwrite(dev) 262 dev_t dev; 263 { 264 register struct tty *tp; 265 266 tp = &dz_tty[minor(dev)]; 267 (*linesw[tp->t_line].l_write)(tp); 268 } 269 270 /*ARGSUSED*/ 271 dzrint(dz) 272 int dz; 273 { 274 register struct tty *tp; 275 register int c; 276 register struct device *dzaddr; 277 register struct tty *tp0; 278 register int unit; 279 int overrun = 0; 280 281 if ((dzact & (1<<dz)) == 0) 282 return; 283 unit = dz * 8; 284 dzaddr = dzpdma[unit].p_addr; 285 tp0 = &dz_tty[unit]; 286 dzaddr->dzcsr &= ~(DZ_RIE|DZ_MIE); /* the manual says this song */ 287 dzaddr->dzcsr |= DZ_RIE|DZ_MIE; /* and dance is necessary */ 288 while (dzaddr->dzcsr & DZ_MSC) { /* DZ32 modem change interrupt */ 289 c = dzaddr->dzmtsr; 290 tp = tp0 + (c&7); 291 if (tp >= &dz_tty[dz_cnt]) 292 break; 293 dzaddr->dzlcs = c&7; /* get status of modem lines */ 294 dzwait(dzaddr); /* wait for them */ 295 if (c & DZ_CD) /* carrier status change? */ 296 if (dzaddr->dzlcs & DZ_CD) { /* carrier up? */ 297 if ((tp->t_state&TS_CARR_ON) == 0) { 298 wakeup((caddr_t)&tp->t_rawq); 299 tp->t_state |= TS_CARR_ON; 300 } 301 } else { /* no carrier */ 302 if (tp->t_state&TS_CARR_ON) { 303 gsignal(tp->t_pgrp, SIGHUP); 304 gsignal(tp->t_pgrp, SIGCONT); 305 dzaddr->dzlcs = DZ_ACK|(c&7); 306 flushtty(tp, FREAD|FWRITE); 307 } 308 tp->t_state &= ~TS_CARR_ON; 309 } 310 } 311 while ((c = dzaddr->dzrbuf) < 0) { /* char present */ 312 tp = tp0 + ((c>>8)&07); 313 if (tp >= &dz_tty[dz_cnt]) 314 continue; 315 if ((tp->t_state & TS_ISOPEN) == 0) { 316 wakeup((caddr_t)&tp->t_rawq); 317 continue; 318 } 319 if (c&DZ_FE) 320 if (tp->t_flags & RAW) 321 c = 0; 322 else 323 c = tun.t_intrc; 324 if (c&DZ_DO && overrun == 0) { 325 /* printf("dz%d,%d: silo overflow\n", dz, (c>>8)&7); */ 326 overrun = 1; 327 } 328 if (c&DZ_PE) 329 if (((tp->t_flags & (EVENP|ODDP)) == EVENP) 330 || ((tp->t_flags & (EVENP|ODDP)) == ODDP)) 331 continue; 332 #if NBK > 0 333 if (tp->t_line == NETLDISC) { 334 c &= 0177; 335 BKINPUT(c, tp); 336 } else 337 #endif 338 (*linesw[tp->t_line].l_rint)(c, tp); 339 } 340 } 341 342 /*ARGSUSED*/ 343 dzioctl(dev, cmd, addr, flag) 344 dev_t dev; 345 caddr_t addr; 346 { 347 register struct tty *tp; 348 register int unit = minor(dev); 349 register int dz = unit >> 3; 350 register struct device *dzaddr; 351 int temp; 352 353 tp = &dz_tty[unit]; 354 cmd = (*linesw[tp->t_line].l_ioctl)(tp, cmd, addr); 355 if (cmd == 0) 356 return; 357 if (ttioctl(tp, cmd, addr, flag)) { 358 if (cmd==TIOCSETP || cmd==TIOCSETN) 359 dzparam(unit); 360 } else switch(cmd) { 361 362 case TIOCSBRK: 363 dzaddr = ((struct pdma *)(tp->t_addr))->p_addr; 364 if (dzaddr->dzcsr&DZ_32) 365 (void) dzmctl(dev, DZ_BRK, DMBIS); 366 else 367 dzaddr->dzbrk = (dz_brk[dz] |= 1 << (unit&07)); 368 break; 369 case TIOCCBRK: 370 dzaddr = ((struct pdma *)(tp->t_addr))->p_addr; 371 if (dzaddr->dzcsr&DZ_32) 372 (void) dzmctl(dev, DZ_BRK, DMBIC); 373 else 374 dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07))); 375 break; 376 case TIOCSDTR: 377 (void) dzmctl(dev, DZ_DTR|DZ_RTS, DMBIS); 378 break; 379 case TIOCCDTR: 380 (void) dzmctl(dev, DZ_DTR|DZ_RTS, DMBIC); 381 break; 382 case TIOCMSET: 383 if (copyin(addr, (caddr_t) &temp, sizeof(temp))) 384 u.u_error = EFAULT; 385 else 386 (void) dzmctl(dev, dmtodz(temp), DMSET); 387 break; 388 case TIOCMBIS: 389 if (copyin(addr, (caddr_t) &temp, sizeof(temp))) 390 u.u_error = EFAULT; 391 else 392 (void) dzmctl(dev, dmtodz(temp), DMBIS); 393 break; 394 case TIOCMBIC: 395 if (copyin(addr, (caddr_t) &temp, sizeof(temp))) 396 u.u_error = EFAULT; 397 else 398 (void) dzmctl(dev, dmtodz(temp), DMBIC); 399 break; 400 case TIOCMGET: 401 temp = dztodm(dzmctl(dev, 0, DMGET)); 402 if (copyout((caddr_t) &temp, addr, sizeof(temp))) 403 u.u_error = EFAULT; 404 break; 405 default: 406 u.u_error = ENOTTY; 407 } 408 } 409 410 dmtodz(bits) 411 register int bits; 412 { 413 register int b; 414 415 b = (bits >>1) & 0370; 416 if (bits & DML_ST) b |= DZ_ST; 417 if (bits & DML_RTS) b |= DZ_RTS; 418 if (bits & DML_DTR) b |= DZ_DTR; 419 if (bits & DML_LE) b |= DZ_LE; 420 return(b); 421 } 422 423 dztodm(bits) 424 register int bits; 425 { 426 register int b; 427 428 b = (bits << 1) & 0360; 429 if (bits & DZ_DSR) b |= DML_DSR; 430 if (bits & DZ_DTR) b |= DML_DTR; 431 if (bits & DZ_ST) b |= DML_ST; 432 if (bits & DZ_RTS) b |= DML_RTS; 433 return(b); 434 } 435 436 dzparam(unit) 437 register int unit; 438 { 439 register struct tty *tp; 440 register struct device *dzaddr; 441 register int lpr; 442 443 tp = &dz_tty[unit]; 444 dzaddr = dzpdma[unit].p_addr; 445 dzaddr->dzcsr = DZ_IEN; 446 dzact |= (1<<(unit>>3)); 447 if (tp->t_ispeed == 0) { 448 (void) dzmctl(unit, DZ_OFF, DMSET); /* hang up line */ 449 return; 450 } 451 lpr = (dz_speeds[tp->t_ispeed]<<8) | (unit & 07); 452 if ((tp->t_local&LLITOUT) || (tp->t_flags&RAW)) 453 lpr |= BITS8; 454 else 455 lpr |= (BITS7|PENABLE); 456 if ((tp->t_flags & EVENP) == 0) 457 lpr |= OPAR; 458 if (tp->t_ispeed == B110) 459 lpr |= TWOSB; 460 dzaddr->dzlpr = lpr; 461 } 462 463 dzxint(tp) 464 register struct tty *tp; 465 { 466 register struct pdma *dp; 467 register s, dz, unit; 468 469 s = spl5(); /* block pdma interrupts */ 470 dp = (struct pdma *)tp->t_addr; 471 tp->t_state &= ~TS_BUSY; 472 if (tp->t_state & TS_FLUSH) 473 tp->t_state &= ~TS_FLUSH; 474 else { 475 ndflush(&tp->t_outq, dp->p_mem-tp->t_outq.c_cf); 476 dp->p_end = dp->p_mem = tp->t_outq.c_cf; 477 } 478 if (tp->t_line) 479 (*linesw[tp->t_line].l_start)(tp); 480 else 481 dzstart(tp); 482 dz = minor(tp->t_dev) >> 3; 483 unit = minor(tp->t_dev) & 7; 484 if (tp->t_outq.c_cc == 0 || (tp->t_state&TS_BUSY)==0) 485 if (dp->p_addr->dzcsr & DZ_32) 486 dp->p_addr->dzlnen = (dz_lnen[dz] &= ~(1<<unit)); 487 else 488 dp->p_addr->dztcr &= ~(1<<unit); 489 splx(s); 490 } 491 492 dzstart(tp) 493 register struct tty *tp; 494 { 495 register struct pdma *dp; 496 register struct device *dzaddr; 497 register int cc; 498 int s, dz, unit; 499 500 dp = (struct pdma *)tp->t_addr; 501 dzaddr = dp->p_addr; 502 s = spl5(); 503 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 504 goto out; 505 if (tp->t_outq.c_cc <= TTLOWAT(tp)) { 506 if (tp->t_state&TS_ASLEEP) { 507 tp->t_state &= ~TS_ASLEEP; 508 wakeup((caddr_t)&tp->t_outq); 509 } 510 if (tp->t_wsel) { 511 selwakeup(tp->t_wsel, tp->t_state & TS_WCOLL); 512 tp->t_wsel = 0; 513 tp->t_state &= ~TS_WCOLL; 514 } 515 } 516 if (tp->t_outq.c_cc == 0) 517 goto out; 518 if ((tp->t_flags&RAW) || (tp->t_local&LLITOUT)) 519 cc = ndqb(&tp->t_outq, 0); 520 else { 521 cc = ndqb(&tp->t_outq, 0200); 522 if (cc == 0) { 523 cc = getc(&tp->t_outq); 524 timeout(ttrstrt, (caddr_t)tp, (cc&0x7f) + 6); 525 tp->t_state |= TS_TIMEOUT; 526 goto out; 527 } 528 } 529 tp->t_state |= TS_BUSY; 530 dp->p_end = dp->p_mem = tp->t_outq.c_cf; 531 dp->p_end += cc; 532 dz = minor(tp->t_dev) >> 3; 533 unit = minor(tp->t_dev) & 7; 534 if (dzaddr->dzcsr & DZ_32) 535 dzaddr->dzlnen = (dz_lnen[dz] |= (1<<unit)); 536 else 537 dzaddr->dztcr |= (1<<unit); 538 out: 539 splx(s); 540 } 541 542 /* 543 * Stop output on a line. 544 */ 545 /*ARGSUSED*/ 546 dzstop(tp, flag) 547 register struct tty *tp; 548 { 549 register struct pdma *dp; 550 register int s; 551 552 dp = (struct pdma *)tp->t_addr; 553 s = spl5(); 554 if (tp->t_state & TS_BUSY) { 555 dp->p_end = dp->p_mem; 556 if ((tp->t_state&TS_TTSTOP)==0) 557 tp->t_state |= TS_FLUSH; 558 } 559 splx(s); 560 } 561 562 dzmctl(dev, bits, how) 563 dev_t dev; 564 int bits, how; 565 { 566 register struct device *dzaddr; 567 register int unit, mbits; 568 int b, s; 569 570 unit = minor(dev); 571 b = 1<<(unit&7); 572 dzaddr = dzpdma[unit].p_addr; 573 s = spl5(); 574 if (dzaddr->dzcsr & DZ_32) { 575 dzwait(dzaddr) 576 DELAY(100); /* IS 100 TOO MUCH? */ 577 dzaddr->dzlcs = unit&7; 578 DELAY(100); 579 dzwait(dzaddr) 580 DELAY(100); 581 mbits = dzaddr->dzlcs; 582 mbits &= 0177770; 583 } else { 584 mbits = (dzaddr->dzdtr & b) ? DZ_DTR : 0; 585 mbits |= (dzaddr->dzmsr & b) ? DZ_CD : 0; 586 mbits |= (dzaddr->dztbuf & b) ? DZ_RI : 0; 587 } 588 switch (how) { 589 case DMSET: 590 mbits = bits; 591 break; 592 593 case DMBIS: 594 mbits |= bits; 595 break; 596 597 case DMBIC: 598 mbits &= ~bits; 599 break; 600 601 case DMGET: 602 (void) splx(s); 603 return(mbits); 604 } 605 if (dzaddr->dzcsr & DZ_32) { 606 mbits |= DZ_ACK|(unit&7); 607 dzaddr->dzlcs = mbits; 608 } else { 609 if (mbits & DZ_DTR) 610 dzaddr->dzdtr |= b; 611 else 612 dzaddr->dzdtr &= ~b; 613 } 614 (void) splx(s); 615 return(mbits); 616 } 617 618 dzscan() 619 { 620 register i; 621 register struct device *dzaddr; 622 register bit; 623 register struct tty *tp; 624 register car; 625 626 for (i = 0; i < dz_cnt ; i++) { 627 dzaddr = dzpdma[i].p_addr; 628 if (dzaddr == 0) 629 continue; 630 tp = &dz_tty[i]; 631 bit = 1<<(i&07); 632 car = 0; 633 if (dzsoftCAR[i>>3]&bit) 634 car = 1; 635 else if (dzaddr->dzcsr & DZ_32) { 636 dzaddr->dzlcs = i&07; 637 dzwait(dzaddr); 638 car = dzaddr->dzlcs & DZ_CD; 639 } else 640 car = dzaddr->dzmsr&bit; 641 if (car) { 642 /* carrier present */ 643 if ((tp->t_state & TS_CARR_ON) == 0) { 644 wakeup((caddr_t)&tp->t_rawq); 645 tp->t_state |= TS_CARR_ON; 646 } 647 } else { 648 if ((tp->t_state&TS_CARR_ON) && 649 (tp->t_local&LNOHANG)==0) { 650 /* carrier lost */ 651 if (tp->t_state&TS_ISOPEN) { 652 gsignal(tp->t_pgrp, SIGHUP); 653 gsignal(tp->t_pgrp, SIGCONT); 654 dzaddr->dzdtr &= ~bit; 655 flushtty(tp, FREAD|FWRITE); 656 } 657 tp->t_state &= ~TS_CARR_ON; 658 } 659 } 660 } 661 timeout(dzscan, (caddr_t)0, 2*hz); 662 } 663 664 dztimer() 665 { 666 int dz; 667 668 for (dz = 0; dz < NDZ; dz++) 669 dzrint(dz); 670 } 671 672 /* 673 * Reset state of driver if UBA reset was necessary. 674 * Reset parameters and restart transmission on open lines. 675 */ 676 dzreset(uban) 677 int uban; 678 { 679 register int unit; 680 register struct tty *tp; 681 register struct uba_device *ui; 682 683 for (unit = 0; unit < NDZLINE; unit++) { 684 ui = dzinfo[unit >> 3]; 685 if (ui == 0 || ui->ui_ubanum != uban || ui->ui_alive == 0) 686 continue; 687 if (unit%8 == 0) 688 printf(" dz%d", unit>>3); 689 tp = &dz_tty[unit]; 690 if (tp->t_state & (TS_ISOPEN|TS_WOPEN)) { 691 dzparam(unit); 692 (void) dzmctl(unit, DZ_ON, DMSET); 693 tp->t_state &= ~TS_BUSY; 694 dzstart(tp); 695 } 696 } 697 dztimer(); 698 } 699 #endif 700