1 /* dz.c 4.48 82/12/17 */ 2 3 #include "dz.h" 4 #if NDZ > 0 5 /* 6 * DZ-11 and DZ32 Driver 7 * 8 * This driver mimics dh.c; see it for explanation of common code. 9 */ 10 #include "bk.h" 11 12 #include "../machine/pte.h" 13 14 #include "../h/param.h" 15 #include "../h/systm.h" 16 #include "../h/ioctl.h" 17 #include "../h/tty.h" 18 #include "../h/dir.h" 19 #include "../h/user.h" 20 #include "../h/proc.h" 21 #include "../h/map.h" 22 #include "../h/buf.h" 23 #include "../h/vm.h" 24 #include "../h/conf.h" 25 #include "../h/bk.h" 26 #include "../h/file.h" 27 #include "../h/uio.h" 28 29 #include "../vaxuba/pdma.h" 30 #include "../vaxuba/ubavar.h" 31 32 /* 33 * Driver information for auto-configuration stuff. 34 */ 35 int dzprobe(), dzattach(), dzrint(); 36 struct uba_device *dzinfo[NDZ]; 37 u_short dzstd[] = { 0 }; 38 struct uba_driver dzdriver = 39 { dzprobe, 0, dzattach, 0, dzstd, "dz", dzinfo }; 40 41 #define NDZLINE (NDZ*8) 42 43 /* 44 * Registers and bits 45 */ 46 47 /* bits in dzlpr */ 48 #define BITS7 0020 49 #define BITS8 0030 50 #define TWOSB 0040 51 #define PENABLE 0100 52 #define OPAR 0200 53 54 /* bits in dzrbuf */ 55 #define DZ_PE 010000 56 #define DZ_FE 020000 57 #define DZ_DO 040000 58 59 /* bits in dzcsr */ 60 #define DZ_32 000001 /* DZ32 mode */ 61 #define DZ_MIE 000002 /* Modem Interrupt Enable */ 62 #define DZ_CLR 000020 /* Reset dz */ 63 #define DZ_MSE 000040 /* Master Scan Enable */ 64 #define DZ_RIE 000100 /* Receiver Interrupt Enable */ 65 #define DZ_MSC 004000 /* Modem Status Change */ 66 #define DZ_SAE 010000 /* Silo Alarm Enable */ 67 #define DZ_TIE 040000 /* Transmit Interrupt Enable */ 68 #define DZ_IEN (DZ_32|DZ_MIE|DZ_MSE|DZ_RIE|DZ_TIE|DZ_SAE) 69 70 /* flags for modem-control */ 71 #define DZ_ON DZ_DTR 72 #define DZ_OFF 0 73 74 /* bits in dzlcs */ 75 #define DZ_ACK 0100000 /* ACK bit in dzlcs */ 76 #define DZ_RTS 0010000 /* Request To Send */ 77 #define DZ_ST 0004000 /* Secondary Transmit */ 78 #define DZ_BRK 0002000 /* Break */ 79 #define DZ_DTR 0001000 /* Data Terminal Ready */ 80 #define DZ_LE 0000400 /* Line Enable */ 81 #define DZ_DSR 0000200 /* Data Set Ready */ 82 #define DZ_RI 0000100 /* Ring Indicate */ 83 #define DZ_CD 0000040 /* Carrier Detect */ 84 #define DZ_CTS 0000020 /* Clear To Send */ 85 #define DZ_SR 0000010 /* Secondary Receive */ 86 87 /* bits in dm lsr, copied from dh.c */ 88 #define DML_DSR 0000400 /* data set ready, not a real DM bit */ 89 #define DML_RNG 0000200 /* ring */ 90 #define DML_CAR 0000100 /* carrier detect */ 91 #define DML_CTS 0000040 /* clear to send */ 92 #define DML_SR 0000020 /* secondary receive */ 93 #define DML_ST 0000010 /* secondary transmit */ 94 #define DML_RTS 0000004 /* request to send */ 95 #define DML_DTR 0000002 /* data terminal ready */ 96 #define DML_LE 0000001 /* line enable */ 97 98 int dzstart(), dzxint(), dzdma(); 99 int ttrstrt(); 100 struct tty dz_tty[NDZLINE]; 101 int dz_cnt = { NDZLINE }; 102 int dzact; 103 104 struct device { 105 short dzcsr; 106 short dzrbuf; 107 union { 108 struct { 109 char dztcr0; 110 char dzdtr0; 111 char dztbuf0; 112 char dzbrk0; 113 } dz11; 114 struct { 115 short dzlcs0; 116 char dztbuf0; 117 char dzlnen0; 118 } dz32; 119 } dzun; 120 }; 121 122 #define dzlpr dzrbuf 123 #define dzmsr dzun.dz11.dzbrk0 124 #define dztcr dzun.dz11.dztcr0 125 #define dzdtr dzun.dz11.dzdtr0 126 #define dztbuf dzun.dz11.dztbuf0 127 #define dzlcs dzun.dz32.dzlcs0 128 #define dzbrk dzmsr 129 #define dzlnen dzun.dz32.dzlnen0 130 #define dzmtsr dzun.dz32.dztbuf0 131 132 #define dzwait(x) while (((x)->dzlcs & DZ_ACK) == 0) 133 134 /* 135 * Software copy of dzbrk since it isn't readable 136 */ 137 char dz_brk[NDZ]; 138 char dzsoftCAR[NDZ]; 139 char dz_lnen[NDZ]; /* saved line enable bits for DZ32 */ 140 141 /* 142 * The dz11 doesn't interrupt on carrier transitions, so 143 * we have to use a timer to watch it. 144 */ 145 char dz_timer; /* timer started? */ 146 147 /* 148 * Pdma structures for fast output code 149 */ 150 struct pdma dzpdma[NDZLINE]; 151 152 char dz_speeds[] = 153 { 0,020,021,022,023,024,0,025,026,027,030,032,034,036,037,0 }; 154 155 #ifndef PORTSELECTOR 156 #define ISPEED B300 157 #define IFLAGS (EVENP|ODDP|ECHO) 158 #else 159 #define ISPEED B4800 160 #define IFLAGS (EVENP|ODDP) 161 #endif 162 163 dzprobe(reg) 164 caddr_t reg; 165 { 166 register int br, cvec; 167 register struct device *dzaddr = (struct device *)reg; 168 169 #ifdef lint 170 br = 0; cvec = br; br = cvec; 171 dzrint(0); dzxint((struct tty *)0); 172 #endif 173 dzaddr->dzcsr = DZ_TIE|DZ_MSE|DZ_32; 174 if (dzaddr->dzcsr & DZ_32) 175 dzaddr->dzlnen = 1; 176 else 177 dzaddr->dztcr = 1; /* enable any line */ 178 DELAY(100000); 179 dzaddr->dzcsr = DZ_CLR|DZ_32; /* reset everything */ 180 if (cvec && cvec != 0x200) 181 cvec -= 4; 182 return (sizeof (struct device)); 183 } 184 185 dzattach(ui) 186 register struct uba_device *ui; 187 { 188 register struct pdma *pdp = &dzpdma[ui->ui_unit*8]; 189 register struct tty *tp = &dz_tty[ui->ui_unit*8]; 190 register int cntr; 191 extern dzscan(); 192 193 for (cntr = 0; cntr < 8; cntr++) { 194 pdp->p_addr = (struct device *)ui->ui_addr; 195 pdp->p_arg = (int)tp; 196 pdp->p_fcn = dzxint; 197 pdp++, tp++; 198 } 199 dzsoftCAR[ui->ui_unit] = ui->ui_flags; 200 if (dz_timer == 0) { 201 dz_timer++; 202 timeout(dzscan, (caddr_t)0, hz); 203 } 204 } 205 206 /*ARGSUSED*/ 207 dzopen(dev, flag) 208 dev_t dev; 209 { 210 register struct tty *tp; 211 register int unit; 212 213 unit = minor(dev); 214 if (unit >= dz_cnt || dzpdma[unit].p_addr == 0) 215 return (ENXIO); 216 tp = &dz_tty[unit]; 217 tp->t_addr = (caddr_t)&dzpdma[unit]; 218 tp->t_oproc = dzstart; 219 tp->t_state |= TS_WOPEN; 220 if ((tp->t_state & TS_ISOPEN) == 0) { 221 ttychars(tp); 222 tp->t_ospeed = tp->t_ispeed = ISPEED; 223 tp->t_flags = IFLAGS; 224 /* tp->t_state |= TS_HUPCLS; */ 225 dzparam(unit); 226 } else if (tp->t_state&TS_XCLUDE && u.u_uid != 0) 227 return (EBUSY); 228 (void) dzmctl(dev, DZ_ON, DMSET); 229 (void) spl5(); 230 while ((tp->t_state & TS_CARR_ON) == 0) { 231 tp->t_state |= TS_WOPEN; 232 sleep((caddr_t)&tp->t_rawq, TTIPRI); 233 } 234 (void) spl0(); 235 return ((*linesw[tp->t_line].l_open)(dev, tp)); 236 } 237 238 /*ARGSUSED*/ 239 dzclose(dev, flag) 240 dev_t dev; 241 { 242 register struct tty *tp; 243 register int unit; 244 register struct device *dzaddr; 245 int dz; 246 247 unit = minor(dev); 248 dz = unit >> 3; 249 tp = &dz_tty[unit]; 250 (*linesw[tp->t_line].l_close)(tp); 251 dzaddr = dzpdma[unit].p_addr; 252 if (dzaddr->dzcsr&DZ_32) 253 (void) dzmctl(dev, DZ_BRK, DMBIC); 254 else 255 dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07))); 256 if ((tp->t_state&(TS_HUPCLS|TS_WOPEN)) || (tp->t_state&TS_ISOPEN) == 0) 257 (void) dzmctl(dev, DZ_OFF, DMSET); 258 ttyclose(tp); 259 } 260 261 dzread(dev, uio) 262 dev_t dev; 263 struct uio *uio; 264 { 265 register struct tty *tp; 266 267 tp = &dz_tty[minor(dev)]; 268 return ((*linesw[tp->t_line].l_read)(tp, uio)); 269 } 270 271 dzwrite(dev, uio) 272 dev_t dev; 273 struct uio *uio; 274 { 275 register struct tty *tp; 276 277 tp = &dz_tty[minor(dev)]; 278 return ((*linesw[tp->t_line].l_write)(tp, uio)); 279 } 280 281 /*ARGSUSED*/ 282 dzrint(dz) 283 int dz; 284 { 285 register struct tty *tp; 286 register int c; 287 register struct device *dzaddr; 288 register struct tty *tp0; 289 register int unit; 290 int overrun = 0; 291 292 if ((dzact & (1<<dz)) == 0) 293 return; 294 unit = dz * 8; 295 dzaddr = dzpdma[unit].p_addr; 296 tp0 = &dz_tty[unit]; 297 dzaddr->dzcsr &= ~(DZ_RIE|DZ_MIE); /* the manual says this song */ 298 dzaddr->dzcsr |= DZ_RIE|DZ_MIE; /* and dance is necessary */ 299 while (dzaddr->dzcsr & DZ_MSC) { /* DZ32 modem change interrupt */ 300 c = dzaddr->dzmtsr; 301 tp = tp0 + (c&7); 302 if (tp >= &dz_tty[dz_cnt]) 303 break; 304 dzaddr->dzlcs = c&7; /* get status of modem lines */ 305 dzwait(dzaddr); /* wait for them */ 306 if (c & DZ_CD) /* carrier status change? */ 307 if (dzaddr->dzlcs & DZ_CD) { /* carrier up? */ 308 if ((tp->t_state&TS_CARR_ON) == 0) { 309 wakeup((caddr_t)&tp->t_rawq); 310 tp->t_state |= TS_CARR_ON; 311 } 312 } else { /* no carrier */ 313 if (tp->t_state&TS_CARR_ON) { 314 gsignal(tp->t_pgrp, SIGHUP); 315 gsignal(tp->t_pgrp, SIGCONT); 316 dzaddr->dzlcs = DZ_ACK|(c&7); 317 flushtty(tp, FREAD|FWRITE); 318 } 319 tp->t_state &= ~TS_CARR_ON; 320 } 321 } 322 while ((c = dzaddr->dzrbuf) < 0) { /* char present */ 323 tp = tp0 + ((c>>8)&07); 324 if (tp >= &dz_tty[dz_cnt]) 325 continue; 326 if ((tp->t_state & TS_ISOPEN) == 0) { 327 wakeup((caddr_t)&tp->t_rawq); 328 #ifdef PORTSELECTOR 329 if ((tp->t_state&TS_WOPEN) == 0) 330 #endif 331 continue; 332 } 333 if (c&DZ_FE) 334 if (tp->t_flags & RAW) 335 c = 0; 336 else 337 c = tp->t_intrc; 338 if (c&DZ_DO && overrun == 0) { 339 /* printf("dz%d,%d: silo overflow\n", dz, (c>>8)&7); */ 340 overrun = 1; 341 } 342 if (c&DZ_PE) 343 if (((tp->t_flags & (EVENP|ODDP)) == EVENP) 344 || ((tp->t_flags & (EVENP|ODDP)) == ODDP)) 345 continue; 346 #if NBK > 0 347 if (tp->t_line == NETLDISC) { 348 c &= 0177; 349 BKINPUT(c, tp); 350 } else 351 #endif 352 (*linesw[tp->t_line].l_rint)(c, tp); 353 } 354 } 355 356 /*ARGSUSED*/ 357 dzioctl(dev, cmd, data, flag) 358 dev_t dev; 359 caddr_t data; 360 { 361 register struct tty *tp; 362 register int unit = minor(dev); 363 register int dz = unit >> 3; 364 register struct device *dzaddr; 365 int error; 366 367 tp = &dz_tty[unit]; 368 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag); 369 if (error >= 0) 370 return (error); 371 error = ttioctl(tp, cmd, data, flag); 372 if (error >= 0) { 373 if (cmd == TIOCSETP || cmd == TIOCSETN) 374 dzparam(unit); 375 return (error); 376 } 377 switch (cmd) { 378 379 case TIOCSBRK: 380 dzaddr = ((struct pdma *)(tp->t_addr))->p_addr; 381 if (dzaddr->dzcsr&DZ_32) 382 (void) dzmctl(dev, DZ_BRK, DMBIS); 383 else 384 dzaddr->dzbrk = (dz_brk[dz] |= 1 << (unit&07)); 385 break; 386 387 case TIOCCBRK: 388 dzaddr = ((struct pdma *)(tp->t_addr))->p_addr; 389 if (dzaddr->dzcsr&DZ_32) 390 (void) dzmctl(dev, DZ_BRK, DMBIC); 391 else 392 dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07))); 393 break; 394 395 case TIOCSDTR: 396 (void) dzmctl(dev, DZ_DTR|DZ_RTS, DMBIS); 397 break; 398 399 case TIOCCDTR: 400 (void) dzmctl(dev, DZ_DTR|DZ_RTS, DMBIC); 401 break; 402 403 case TIOCMSET: 404 (void) dzmctl(dev, dmtodz(*(int *)data), DMSET); 405 break; 406 407 case TIOCMBIS: 408 (void) dzmctl(dev, dmtodz(*(int *)data), DMBIS); 409 break; 410 411 case TIOCMBIC: 412 (void) dzmctl(dev, dmtodz(*(int *)data), DMBIC); 413 break; 414 415 case TIOCMGET: 416 *(int *)data = dztodm(dzmctl(dev, 0, DMGET)); 417 break; 418 419 default: 420 return (ENOTTY); 421 } 422 return (0); 423 } 424 425 dmtodz(bits) 426 register int bits; 427 { 428 register int b; 429 430 b = (bits >>1) & 0370; 431 if (bits & DML_ST) b |= DZ_ST; 432 if (bits & DML_RTS) b |= DZ_RTS; 433 if (bits & DML_DTR) b |= DZ_DTR; 434 if (bits & DML_LE) b |= DZ_LE; 435 return(b); 436 } 437 438 dztodm(bits) 439 register int bits; 440 { 441 register int b; 442 443 b = (bits << 1) & 0360; 444 if (bits & DZ_DSR) b |= DML_DSR; 445 if (bits & DZ_DTR) b |= DML_DTR; 446 if (bits & DZ_ST) b |= DML_ST; 447 if (bits & DZ_RTS) b |= DML_RTS; 448 return(b); 449 } 450 451 dzparam(unit) 452 register int unit; 453 { 454 register struct tty *tp; 455 register struct device *dzaddr; 456 register int lpr; 457 458 tp = &dz_tty[unit]; 459 dzaddr = dzpdma[unit].p_addr; 460 dzaddr->dzcsr = DZ_IEN; 461 dzact |= (1<<(unit>>3)); 462 if (tp->t_ispeed == 0) { 463 (void) dzmctl(unit, DZ_OFF, DMSET); /* hang up line */ 464 return; 465 } 466 lpr = (dz_speeds[tp->t_ispeed]<<8) | (unit & 07); 467 if (tp->t_flags & (RAW|LITOUT)) 468 lpr |= BITS8; 469 else 470 lpr |= (BITS7|PENABLE); 471 if ((tp->t_flags & EVENP) == 0) 472 lpr |= OPAR; 473 if (tp->t_ispeed == B110) 474 lpr |= TWOSB; 475 dzaddr->dzlpr = lpr; 476 } 477 478 dzxint(tp) 479 register struct tty *tp; 480 { 481 register struct pdma *dp; 482 register s, dz, unit; 483 484 s = spl5(); /* block pdma interrupts */ 485 dp = (struct pdma *)tp->t_addr; 486 tp->t_state &= ~TS_BUSY; 487 if (tp->t_state & TS_FLUSH) 488 tp->t_state &= ~TS_FLUSH; 489 else { 490 ndflush(&tp->t_outq, dp->p_mem-tp->t_outq.c_cf); 491 dp->p_end = dp->p_mem = tp->t_outq.c_cf; 492 } 493 if (tp->t_line) 494 (*linesw[tp->t_line].l_start)(tp); 495 else 496 dzstart(tp); 497 dz = minor(tp->t_dev) >> 3; 498 unit = minor(tp->t_dev) & 7; 499 if (tp->t_outq.c_cc == 0 || (tp->t_state&TS_BUSY)==0) 500 if (dp->p_addr->dzcsr & DZ_32) 501 dp->p_addr->dzlnen = (dz_lnen[dz] &= ~(1<<unit)); 502 else 503 dp->p_addr->dztcr &= ~(1<<unit); 504 splx(s); 505 } 506 507 dzstart(tp) 508 register struct tty *tp; 509 { 510 register struct pdma *dp; 511 register struct device *dzaddr; 512 register int cc; 513 int s, dz, unit; 514 515 dp = (struct pdma *)tp->t_addr; 516 dzaddr = dp->p_addr; 517 s = spl5(); 518 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 519 goto out; 520 if (tp->t_outq.c_cc <= TTLOWAT(tp)) { 521 if (tp->t_state&TS_ASLEEP) { 522 tp->t_state &= ~TS_ASLEEP; 523 wakeup((caddr_t)&tp->t_outq); 524 } 525 if (tp->t_wsel) { 526 selwakeup(tp->t_wsel, tp->t_state & TS_WCOLL); 527 tp->t_wsel = 0; 528 tp->t_state &= ~TS_WCOLL; 529 } 530 } 531 if (tp->t_outq.c_cc == 0) 532 goto out; 533 if (tp->t_flags & (RAW|LITOUT)) 534 cc = ndqb(&tp->t_outq, 0); 535 else { 536 cc = ndqb(&tp->t_outq, 0200); 537 if (cc == 0) { 538 cc = getc(&tp->t_outq); 539 timeout(ttrstrt, (caddr_t)tp, (cc&0x7f) + 6); 540 tp->t_state |= TS_TIMEOUT; 541 goto out; 542 } 543 } 544 tp->t_state |= TS_BUSY; 545 dp->p_end = dp->p_mem = tp->t_outq.c_cf; 546 dp->p_end += cc; 547 dz = minor(tp->t_dev) >> 3; 548 unit = minor(tp->t_dev) & 7; 549 if (dzaddr->dzcsr & DZ_32) 550 dzaddr->dzlnen = (dz_lnen[dz] |= (1<<unit)); 551 else 552 dzaddr->dztcr |= (1<<unit); 553 out: 554 splx(s); 555 } 556 557 /* 558 * Stop output on a line. 559 */ 560 /*ARGSUSED*/ 561 dzstop(tp, flag) 562 register struct tty *tp; 563 { 564 register struct pdma *dp; 565 register int s; 566 567 dp = (struct pdma *)tp->t_addr; 568 s = spl5(); 569 if (tp->t_state & TS_BUSY) { 570 dp->p_end = dp->p_mem; 571 if ((tp->t_state&TS_TTSTOP)==0) 572 tp->t_state |= TS_FLUSH; 573 } 574 splx(s); 575 } 576 577 dzmctl(dev, bits, how) 578 dev_t dev; 579 int bits, how; 580 { 581 register struct device *dzaddr; 582 register int unit, mbits; 583 int b, s; 584 585 unit = minor(dev); 586 b = 1<<(unit&7); 587 dzaddr = dzpdma[unit].p_addr; 588 s = spl5(); 589 if (dzaddr->dzcsr & DZ_32) { 590 dzwait(dzaddr) 591 DELAY(100); /* IS 100 TOO MUCH? */ 592 dzaddr->dzlcs = unit&7; 593 DELAY(100); 594 dzwait(dzaddr) 595 DELAY(100); 596 mbits = dzaddr->dzlcs; 597 mbits &= 0177770; 598 } else { 599 mbits = (dzaddr->dzdtr & b) ? DZ_DTR : 0; 600 mbits |= (dzaddr->dzmsr & b) ? DZ_CD : 0; 601 mbits |= (dzaddr->dztbuf & b) ? DZ_RI : 0; 602 } 603 switch (how) { 604 case DMSET: 605 mbits = bits; 606 break; 607 608 case DMBIS: 609 mbits |= bits; 610 break; 611 612 case DMBIC: 613 mbits &= ~bits; 614 break; 615 616 case DMGET: 617 (void) splx(s); 618 return(mbits); 619 } 620 if (dzaddr->dzcsr & DZ_32) { 621 mbits |= DZ_ACK|(unit&7); 622 dzaddr->dzlcs = mbits; 623 } else { 624 if (mbits & DZ_DTR) 625 dzaddr->dzdtr |= b; 626 else 627 dzaddr->dzdtr &= ~b; 628 } 629 (void) splx(s); 630 return(mbits); 631 } 632 633 dzscan() 634 { 635 register i; 636 register struct device *dzaddr; 637 register bit; 638 register struct tty *tp; 639 register car; 640 641 for (i = 0; i < dz_cnt ; i++) { 642 dzaddr = dzpdma[i].p_addr; 643 if (dzaddr == 0) 644 continue; 645 tp = &dz_tty[i]; 646 bit = 1<<(i&07); 647 car = 0; 648 if (dzsoftCAR[i>>3]&bit) 649 car = 1; 650 else if (dzaddr->dzcsr & DZ_32) { 651 dzaddr->dzlcs = i&07; 652 dzwait(dzaddr); 653 car = dzaddr->dzlcs & DZ_CD; 654 } else 655 car = dzaddr->dzmsr&bit; 656 if (car) { 657 /* carrier present */ 658 if ((tp->t_state & TS_CARR_ON) == 0) { 659 wakeup((caddr_t)&tp->t_rawq); 660 tp->t_state |= TS_CARR_ON; 661 } 662 } else { 663 if ((tp->t_state&TS_CARR_ON) && 664 (tp->t_flags&NOHANG) == 0) { 665 /* carrier lost */ 666 if (tp->t_state&TS_ISOPEN) { 667 gsignal(tp->t_pgrp, SIGHUP); 668 gsignal(tp->t_pgrp, SIGCONT); 669 dzaddr->dzdtr &= ~bit; 670 flushtty(tp, FREAD|FWRITE); 671 } 672 tp->t_state &= ~TS_CARR_ON; 673 } 674 } 675 } 676 timeout(dzscan, (caddr_t)0, 2*hz); 677 } 678 679 dztimer() 680 { 681 register int dz; 682 register int s = spl5(); 683 684 for (dz = 0; dz < NDZ; dz++) 685 dzrint(dz); 686 splx(s); 687 } 688 689 /* 690 * Reset state of driver if UBA reset was necessary. 691 * Reset parameters and restart transmission on open lines. 692 */ 693 dzreset(uban) 694 int uban; 695 { 696 register int unit; 697 register struct tty *tp; 698 register struct uba_device *ui; 699 700 for (unit = 0; unit < NDZLINE; unit++) { 701 ui = dzinfo[unit >> 3]; 702 if (ui == 0 || ui->ui_ubanum != uban || ui->ui_alive == 0) 703 continue; 704 if (unit%8 == 0) 705 printf(" dz%d", unit>>3); 706 tp = &dz_tty[unit]; 707 if (tp->t_state & (TS_ISOPEN|TS_WOPEN)) { 708 dzparam(unit); 709 (void) dzmctl(unit, DZ_ON, DMSET); 710 tp->t_state &= ~TS_BUSY; 711 dzstart(tp); 712 } 713 } 714 dztimer(); 715 } 716 #endif 717