1 /* dz.c 4.36 82/05/04 */ 2 3 #include "dz.h" 4 #if NDZ > 0 5 /* 6 * DZ-11 and DZ32 Driver 7 * 8 * This driver mimics dh.c; see it for explanation of common code. 9 */ 10 #include "bk.h" 11 #include "../h/param.h" 12 #include "../h/systm.h" 13 #include "../h/tty.h" 14 #include "../h/dir.h" 15 #include "../h/user.h" 16 #include "../h/proc.h" 17 #include "../h/map.h" 18 #include "../h/pte.h" 19 #include "../h/buf.h" 20 #include "../h/vm.h" 21 #include "../h/ubavar.h" 22 #include "../h/conf.h" 23 #include "../h/pdma.h" 24 #include "../h/bk.h" 25 #include "../h/file.h" 26 27 /* 28 * Driver information for auto-configuration stuff. 29 */ 30 int dzprobe(), dzattach(), dzrint(); 31 struct uba_device *dzinfo[NDZ]; 32 u_short dzstd[] = { 0 }; 33 struct uba_driver dzdriver = 34 { dzprobe, 0, dzattach, 0, dzstd, "dz", dzinfo }; 35 36 #define NDZLINE (NDZ*8) 37 38 /* 39 * Registers and bits 40 */ 41 42 /* bits in dzlpr */ 43 #define BITS7 0020 44 #define BITS8 0030 45 #define TWOSB 0040 46 #define PENABLE 0100 47 #define OPAR 0200 48 49 /* bits in dzrbuf */ 50 #define DZ_PE 010000 51 #define DZ_FE 020000 52 #define DZ_DO 040000 53 54 /* bits in dzcsr */ 55 #define DZ_32 000001 /* DZ32 mode */ 56 #define DZ_MIE 000002 /* Modem Interrupt Enable */ 57 #define DZ_CLR 000020 /* Reset dz */ 58 #define DZ_MSE 000040 /* Master Scan Enable */ 59 #define DZ_RIE 000100 /* Receiver Interrupt Enable */ 60 #define DZ_MSC 004000 /* Modem Status Change */ 61 #define DZ_SAE 010000 /* Silo Alarm Enable */ 62 #define DZ_TIE 040000 /* Transmit Interrupt Enable */ 63 #define DZ_IEN (DZ_32|DZ_MIE|DZ_MSE|DZ_RIE|DZ_TIE|DZ_SAE) 64 65 /* flags for modem-control */ 66 #define DZ_ON DZ_DTR 67 #define DZ_OFF 0 68 69 /* bits in dzlcs */ 70 #define DZ_ACK 0100000 /* ACK bit in dzlcs */ 71 #define DZ_RTS 0010000 /* Request To Send */ 72 #define DZ_ST 0004000 /* Secondary Transmit */ 73 #define DZ_BRK 0002000 /* Break */ 74 #define DZ_DTR 0001000 /* Data Terminal Ready */ 75 #define DZ_LE 0000400 /* Line Enable */ 76 #define DZ_DSR 0000200 /* Data Set Ready */ 77 #define DZ_RI 0000100 /* Ring Indicate */ 78 #define DZ_CD 0000040 /* Carrier Detect */ 79 #define DZ_CTS 0000020 /* Clear To Send */ 80 #define DZ_SR 0000010 /* Secondary Receive */ 81 82 /* bits in dm lsr, copied from dh.c */ 83 #define DML_DSR 0000400 /* data set ready, not a real DM bit */ 84 #define DML_RNG 0000200 /* ring */ 85 #define DML_CAR 0000100 /* carrier detect */ 86 #define DML_CTS 0000040 /* clear to send */ 87 #define DML_SR 0000020 /* secondary receive */ 88 #define DML_ST 0000010 /* secondary transmit */ 89 #define DML_RTS 0000004 /* request to send */ 90 #define DML_DTR 0000002 /* data terminal ready */ 91 #define DML_LE 0000001 /* line enable */ 92 93 int dzstart(), dzxint(), dzdma(); 94 int ttrstrt(); 95 struct tty dz_tty[NDZLINE]; 96 int dz_cnt = { NDZLINE }; 97 int dzact; 98 99 struct device { 100 short dzcsr; 101 short dzrbuf; 102 union { 103 struct { 104 char dztcr0; 105 char dzdtr0; 106 char dztbuf0; 107 char dzbrk0; 108 } dz11; 109 struct { 110 short dzlcs0; 111 char dztbuf0; 112 char dzlnen0; 113 } dz32; 114 } dzun; 115 }; 116 117 #define dzlpr dzrbuf 118 #define dzmsr dzun.dz11.dzbrk0 119 #define dztcr dzun.dz11.dztcr0 120 #define dzdtr dzun.dz11.dzdtr0 121 #define dztbuf dzun.dz11.dztbuf0 122 #define dzlcs dzun.dz32.dzlcs0 123 #define dzbrk dzmsr 124 #define dzlnen dzun.dz32.dzlnen0 125 #define dzmtsr dzun.dz32.dztbuf0; 126 127 #define dzwait(x) while (((x)->dzlcs & DZ_ACK) == 0) 128 129 /* 130 * Software copy of dzbrk since it isn't readable 131 */ 132 char dz_brk[NDZ]; 133 char dzsoftCAR[NDZ]; 134 char dz_lnen[NDZ]; /* saved line enable bits for DZ32 */ 135 136 /* 137 * The dz11 doesn't interrupt on carrier transitions, so 138 * we have to use a timer to watch it. 139 */ 140 char dz_timer; /* timer started? */ 141 142 /* 143 * Pdma structures for fast output code 144 */ 145 struct pdma dzpdma[NDZLINE]; 146 147 char dz_speeds[] = 148 { 0,020,021,022,023,024,0,025,026,027,030,032,034,036,0,0 }; 149 150 #ifndef PORTSELECTOR 151 #define ISPEED B300 152 #define IFLAGS (EVENP|ODDP|ECHO) 153 #else 154 #define ISPEED B4800 155 #define IFLAGS (EVENP|ODDP) 156 #endif 157 158 dzprobe(reg) 159 caddr_t reg; 160 { 161 register int br, cvec; 162 register struct device *dzaddr = (struct device *)reg; 163 164 #ifdef lint 165 br = 0; cvec = br; br = cvec; 166 dzrint(0); dzxint((struct tty *)0); 167 #endif 168 dzaddr->dzcsr = DZ_TIE|DZ_MSE|DZ_32; 169 if (dzaddr->dzcsr & DZ_32) 170 dzaddr->dzlnen = 1; 171 else 172 dzaddr->dztcr = 1; /* enable any line */ 173 DELAY(100000); 174 dzaddr->dzcsr = DZ_CLR|DZ_32; /* reset everything */ 175 if (cvec && cvec != 0x200) 176 cvec -= 4; 177 return (1); 178 } 179 180 dzattach(ui) 181 register struct uba_device *ui; 182 { 183 register struct pdma *pdp = &dzpdma[ui->ui_unit*8]; 184 register struct tty *tp = &dz_tty[ui->ui_unit*8]; 185 register int cntr; 186 extern dzscan(); 187 188 for (cntr = 0; cntr < 8; cntr++) { 189 pdp->p_addr = (struct device *)ui->ui_addr; 190 pdp->p_arg = (int)tp; 191 pdp->p_fcn = dzxint; 192 pdp++, tp++; 193 } 194 dzsoftCAR[ui->ui_unit] = ui->ui_flags; 195 if (dz_timer == 0) { 196 dz_timer++; 197 timeout(dzscan, (caddr_t)0, hz); 198 } 199 } 200 201 /*ARGSUSED*/ 202 dzopen(dev, flag) 203 dev_t dev; 204 { 205 register struct tty *tp; 206 register int unit; 207 208 unit = minor(dev); 209 if (unit >= dz_cnt || dzpdma[unit].p_addr == 0) { 210 u.u_error = ENXIO; 211 return; 212 } 213 tp = &dz_tty[unit]; 214 tp->t_addr = (caddr_t)&dzpdma[unit]; 215 tp->t_oproc = dzstart; 216 tp->t_state |= TS_WOPEN; 217 if ((tp->t_state & TS_ISOPEN) == 0) { 218 ttychars(tp); 219 tp->t_ospeed = tp->t_ispeed = ISPEED; 220 tp->t_flags = IFLAGS; 221 /* tp->t_state |= TS_HUPCLS; */ 222 dzparam(unit); 223 } else if (tp->t_state&TS_XCLUDE && u.u_uid != 0) { 224 u.u_error = EBUSY; 225 return; 226 } 227 (void) dzmctl(dev, DZ_ON, DMSET); 228 (void) spl5(); 229 while ((tp->t_state & TS_CARR_ON) == 0) { 230 tp->t_state |= TS_WOPEN; 231 sleep((caddr_t)&tp->t_rawq, TTIPRI); 232 } 233 (void) spl0(); 234 (*linesw[tp->t_line].l_open)(dev, tp); 235 } 236 237 /*ARGSUSED*/ 238 dzclose(dev, flag) 239 dev_t dev; 240 { 241 register struct tty *tp; 242 register int unit; 243 register struct device *dzaddr; 244 int dz; 245 246 unit = minor(dev); 247 dz = unit >> 3; 248 tp = &dz_tty[unit]; 249 (*linesw[tp->t_line].l_close)(tp); 250 dzaddr = dzpdma[unit].p_addr; 251 if (dzaddr->dzcsr&DZ_32) 252 (void) dzmctl(dev, DZ_BRK, DMBIC); 253 else 254 dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07))); 255 if ((tp->t_state&TS_HUPCLS) || (tp->t_state&TS_ISOPEN) == 0) 256 (void) dzmctl(dev, DZ_OFF, DMSET); 257 ttyclose(tp); 258 } 259 260 dzread(dev) 261 dev_t dev; 262 { 263 register struct tty *tp; 264 265 tp = &dz_tty[minor(dev)]; 266 (*linesw[tp->t_line].l_read)(tp); 267 } 268 269 dzwrite(dev) 270 dev_t dev; 271 { 272 register struct tty *tp; 273 274 tp = &dz_tty[minor(dev)]; 275 (*linesw[tp->t_line].l_write)(tp); 276 } 277 278 /*ARGSUSED*/ 279 dzrint(dz) 280 int dz; 281 { 282 register struct tty *tp; 283 register int c; 284 register struct device *dzaddr; 285 register struct tty *tp0; 286 register int unit; 287 int overrun = 0; 288 289 if ((dzact & (1<<dz)) == 0) 290 return; 291 unit = dz * 8; 292 dzaddr = dzpdma[unit].p_addr; 293 tp0 = &dz_tty[unit]; 294 dzaddr->dzcsr &= ~(DZ_RIE|DZ_MIE); /* the manual says this song */ 295 dzaddr->dzcsr |= DZ_RIE|DZ_MIE; /* and dance is necessary */ 296 while (dzaddr->dzcsr & DZ_MSC) { /* DZ32 modem change interrupt */ 297 c = dzaddr->dzmtsr; 298 tp = tp0 + (c&7); 299 if (tp >= &dz_tty[dz_cnt]) 300 break; 301 dzaddr->dzlcs = c&7; /* get status of modem lines */ 302 dzwait(dzaddr); /* wait for them */ 303 if (c & DZ_CD) /* carrier status change? */ 304 if (dzaddr->dzlcs & DZ_CD) { /* carrier up? */ 305 if ((tp->t_state&TS_CARR_ON) == 0) { 306 wakeup((caddr_t)&tp->t_rawq); 307 tp->t_state |= TS_CARR_ON; 308 } 309 } else { /* no carrier */ 310 if (tp->t_state&TS_CARR_ON) { 311 gsignal(tp->t_pgrp, SIGHUP); 312 gsignal(tp->t_pgrp, SIGCONT); 313 dzaddr->dzlcs = DZ_ACK|(c&7); 314 flushtty(tp, FREAD|FWRITE); 315 } 316 tp->t_state &= ~TS_CARR_ON; 317 } 318 } 319 while ((c = dzaddr->dzrbuf) < 0) { /* char present */ 320 tp = tp0 + ((c>>8)&07); 321 if (tp >= &dz_tty[dz_cnt]) 322 continue; 323 if ((tp->t_state & TS_ISOPEN) == 0) { 324 wakeup((caddr_t)&tp->t_rawq); 325 #ifdef PORTSELECTOR 326 if ((tp->t_state&TS_WOPEN) == 0) 327 #endif 328 continue; 329 } 330 if (c&DZ_FE) 331 if (tp->t_flags & RAW) 332 c = 0; 333 else 334 c = tun.t_intrc; 335 if (c&DZ_DO && overrun == 0) { 336 /* printf("dz%d,%d: silo overflow\n", dz, (c>>8)&7); */ 337 overrun = 1; 338 } 339 if (c&DZ_PE) 340 if (((tp->t_flags & (EVENP|ODDP)) == EVENP) 341 || ((tp->t_flags & (EVENP|ODDP)) == ODDP)) 342 continue; 343 #if NBK > 0 344 if (tp->t_line == NETLDISC) { 345 c &= 0177; 346 BKINPUT(c, tp); 347 } else 348 #endif 349 (*linesw[tp->t_line].l_rint)(c, tp); 350 } 351 } 352 353 /*ARGSUSED*/ 354 dzioctl(dev, cmd, addr, flag) 355 dev_t dev; 356 caddr_t addr; 357 { 358 register struct tty *tp; 359 register int unit = minor(dev); 360 register int dz = unit >> 3; 361 register struct device *dzaddr; 362 int temp; 363 364 tp = &dz_tty[unit]; 365 cmd = (*linesw[tp->t_line].l_ioctl)(tp, cmd, addr); 366 if (cmd == 0) 367 return; 368 if (ttioctl(tp, cmd, addr, flag)) { 369 if (cmd==TIOCSETP || cmd==TIOCSETN) 370 dzparam(unit); 371 } else switch(cmd) { 372 373 case TIOCSBRK: 374 dzaddr = ((struct pdma *)(tp->t_addr))->p_addr; 375 if (dzaddr->dzcsr&DZ_32) 376 (void) dzmctl(dev, DZ_BRK, DMBIS); 377 else 378 dzaddr->dzbrk = (dz_brk[dz] |= 1 << (unit&07)); 379 break; 380 case TIOCCBRK: 381 dzaddr = ((struct pdma *)(tp->t_addr))->p_addr; 382 if (dzaddr->dzcsr&DZ_32) 383 (void) dzmctl(dev, DZ_BRK, DMBIC); 384 else 385 dzaddr->dzbrk = (dz_brk[dz] &= ~(1 << (unit&07))); 386 break; 387 case TIOCSDTR: 388 (void) dzmctl(dev, DZ_DTR|DZ_RTS, DMBIS); 389 break; 390 case TIOCCDTR: 391 (void) dzmctl(dev, DZ_DTR|DZ_RTS, DMBIC); 392 break; 393 case TIOCMSET: 394 if (copyin(addr, (caddr_t) &temp, sizeof(temp))) 395 u.u_error = EFAULT; 396 else 397 (void) dzmctl(dev, dmtodz(temp), DMSET); 398 break; 399 case TIOCMBIS: 400 if (copyin(addr, (caddr_t) &temp, sizeof(temp))) 401 u.u_error = EFAULT; 402 else 403 (void) dzmctl(dev, dmtodz(temp), DMBIS); 404 break; 405 case TIOCMBIC: 406 if (copyin(addr, (caddr_t) &temp, sizeof(temp))) 407 u.u_error = EFAULT; 408 else 409 (void) dzmctl(dev, dmtodz(temp), DMBIC); 410 break; 411 case TIOCMGET: 412 temp = dztodm(dzmctl(dev, 0, DMGET)); 413 if (copyout((caddr_t) &temp, addr, sizeof(temp))) 414 u.u_error = EFAULT; 415 break; 416 default: 417 u.u_error = ENOTTY; 418 } 419 } 420 421 dmtodz(bits) 422 register int bits; 423 { 424 register int b; 425 426 b = (bits >>1) & 0370; 427 if (bits & DML_ST) b |= DZ_ST; 428 if (bits & DML_RTS) b |= DZ_RTS; 429 if (bits & DML_DTR) b |= DZ_DTR; 430 if (bits & DML_LE) b |= DZ_LE; 431 return(b); 432 } 433 434 dztodm(bits) 435 register int bits; 436 { 437 register int b; 438 439 b = (bits << 1) & 0360; 440 if (bits & DZ_DSR) b |= DML_DSR; 441 if (bits & DZ_DTR) b |= DML_DTR; 442 if (bits & DZ_ST) b |= DML_ST; 443 if (bits & DZ_RTS) b |= DML_RTS; 444 return(b); 445 } 446 447 dzparam(unit) 448 register int unit; 449 { 450 register struct tty *tp; 451 register struct device *dzaddr; 452 register int lpr; 453 454 tp = &dz_tty[unit]; 455 dzaddr = dzpdma[unit].p_addr; 456 dzaddr->dzcsr = DZ_IEN; 457 dzact |= (1<<(unit>>3)); 458 if (tp->t_ispeed == 0) { 459 (void) dzmctl(unit, DZ_OFF, DMSET); /* hang up line */ 460 return; 461 } 462 lpr = (dz_speeds[tp->t_ispeed]<<8) | (unit & 07); 463 if ((tp->t_local&LLITOUT) || (tp->t_flags&RAW)) 464 lpr |= BITS8; 465 else 466 lpr |= (BITS7|PENABLE); 467 if ((tp->t_flags & EVENP) == 0) 468 lpr |= OPAR; 469 if (tp->t_ispeed == B110) 470 lpr |= TWOSB; 471 dzaddr->dzlpr = lpr; 472 } 473 474 dzxint(tp) 475 register struct tty *tp; 476 { 477 register struct pdma *dp; 478 register s, dz, unit; 479 480 s = spl5(); /* block pdma interrupts */ 481 dp = (struct pdma *)tp->t_addr; 482 tp->t_state &= ~TS_BUSY; 483 if (tp->t_state & TS_FLUSH) 484 tp->t_state &= ~TS_FLUSH; 485 else { 486 ndflush(&tp->t_outq, dp->p_mem-tp->t_outq.c_cf); 487 dp->p_end = dp->p_mem = tp->t_outq.c_cf; 488 } 489 if (tp->t_line) 490 (*linesw[tp->t_line].l_start)(tp); 491 else 492 dzstart(tp); 493 dz = minor(tp->t_dev) >> 3; 494 unit = minor(tp->t_dev) & 7; 495 if (tp->t_outq.c_cc == 0 || (tp->t_state&TS_BUSY)==0) 496 if (dp->p_addr->dzcsr & DZ_32) 497 dp->p_addr->dzlnen = (dz_lnen[dz] &= ~(1<<unit)); 498 else 499 dp->p_addr->dztcr &= ~(1<<unit); 500 splx(s); 501 } 502 503 dzstart(tp) 504 register struct tty *tp; 505 { 506 register struct pdma *dp; 507 register struct device *dzaddr; 508 register int cc; 509 int s, dz, unit; 510 511 dp = (struct pdma *)tp->t_addr; 512 dzaddr = dp->p_addr; 513 s = spl5(); 514 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 515 goto out; 516 if (tp->t_outq.c_cc <= TTLOWAT(tp)) { 517 if (tp->t_state&TS_ASLEEP) { 518 tp->t_state &= ~TS_ASLEEP; 519 wakeup((caddr_t)&tp->t_outq); 520 } 521 if (tp->t_wsel) { 522 selwakeup(tp->t_wsel, tp->t_state & TS_WCOLL); 523 tp->t_wsel = 0; 524 tp->t_state &= ~TS_WCOLL; 525 } 526 } 527 if (tp->t_outq.c_cc == 0) 528 goto out; 529 if ((tp->t_flags&RAW) || (tp->t_local&LLITOUT)) 530 cc = ndqb(&tp->t_outq, 0); 531 else { 532 cc = ndqb(&tp->t_outq, 0200); 533 if (cc == 0) { 534 cc = getc(&tp->t_outq); 535 timeout(ttrstrt, (caddr_t)tp, (cc&0x7f) + 6); 536 tp->t_state |= TS_TIMEOUT; 537 goto out; 538 } 539 } 540 tp->t_state |= TS_BUSY; 541 dp->p_end = dp->p_mem = tp->t_outq.c_cf; 542 dp->p_end += cc; 543 dz = minor(tp->t_dev) >> 3; 544 unit = minor(tp->t_dev) & 7; 545 if (dzaddr->dzcsr & DZ_32) 546 dzaddr->dzlnen = (dz_lnen[dz] |= (1<<unit)); 547 else 548 dzaddr->dztcr |= (1<<unit); 549 out: 550 splx(s); 551 } 552 553 /* 554 * Stop output on a line. 555 */ 556 /*ARGSUSED*/ 557 dzstop(tp, flag) 558 register struct tty *tp; 559 { 560 register struct pdma *dp; 561 register int s; 562 563 dp = (struct pdma *)tp->t_addr; 564 s = spl5(); 565 if (tp->t_state & TS_BUSY) { 566 dp->p_end = dp->p_mem; 567 if ((tp->t_state&TS_TTSTOP)==0) 568 tp->t_state |= TS_FLUSH; 569 } 570 splx(s); 571 } 572 573 dzmctl(dev, bits, how) 574 dev_t dev; 575 int bits, how; 576 { 577 register struct device *dzaddr; 578 register int unit, mbits; 579 int b, s; 580 581 unit = minor(dev); 582 b = 1<<(unit&7); 583 dzaddr = dzpdma[unit].p_addr; 584 s = spl5(); 585 if (dzaddr->dzcsr & DZ_32) { 586 dzwait(dzaddr) 587 DELAY(100); /* IS 100 TOO MUCH? */ 588 dzaddr->dzlcs = unit&7; 589 DELAY(100); 590 dzwait(dzaddr) 591 DELAY(100); 592 mbits = dzaddr->dzlcs; 593 mbits &= 0177770; 594 } else { 595 mbits = (dzaddr->dzdtr & b) ? DZ_DTR : 0; 596 mbits |= (dzaddr->dzmsr & b) ? DZ_CD : 0; 597 mbits |= (dzaddr->dztbuf & b) ? DZ_RI : 0; 598 } 599 switch (how) { 600 case DMSET: 601 mbits = bits; 602 break; 603 604 case DMBIS: 605 mbits |= bits; 606 break; 607 608 case DMBIC: 609 mbits &= ~bits; 610 break; 611 612 case DMGET: 613 (void) splx(s); 614 return(mbits); 615 } 616 if (dzaddr->dzcsr & DZ_32) { 617 mbits |= DZ_ACK|(unit&7); 618 dzaddr->dzlcs = mbits; 619 } else { 620 if (mbits & DZ_DTR) 621 dzaddr->dzdtr |= b; 622 else 623 dzaddr->dzdtr &= ~b; 624 } 625 (void) splx(s); 626 return(mbits); 627 } 628 629 dzscan() 630 { 631 register i; 632 register struct device *dzaddr; 633 register bit; 634 register struct tty *tp; 635 register car; 636 637 for (i = 0; i < dz_cnt ; i++) { 638 dzaddr = dzpdma[i].p_addr; 639 if (dzaddr == 0) 640 continue; 641 tp = &dz_tty[i]; 642 bit = 1<<(i&07); 643 car = 0; 644 if (dzsoftCAR[i>>3]&bit) 645 car = 1; 646 else if (dzaddr->dzcsr & DZ_32) { 647 dzaddr->dzlcs = i&07; 648 dzwait(dzaddr); 649 car = dzaddr->dzlcs & DZ_CD; 650 } else 651 car = dzaddr->dzmsr&bit; 652 if (car) { 653 /* carrier present */ 654 if ((tp->t_state & TS_CARR_ON) == 0) { 655 wakeup((caddr_t)&tp->t_rawq); 656 tp->t_state |= TS_CARR_ON; 657 } 658 } else { 659 if ((tp->t_state&TS_CARR_ON) && 660 (tp->t_local&LNOHANG)==0) { 661 /* carrier lost */ 662 if (tp->t_state&TS_ISOPEN) { 663 gsignal(tp->t_pgrp, SIGHUP); 664 gsignal(tp->t_pgrp, SIGCONT); 665 dzaddr->dzdtr &= ~bit; 666 flushtty(tp, FREAD|FWRITE); 667 } 668 tp->t_state &= ~TS_CARR_ON; 669 } 670 } 671 } 672 timeout(dzscan, (caddr_t)0, 2*hz); 673 } 674 675 dztimer() 676 { 677 int dz; 678 679 for (dz = 0; dz < NDZ; dz++) 680 dzrint(dz); 681 } 682 683 /* 684 * Reset state of driver if UBA reset was necessary. 685 * Reset parameters and restart transmission on open lines. 686 */ 687 dzreset(uban) 688 int uban; 689 { 690 register int unit; 691 register struct tty *tp; 692 register struct uba_device *ui; 693 694 for (unit = 0; unit < NDZLINE; unit++) { 695 ui = dzinfo[unit >> 3]; 696 if (ui == 0 || ui->ui_ubanum != uban || ui->ui_alive == 0) 697 continue; 698 if (unit%8 == 0) 699 printf(" dz%d", unit>>3); 700 tp = &dz_tty[unit]; 701 if (tp->t_state & (TS_ISOPEN|TS_WOPEN)) { 702 dzparam(unit); 703 (void) dzmctl(unit, DZ_ON, DMSET); 704 tp->t_state &= ~TS_BUSY; 705 dzstart(tp); 706 } 707 } 708 dztimer(); 709 } 710 #endif 711