xref: /original-bsd/sys/vax/uba/dzreg.h (revision fbb2a877)
1 /*
2  * Copyright (c) 1982, 1986 Regents of the University of California.
3  * All rights reserved.  The Berkeley software License Agreement
4  * specifies the terms and conditions for redistribution.
5  *
6  *	@(#)dzreg.h	7.1 (Berkeley) 06/05/86
7  */
8 
9 /*
10  * DZ-11/DZ-32 Registers and bits.
11  */
12 struct dzdevice {
13 	short dzcsr;
14 	short dzrbuf;
15 	union {
16 		struct {
17 			char	dztcr0;
18 			char	dzdtr0;
19 			char	dztbuf0;
20 			char	dzbrk0;
21 		} dz11;
22 		struct {
23 			short	dzlcs0;
24 			char	dztbuf0;
25 			char	dzlnen0;
26 		} dz32;
27 	} dzun;
28 };
29 
30 #define dzlpr	dzrbuf
31 #define dzmsr	dzun.dz11.dzbrk0
32 #define dztcr	dzun.dz11.dztcr0
33 #define dzdtr	dzun.dz11.dzdtr0
34 #define dztbuf	dzun.dz11.dztbuf0
35 #define dzlcs	dzun.dz32.dzlcs0
36 #define	dzbrk	dzmsr
37 #define dzlnen	dzun.dz32.dzlnen0
38 #define dzmtsr	dzun.dz32.dztbuf0
39 
40 /* bits in dzlpr */
41 #define	BITS7	0020
42 #define	BITS8	0030
43 #define	TWOSB	0040
44 #define	PENABLE	0100
45 #define	OPAR	0200
46 
47 /* bits in dzrbuf */
48 #define	DZ_PE	010000
49 #define	DZ_FE	020000
50 #define	DZ_DO	040000
51 
52 /* bits in dzcsr */
53 #define	DZ_32	000001		/* DZ32 mode */
54 #define	DZ_MIE	000002		/* Modem Interrupt Enable */
55 #define	DZ_CLR	000020		/* Reset dz */
56 #define	DZ_MSE	000040		/* Master Scan Enable */
57 #define	DZ_RIE	000100		/* Receiver Interrupt Enable */
58 #define DZ_MSC	004000		/* Modem Status Change */
59 #define	DZ_SAE	010000		/* Silo Alarm Enable */
60 #define	DZ_TIE	040000		/* Transmit Interrupt Enable */
61 #define	DZ_IEN	(DZ_32|DZ_MIE|DZ_MSE|DZ_RIE|DZ_TIE)
62 
63 /* flags for modem-control */
64 #define	DZ_ON	DZ_DTR
65 #define	DZ_OFF	0
66 
67 /* bits in dzlcs */
68 #define DZ_ACK	0100000		/* ACK bit in dzlcs */
69 #define DZ_RTS	0010000		/* Request To Send */
70 #define	DZ_ST	0004000		/* Secondary Transmit */
71 #define	DZ_BRK	0002000		/* Break */
72 #define DZ_DTR	0001000		/* Data Terminal Ready */
73 #define	DZ_LE	0000400		/* Line Enable */
74 #define	DZ_DSR	0000200		/* Data Set Ready */
75 #define	DZ_RI	0000100		/* Ring Indicate */
76 #define DZ_CD	0000040		/* Carrier Detect */
77 #define	DZ_CTS	0000020		/* Clear To Send */
78 #define	DZ_SR	0000010		/* Secondary Receive */
79 
80 /* bits in dm lsr, copied from dmreg.h */
81 #define	DML_DSR		0000400		/* data set ready, not a real DM bit */
82 #define	DML_RNG		0000200		/* ring */
83 #define	DML_CAR		0000100		/* carrier detect */
84 #define	DML_CTS		0000040		/* clear to send */
85 #define	DML_SR		0000020		/* secondary receive */
86 #define	DML_ST		0000010		/* secondary transmit */
87 #define	DML_RTS		0000004		/* request to send */
88 #define	DML_DTR		0000002		/* data terminal ready */
89 #define	DML_LE		0000001		/* line enable */
90