1 /* 2 * Copyright (c) 1982, 1986 Regents of the University of California. 3 * All rights reserved. The Berkeley software License Agreement 4 * specifies the terms and conditions for redistribution. 5 * 6 * @(#)psreg.h 7.2 (Berkeley) 12/22/87 7 */ 8 9 10 /* 11 * The Real Nitty Gritty Device Registers 12 */ 13 14 struct psdevice { 15 short int ps_data; /* data register */ 16 short int ps_addr; /* address register */ 17 short int ps_wcount; /* word count register */ 18 short int ps_busaddr; /* unibus address register */ 19 short int ps_iostat; /* io status register */ 20 }; 21 22 /* 23 * Possible ioctl's 24 */ 25 #define PSIOAUTOREFRESH _IO('p', 0) /* auto refresh */ 26 #define PSIOSINGLEREFRESH _IO('p', 1) /* single refresh */ 27 #define PSIOAUTOMAP _IO('p', 2) /* auto map */ 28 #define PSIOSINGLEMAP _IO('p', 3) /* single map */ 29 #define PSIODOUBLEBUFFER _IO('p', 4) /* double buffer */ 30 #define PSIOSINGLEBUFFER _IO('p', 5) /* single buffer */ 31 #define PSIOWAITREFRESH _IO('p', 6) /* await refresh */ 32 #define PSIOWAITMAP _IO('p', 7) /* await map */ 33 #define PSIOWAITHIT _IO('p', 8) /* await hit */ 34 #define PSIOSTOPREFRESH _IO('p', 9) /* stop refresh */ 35 #define PSIOSTOPMAP _IO('p',10) /* stop map */ 36 #define PSIOGETADDR _IOR('p',11, int) /* get Unibus address */ 37 #define PSIOTIMEREFRESH _IO('p',12) /* time refresh */ 38 39 /* 40 * Picture system io status register bits 41 */ 42 43 #define DIOREADY 0100000 44 #define PSAHOLD 040000 45 #define PSRESET 020000 46 #define DIORESET 010000 47 #define DMARESET 04000 48 #define PSIE 0400 49 #define DMAREADY 0200 50 #define DMAIE 0100 51 #define PASSIVE 010 52 #define DMAIN 04 53 #define NEXEM 02 54 #define GO 01 55 56 /* 57 * Picture system memory mapping control registers: SCB 0177400-0177410 58 */ 59 60 #define EXMMR_DMA 0177400 61 #define EXMMR_DIO 0177404 62 #define EXMMR_RC 0177405 63 #define EXMMR_MAPOUT 0177406 64 #define EXMMR_MAPIN 0177407 65 #define EXMSR 0177410 66 67 /* 68 * Extended memory status register bits 69 */ 70 71 #define DBERROR 0100000 72 #define SBERROR 040000 73 #define MEMREADY 0200 74 #define DBIE 0100 75 #define MMENBL 02 76 #define INITMEM 01 77 78 /* 79 * Size of extended memory 80 */ 81 82 #define NEXMPAGES (256*2) 83 #define WORDSPERPAGE (256) 84 85 /* 86 * MAP picture processor registers: SCB 0177750-0177753 87 */ 88 89 #define MAOL 0177750 90 #define MAOA 0177751 91 #define MAIA 0177752 92 #define MASR 0177753 93 #define MAMSR 0177754 94 95 /* 96 * MAP status register bits 97 */ 98 99 #define PPDONE 0100000 100 #define FIFOFULL 040000 101 #define FIFOEMPTY 020000 102 #define HIT 010000 103 #define IB 04000 104 #define TAKE 02000 105 #define MMODE 01400 106 #define MOSTOPPED 0200 107 #define IOUT 0100 108 #define MAO 040 109 #define MAI 020 110 #define HIT_HOLD 010 111 #define RSR_HOLD 04 112 #define VEC_HOLD 02 113 #define MAP_RESET 01 114 115 /* 116 * Refresh controller registers: SCB 0177730-0177737 117 */ 118 119 #define RFCSN 0177730 120 #define RFSN 0177731 121 #define RFAWA 0177732 122 #define RFAWL 0177733 123 #define RFAIA 0177734 124 #define RFASA 0177735 125 #define RFAIL 0177736 126 #define RFSR 0177737 127 128 /* 129 * Refresh controller status register bits 130 */ 131 132 #define RFSTOPPED 0100000 133 #define RFHOLD 040000 134 #define RFSTART 020000 135 #define AUTOREF 010000 136 #define RFBLANK 04000 137 #define RIGHT 02000 138 #define LGFIFO_FULL 01000 139 #define NOT_EXEC 0200 140 #define SKIPSEG 0100 141 #define WRITEBACK 040 142 #define SEARCH 020 143 #define MATCH_HOLD 010 144 #define MATCH_DEC 04 145 #define SEARCH_MODE 03 146 147 /* 148 * Interrupt control 149 */ 150 151 #define RTCREQ 0177760 152 #define RTCIE 0177761 153 #define SYSREQ 0177762 154 #define SYSIE 0177763 155 #define DEVREQ 0177764 156 #define DEVIE 0177765 157 158 /* 159 * System interrupt request bits 160 */ 161 162 #define LPEN_REQ 0200 163 #define MATCH_REQ 0100 164 #define WBSTOP_REQ 040 165 #define RFSTOP_REQ 020 166 #define MOSTOP_REQ 010 167 #define JUMP_REQ 04 168 #define HIT_REQ 02 169 #define HALT_REQ 01 170 171 /* 172 * Real-Time Clock registers 173 */ 174 175 #define RTCCNT 0177744 176 #define RTCSR 0177745 177 178 /* 179 * Real-Time Clock status register bits 180 */ 181 182 #define HZ120 040 183 #define EXT 020 184 #define SYNC 010 185 #define EXTSEL2 04 186 #define EXTSEL1 02 187 #define RUN 01 188 189 /* 190 * Control dials a/d registers 191 */ 192 193 #define ADDR0 0177500 194 #define ADDR1 0177501 195 #define ADDR2 0177502 196 #define ADDR3 0177503 197 #define ADDR4 0177504 198 #define ADDR5 0177505 199 #define ADDR6 0177506 200 #define ADDR7 0177507 201 202 /* 203 * Function switches and lights 204 */ 205 206 #define FSWR 0177626 207 #define FSLR 0177627 208