1 /* psreg.h 4.2 82/08/01 */ 2 3 4 /* 5 * The Real Nitty Gritty Device Registers 6 */ 7 8 struct psdevice { 9 short int ps_data; /* data register */ 10 short int ps_addr; /* address register */ 11 short int ps_wcount; /* word count register */ 12 short int ps_busaddr; /* unibus address register */ 13 short int ps_iostat; /* io status register */ 14 }; 15 16 /* 17 * Possible ioctl's 18 */ 19 #define PSIOAUTOREFRESH _IO(p, 0) /* auto refresh */ 20 #define PSIOSINGLEREFRESH _IO(p, 1) /* single refresh */ 21 #define PSIOAUTOMAP _IO(p, 2) /* auto map */ 22 #define PSIOSINGLEMAP _IO(p, 3) /* single map */ 23 #define PSIODOUBLEBUFFER _IO(p, 4) /* double buffer */ 24 #define PSIOSINGLEBUFFER _IO(p, 5) /* single buffer */ 25 #define PSIOWAITREFRESH _IO(p, 6) /* await refresh */ 26 #define PSIOWAITMAP _IO(p, 7) /* await map */ 27 #define PSIOWAITHIT _IO(p, 8) /* await hit */ 28 #define PSIOSTOPREFRESH _IO(p, 9) /* stop refresh */ 29 #define PSIOSTOPMAP _IO(p,10) /* stop map */ 30 #define PSIOGETADDR _IOR(p,11, int) /* get Unibus address */ 31 32 /* 33 * Picture system io status register bits 34 */ 35 36 #define DIOREADY 0100000 37 #define PSAHOLD 040000 38 #define PSRESET 020000 39 #define DIORESET 010000 40 #define DMARESET 04000 41 #define PSIE 0400 42 #define DMAREADY 0200 43 #define DMAIE 0100 44 #define PASSIVE 010 45 #define DMAIN 04 46 #define NEXEM 02 47 #define GO 01 48 49 /* 50 * Picture system memory mapping control registers: SCB 0177400-0177410 51 */ 52 53 #define EXMMR_DMA 0177400 54 #define EXMMR_DIO 0177404 55 #define EXMMR_RC 0177405 56 #define EXMMR_MAPOUT 0177406 57 #define EXMMR_MAPIN 0177407 58 #define EXMSR 0177410 59 60 /* 61 * Extended memory status register bits 62 */ 63 64 #define DBERROR 0100000 65 #define SBERROR 040000 66 #define MEMREADY 0200 67 #define DBIE 0100 68 #define MMENBL 02 69 #define INITMEM 01 70 71 /* 72 * Size of extended memory 73 */ 74 75 #define NEXMPAGES (256*2) 76 #define WORDSPERPAGE (256) 77 78 /* 79 * MAP picture processor registers: SCB 0177750-0177753 80 */ 81 82 #define MAOL 0177750 83 #define MAOA 0177751 84 #define MAIA 0177752 85 #define MASR 0177753 86 #define MAMSR 0177754 87 88 /* 89 * MAP status register bits 90 */ 91 92 #define PPDONE 0100000 93 #define FIFOFULL 040000 94 #define FIFOEMPTY 020000 95 #define HIT 010000 96 #define IB 04000 97 #define TAKE 02000 98 #define MMODE 01400 99 #define MOSTOPPED 0200 100 #define IOUT 0100 101 #define MAO 040 102 #define MAI 020 103 #define HIT_HOLD 010 104 #define RSR_HOLD 04 105 #define VEC_HOLD 02 106 #define MAP_RESET 01 107 108 /* 109 * Refresh controller registers: SCB 0177730-0177737 110 */ 111 112 #define RFCSN 0177730 113 #define RFSN 0177731 114 #define RFAWA 0177732 115 #define RFAWL 0177733 116 #define RFAIA 0177734 117 #define RFASA 0177735 118 #define RFAIL 0177736 119 #define RFSR 0177737 120 121 /* 122 * Refresh controller status register bits 123 */ 124 125 #define RFSTOPPED 0100000 126 #define RFHOLD 040000 127 #define RFSTART 020000 128 #define AUTOREF 010000 129 #define RFBLANK 04000 130 #define RIGHT 02000 131 #define LGFIFO_FULL 01000 132 #define NOT_EXEC 0200 133 #define SKIPSEG 0100 134 #define WRITEBACK 040 135 #define SEARCH 020 136 #define MATCH_HOLD 010 137 #define MATCH_DEC 04 138 #define SEARCH_MODE 03 139 140 /* 141 * Interrupt control 142 */ 143 144 #define RTCREQ 0177760 145 #define RTCIE 0177761 146 #define SYSREQ 0177762 147 #define SYSIE 0177763 148 #define DEVREQ 0177764 149 #define DEVIE 0177765 150 151 /* 152 * System interrupt request bits 153 */ 154 155 #define LPEN_REQ 0200 156 #define MATCH_REQ 0100 157 #define WBSTOP_REQ 040 158 #define RFSTOP_REQ 020 159 #define MOSTOP_REQ 010 160 #define JUMP_REQ 04 161 #define HIT_REQ 02 162 #define HALT_REQ 01 163 164 /* 165 * Real-Time Clock registers 166 */ 167 168 #define RTCCNT 0177744 169 #define RTCSR 0177745 170 171 /* 172 * Real-Time Clock status register bits 173 */ 174 175 #define HZ120 040 176 #define EXT 020 177 #define SYNC 010 178 #define EXTSEL2 04 179 #define EXTSEL1 02 180 #define RUN 01 181 182 /* 183 * Control dials a/d registers 184 */ 185 186 #define ADDR0 0177500 187 #define ADDR1 0177501 188 #define ADDR2 0177502 189 #define ADDR3 0177503 190 #define ADDR4 0177504 191 #define ADDR5 0177505 192 #define ADDR6 0177506 193 #define ADDR7 0177507 194 195 /* 196 * Function switches and lights 197 */ 198 199 #define FSWR 0177626 200 #define FSLR 0177627 201