xref: /original-bsd/sys/vax/uba/qduser.h (revision a05d0f95)
1*a05d0f95Sbostic /*-
2*a05d0f95Sbostic  * Copyright (c) 1982, 1986 The Regents of the University of California.
3*a05d0f95Sbostic  * All rights reserved.
4775e8ad9Smarc  *
5*a05d0f95Sbostic  * %sccs.include.redist.c%
6*a05d0f95Sbostic  *
7*a05d0f95Sbostic  *	@(#)qduser.h	7.1 (Berkeley) 05/09/91
8775e8ad9Smarc  */
9*a05d0f95Sbostic 
10b444c2e4Smarc /* derived from: @(#)qduser.h	6.1	(ULTRIX)	11/24/87       */
1100dcc46cSmarc /************************************************************************
1200dcc46cSmarc  *									*
1300dcc46cSmarc  *			Copyright (c) 1986 by				*
1400dcc46cSmarc  *		Digital Equipment Corporation, Maynard, MA		*
1500dcc46cSmarc  *			All rights reserved.				*
1600dcc46cSmarc  *									*
1700dcc46cSmarc  *   This software is furnished under a license and may be used and	*
1800dcc46cSmarc  *   copied  only  in accordance with the terms of such license and	*
1900dcc46cSmarc  *   with the  inclusion  of  the  above  copyright  notice.   This	*
2000dcc46cSmarc  *   software  or  any  other copies thereof may not be provided or	*
2100dcc46cSmarc  *   otherwise made available to any other person.  No title to and	*
2200dcc46cSmarc  *   ownership of the software is hereby transferred.			*
2300dcc46cSmarc  *									*
2400dcc46cSmarc  *   The information in this software is subject to change  without	*
2500dcc46cSmarc  *   notice  and should not be construed as a commitment by Digital	*
2600dcc46cSmarc  *   Equipment Corporation.						*
2700dcc46cSmarc  *									*
2800dcc46cSmarc  *   Digital assumes no responsibility for the use  or  reliability	*
2900dcc46cSmarc  *   of its software on equipment which is not supplied by Digital.	*
3000dcc46cSmarc  *									*
3100dcc46cSmarc  ************************************************************************/
3200dcc46cSmarc 
3300dcc46cSmarc /***************************************************************************
3400dcc46cSmarc *
3500dcc46cSmarc *	QDUSER...
3600dcc46cSmarc *	This file defines values shared between the driver and a client
3700dcc46cSmarc *
3800dcc46cSmarc ***************************************************************************/
3900dcc46cSmarc 
4000dcc46cSmarc /***************************************************************************
41b444c2e4Smarc *	revision history:
4200dcc46cSmarc ****************************************************************************
4300dcc46cSmarc *
4400dcc46cSmarc * 21 jul 86  ram    fixed define of CURSOR_MIN_Y
4500dcc46cSmarc * 25 nov 85  longo  added macro and bit defines for DMA error flags
4600dcc46cSmarc * 11 nov 85  longo  renamed _vs_eventqueue to "qdinput" struct
4700dcc46cSmarc * 23 oct 85  longo  added more defines to the DMA stuff
4800dcc46cSmarc * 17 oct 85  longo  changed "struct rgb" chars to be unsigned
4900dcc46cSmarc * 16 oct 85  longo  added new TABLET support definitions
5000dcc46cSmarc * 15 oct 85  longo  re-wrote DMA queue access macros
5100dcc46cSmarc * 08 oct 85  longo  added status flag manipulation macros to DMA stuff
5200dcc46cSmarc * 02 oct 85  longo  added support for color map write buffer loading
5300dcc46cSmarc * 26 sep 85  longo  removed adder sertup params from DMA request struct
5400dcc46cSmarc * 23 sep 85  longo  added DMA queue access macros
5500dcc46cSmarc * 30 aug 85  longo  fixed crock in "qdiobuf" struct compile-time sizing. Also
5600dcc46cSmarc *		    removed DMAcontrol struct from DMA buffer for field test
5700dcc46cSmarc * 26 aug 85  longo  put in conditional include of "qevent.h" for user prg's
5800dcc46cSmarc * 18 jul 85  longo  changed semantics so that head is tail and tail is head
5900dcc46cSmarc * 12 jul 85  longo  moved "mouse_report" struct and defs over to qd_data.c
6000dcc46cSmarc * 11 jul 85  longo  added device coordinate to gate array cursor coordinate
6100dcc46cSmarc *		    transformation macros
6200dcc46cSmarc * 03 jul 85  longo  changed kernel typdef's for data types to long-hand
6300dcc46cSmarc * 10 may 85  longo  created
6400dcc46cSmarc *
6500dcc46cSmarc ***************************************************************************/
6600dcc46cSmarc 
6700dcc46cSmarc #ifdef KERNEL
681c14281dSbostic #include "../uba/qevent.h"		/* include event struct defs */
6900dcc46cSmarc #else
701c14281dSbostic #include <vax/uba/qevent.h>
7100dcc46cSmarc #endif
7200dcc46cSmarc 
7300dcc46cSmarc /*---------------------
7400dcc46cSmarc * QDSS device map */
7500dcc46cSmarc 
7600dcc46cSmarc 	struct qdmap {			/* map of register blocks in QDSS */
7700dcc46cSmarc 
7800dcc46cSmarc 	    char *template;
7900dcc46cSmarc 	    char *adder;
8000dcc46cSmarc 	    char *dga;
8100dcc46cSmarc 	    char *duart;
8200dcc46cSmarc 	    char *memcsr;
8300dcc46cSmarc 	    char *red;
8400dcc46cSmarc 	    char *blue;
8500dcc46cSmarc 	    char *green;
8600dcc46cSmarc 	};
8700dcc46cSmarc 
8800dcc46cSmarc /*--------------------------------------------
8900dcc46cSmarc * DGA CSR bit definitions and register map */
9000dcc46cSmarc 
9100dcc46cSmarc #define DMADONE		0x8000		/* DMA done status */
9200dcc46cSmarc #define SET_DONE_FIFO	0x4000		/* set DMADONE when FIFO empty.. */
9300dcc46cSmarc 					/* ..AND count = 0 */
9400dcc46cSmarc 
9500dcc46cSmarc #define PTOB_ENB	0x0600		/* host-to-bitmap DMA xfer */
9600dcc46cSmarc #define BTOP_ENB	0x0400		/* bitmap-to-host DMA xfer */
9700dcc46cSmarc #define DL_ENB		0x0200		/* display list DMA xfer */
9800dcc46cSmarc #define HALT		0x0000		/* halt DGA */
9900dcc46cSmarc 
10000dcc46cSmarc #define BYTE_DMA	0x0100		/* byte/word DMA xfer */
10100dcc46cSmarc 
10200dcc46cSmarc #define DMA_ERR		0x0080		/* DMA error bits */
10300dcc46cSmarc #define PARITY_ERR	0x0040		/* memory parity error in DMA */
10400dcc46cSmarc #define BUS_ERR		0x0020		/* bus timeout error in DMA */
10500dcc46cSmarc 
10600dcc46cSmarc #define GLOBAL_IE	0x0004		/* global interrupt enable */
10700dcc46cSmarc #define DMA_IE		0x0002		/* DMA interrupt enable */
10800dcc46cSmarc #define CURS_ENB	0x0001		/* cursor enable */
10900dcc46cSmarc 
11000dcc46cSmarc /* QDSS memcsr bit definitions */
11100dcc46cSmarc 
11200dcc46cSmarc #define	UNBLANK			0x0020
11300dcc46cSmarc #define SYNC_ON			0x0008
11400dcc46cSmarc 
11500dcc46cSmarc 	struct dga {
11600dcc46cSmarc 
11700dcc46cSmarc 	    unsigned short csr;
11800dcc46cSmarc 	    unsigned short adrs_lo;	/* destination address of bitmap to */
11900dcc46cSmarc 	    unsigned short adrs_hi;	/*   host DMA */
12000dcc46cSmarc 	    unsigned short bytcnt_lo;	/* byte length of requested DMA */
12100dcc46cSmarc 	    unsigned short bytcnt_hi;	/* (WO = bytcnt) (RO = fifo count) */
12200dcc46cSmarc 	    unsigned short fifo;	/* FIFO register */
12300dcc46cSmarc 	    unsigned short x_cursor;	/* cursor position registers */
12400dcc46cSmarc 	    unsigned short y_cursor;
12500dcc46cSmarc 	    unsigned short ivr;		/* interrupt vector register */
12600dcc46cSmarc 	    unsigned short memadr;	/* memory base address register */
12700dcc46cSmarc 	};
12800dcc46cSmarc 
12900dcc46cSmarc /*-------------------------------------------------------------------------
13000dcc46cSmarc * macros to transform device coordinates to hardware cursor coordinates */
13100dcc46cSmarc 
13200dcc46cSmarc #define CURS_MIN_X 	232	/* device coordinate x = 0 */
13300dcc46cSmarc #define CURS_MIN_Y 	16	/* device coordinate y = 0 */
13400dcc46cSmarc 
13500dcc46cSmarc #define TRANX(x) ( -(((int)(x)+CURS_MIN_X) & ~0x0003) | \
13600dcc46cSmarc 		   (((int)(x)+CURS_MIN_X) & 0x0003) )
13700dcc46cSmarc 
13800dcc46cSmarc #define TRANY(y) ( -((y)+CURS_MIN_Y) )
13900dcc46cSmarc 
14000dcc46cSmarc /*********************************************************************
14100dcc46cSmarc *
14200dcc46cSmarc *	EVENT QUEUE DEFINITIONS
14300dcc46cSmarc *
14400dcc46cSmarc **********************************************************************
14500dcc46cSmarc * most of the event queue definitions are found in "qevent.h".  But a
14600dcc46cSmarc * few things not found there are here.  */
14700dcc46cSmarc 
14800dcc46cSmarc /* The event queue header */
14900dcc46cSmarc 
15000dcc46cSmarc typedef struct qdinput {
15100dcc46cSmarc 
15200dcc46cSmarc 	    struct _vs_eventqueue header;  /* event queue ring handling */
15300dcc46cSmarc 
15400dcc46cSmarc 	    /* for VS100 and QVSS compatability reasons, additions to this
15500dcc46cSmarc 	    *  structure must be made below this point.  */
15600dcc46cSmarc 
15700dcc46cSmarc 	    struct _vs_cursor curs_pos;	/* current mouse position */
15800dcc46cSmarc 	    struct _vs_box curs_box;	/* cursor reporting box */
15900dcc46cSmarc 
16000dcc46cSmarc 	};
16100dcc46cSmarc 
16200dcc46cSmarc /* vse_key field.  definitions for mouse buttons */
16300dcc46cSmarc 
16400dcc46cSmarc #define VSE_LEFT_BUTTON		0
16500dcc46cSmarc #define VSE_MIDDLE_BUTTON	1
16600dcc46cSmarc #define VSE_RIGHT_BUTTON	2
16700dcc46cSmarc 
16800dcc46cSmarc /* vse_key field.  definitions for mouse buttons */
16900dcc46cSmarc 
17000dcc46cSmarc #define VSE_T_LEFT_BUTTON	0
17100dcc46cSmarc #define VSE_T_FRONT_BUTTON	1
17200dcc46cSmarc #define VSE_T_RIGHT_BUTTON	2
17300dcc46cSmarc #define VSE_T_BACK_BUTTON	4
17400dcc46cSmarc 
17500dcc46cSmarc #define VSE_T_BARREL_BUTTON	VSE_T_LEFT_BUTTON
17600dcc46cSmarc #define VSE_T_TIP_BUTTON	VSE_T_FRONT_BUTTON
17700dcc46cSmarc 
17800dcc46cSmarc /*--------------------------------------------------------------------------
17900dcc46cSmarc *   These are the macros to be used for loading and extracting from the event
18000dcc46cSmarc * queue.  It is presumed that the macro user will only use the access macros
18100dcc46cSmarc * if the event queue is non-empty ( ISEMPTY(eq) == FALSE ), and that the
18200dcc46cSmarc * driver will only load the event queue after checking that it is not full
18300dcc46cSmarc * ( ISFULL(eq) == FALSE ).  ("eq" is a pointer to the event queue header.)
18400dcc46cSmarc *
18500dcc46cSmarc *   Before an event access session for a particular event, the macro users
18600dcc46cSmarc * must use the xxxBEGIN macro, and the xxxEND macro after an event is through
18700dcc46cSmarc * with.  As seen below, the xxxBEGIN and xxxEND macros maintain the event
18800dcc46cSmarc * queue access mechanism.
18900dcc46cSmarc *
19000dcc46cSmarc * First, the macros to be used by the event queue reader
19100dcc46cSmarc */
19200dcc46cSmarc 
19300dcc46cSmarc #define ISEMPTY(eq)	  ((eq)->header.head == (eq)->header.tail)
19400dcc46cSmarc #define GETBEGIN(eq)	  (&(eq)->header.events[(eq)->header.head])
19500dcc46cSmarc 
19600dcc46cSmarc #define GET_X(event)	  ((event)->vse_x)  	     /* get x position */
19700dcc46cSmarc #define GET_Y(event)	  ((event)->vse_y)  	     /* get y position */
19800dcc46cSmarc #define GET_TIME(event)	  ((event)->vse_time) 	     /* get time */
19900dcc46cSmarc #define GET_TYPE(event)	  ((event)->vse_type)	     /* get entry type */
20000dcc46cSmarc #define GET_KEY(event)	  ((event)->vse_key)  	     /* get keycode */
20100dcc46cSmarc #define GET_DIR(event)	  ((event)->vse_direction)     /* get direction */
20200dcc46cSmarc #define GET_DEVICE(event) ((event)->vse_device)        /* get device */
20300dcc46cSmarc 
20400dcc46cSmarc #define GETEND(eq)        (++(eq)->header.head >= (eq)->header.size ? \
20500dcc46cSmarc 			   (eq)->header.head = 0 : 0 )
20600dcc46cSmarc 
20700dcc46cSmarc /*------------------------------------------------
20800dcc46cSmarc * macros to be used by the event queue loader  */
20900dcc46cSmarc 
21000dcc46cSmarc 	/* ISFULL yields TRUE if queue is full */
21100dcc46cSmarc 
21200dcc46cSmarc #define ISFULL(eq)	((eq)->header.tail+1 == (eq)->header.head ||   \
21300dcc46cSmarc 			 ((eq)->header.tail+1 == (eq)->header.size &&  \
21400dcc46cSmarc 			  (eq)->header.head == 0))
21500dcc46cSmarc 
21600dcc46cSmarc 	/* get address of the billet for NEXT event */
21700dcc46cSmarc 
21800dcc46cSmarc #define PUTBEGIN(eq)	(&(eq)->header.events[(eq)->header.tail])
21900dcc46cSmarc 
22000dcc46cSmarc #define PUT_X(event, value)  	((event)->vse_x = value)    /* put X pos */
22100dcc46cSmarc #define PUT_Y(event, value)   	((event)->vse_y = value)    /* put Y pos */
22200dcc46cSmarc #define PUT_TIME(event, value)	((event)->vse_time = value)   /* put time */
22300dcc46cSmarc #define PUT_TYPE(event, value)	((event)->vse_type = value) /* put type */
22400dcc46cSmarc #define PUT_KEY(event, value)	((event)->vse_key = value) /* put input key */
22500dcc46cSmarc #define PUT_DIR(event, value)	((event)->vse_direction = value) /* put dir */
22600dcc46cSmarc #define PUT_DEVICE(event, value) ((event)->vse_device = value)   /* put dev */
22700dcc46cSmarc 
22800dcc46cSmarc #define PUTEND(eq)     (++(eq)->header.tail >= (eq)->header.size ?  \
22900dcc46cSmarc 			(eq)->header.tail = 0 : 0)
23000dcc46cSmarc 
23100dcc46cSmarc /******************************************************************
23200dcc46cSmarc *
23300dcc46cSmarc *	DMA I/O DEFINITIONS
23400dcc46cSmarc *
23500dcc46cSmarc ******************************************************************/
23600dcc46cSmarc 
23700dcc46cSmarc /*---------------------------------------------------------------------
23800dcc46cSmarc * The DMA request queue is implemented as a ring buffer of "DMAreq"
23900dcc46cSmarc   structures.  The queue is accessed using ring indices located in the
24000dcc46cSmarc   "DMAreq_header" structure.  Access is implemented using access macros
24100dcc46cSmarc   similar to the event queue access macros above.  */
24200dcc46cSmarc 
24300dcc46cSmarc 	struct DMAreq {
24400dcc46cSmarc 
24500dcc46cSmarc 	    short DMAtype;		/* DMA type code (for QDSS) */
24600dcc46cSmarc 	    short DMAdone;		/* DMA done parameter */
24700dcc46cSmarc 	    char  *bufp;		/* virtual adrs of buffer */
24800dcc46cSmarc 	    int   length;	        /* transfer buffer length */
24900dcc46cSmarc 	};
25000dcc46cSmarc 
25100dcc46cSmarc /* DMA type command codes */
25200dcc46cSmarc 
25300dcc46cSmarc #define DISPLIST	1	/* display list DMA */
25400dcc46cSmarc #define PTOB		2	/* 1 plane Qbus to bitmap DMA */
25500dcc46cSmarc #define BTOP		3	/* 1 plane bitmap to Qbus DMA */
25600dcc46cSmarc 
25700dcc46cSmarc /* DMA done notification code */
25800dcc46cSmarc 
25900dcc46cSmarc #define FIFO_EMPTY	0x01	/* DONE when FIFO becomes empty */
26000dcc46cSmarc #define COUNT_ZERO	0x02	/* DONE when count becomes zero */
26100dcc46cSmarc #define WORD_PACK	0x04    /* program the gate array for word packing */
26200dcc46cSmarc #define BYTE_PACK	0x08	/* program gate array for byte packing */
26300dcc46cSmarc #define REQUEST_DONE	0x100	/* clear when driver has processed request */
26400dcc46cSmarc #define HARD_ERROR	0x200   /* DMA hardware error occurred */
26500dcc46cSmarc 
26600dcc46cSmarc /* DMA request queue is a ring buffer of request structures */
26700dcc46cSmarc 
26800dcc46cSmarc 	struct DMAreq_header {
26900dcc46cSmarc 
27000dcc46cSmarc 	    int QBAreg;		    /* cookie Qbus map reg for this buffer */
27100dcc46cSmarc 	    short status;	    /* master DMA status word */
27200dcc46cSmarc 	    int shared_size;	    /* size of shared memory in bytes */
27300dcc46cSmarc 	    struct DMAreq *DMAreq;  /* start address of request queue */
27400dcc46cSmarc 	    int used;		    /* # of queue entries currently used */
27500dcc46cSmarc 	    int size;		    /* # of "DMAreq"'s in the request queue */
27600dcc46cSmarc 	    int oldest;		    /* index to oldest queue'd request */
27700dcc46cSmarc 	    int newest;		    /* index to newest queue'd request */
27800dcc46cSmarc 	};
27900dcc46cSmarc 
28000dcc46cSmarc /* bit definitions for DMAstatus word in DMAreq_header */
28100dcc46cSmarc 
28200dcc46cSmarc #define	DMA_ACTIVE	0x0004		/* DMA in progress */
28300dcc46cSmarc #define DMA_ERROR	0x0080		/* DMA hardware error */
28400dcc46cSmarc #define DMA_IGNORE	0x0002		/* flag to ignore this interrupt */
28500dcc46cSmarc 
28600dcc46cSmarc /*------------------------------------------
28700dcc46cSmarc * macros for DMA request queue fiddling  */
28800dcc46cSmarc 
28900dcc46cSmarc 	/* DMA status set/check macros */
29000dcc46cSmarc 
29100dcc46cSmarc #define DMA_SETACTIVE(header)   ((header)->status |= DMA_ACTIVE)
29200dcc46cSmarc #define DMA_CLRACTIVE(header)	((header)->status &= ~DMA_ACTIVE)
29300dcc46cSmarc #define DMA_ISACTIVE(header)    ((header)->status & DMA_ACTIVE)
29400dcc46cSmarc 
29500dcc46cSmarc #define DMA_SETERROR(header)    ((header)->status |= DMA_ERROR)
29600dcc46cSmarc #define DMA_CLRERROR(header)    ((header)->status &= ~DMA_ERROR)
29700dcc46cSmarc #define DMA_ISERROR(header)     ((header)->status & DMA_ERROR)
29800dcc46cSmarc 
29900dcc46cSmarc #define DMA_SETIGNORE(header)	((header)->status |= DMA_IGNORE)
30000dcc46cSmarc #define DMA_CLRIGNORE(header)   ((header)->status &= ~DMA_IGNORE)
30100dcc46cSmarc #define DMA_ISIGNORE(header)    ((header)->status & DMA_IGNORE)
30200dcc46cSmarc 
30300dcc46cSmarc 	/* yields TRUE if queue is empty (ISEMPTY) or full (ISFULL) */
30400dcc46cSmarc 
30500dcc46cSmarc #define DMA_ISEMPTY(header)	((header)->used == 0)
30600dcc46cSmarc #define DMA_ISFULL(header)	((header)->used >= (header)->size)
30700dcc46cSmarc 
30800dcc46cSmarc 	/* returns address of the billet for next (PUT)
30900dcc46cSmarc 	 * or oldest (GET) request */
31000dcc46cSmarc 
31100dcc46cSmarc #define DMA_PUTBEGIN(header)	(&(header)->DMAreq[(header)->newest])
31200dcc46cSmarc #define DMA_GETBEGIN(header)  	(&(header)->DMAreq[(header)->oldest])
31300dcc46cSmarc 
31400dcc46cSmarc 	/* does queue access pointer maintenance */
31500dcc46cSmarc 
31600dcc46cSmarc #define DMA_GETEND(header)      (++(header)->oldest >= (header)->size    \
31700dcc46cSmarc 				  ? (header)->oldest = 0 : 0);		 \
31800dcc46cSmarc 				--(header)->used;
31900dcc46cSmarc 
32000dcc46cSmarc #define DMA_PUTEND(header)     	(++(header)->newest >= (header)->size    \
32100dcc46cSmarc 				  ? (header)->newest = 0 : 0);		 \
32200dcc46cSmarc 				++(header)->used;
32300dcc46cSmarc 
32400dcc46cSmarc /******************************************************************
32500dcc46cSmarc *
32600dcc46cSmarc *	COLOR MAP WRITE BUFFER DEFINITIONS
32700dcc46cSmarc *
32800dcc46cSmarc ******************************************************************/
32900dcc46cSmarc 
33000dcc46cSmarc 	struct rgb {
33100dcc46cSmarc 
33200dcc46cSmarc 	    unsigned char offset;	/* color map address for load */
33300dcc46cSmarc 	    unsigned char red;		/* data for red map */
33400dcc46cSmarc 	    unsigned char green;	/* data for green map */
33500dcc46cSmarc 	    unsigned char blue;		/* data for blue map */
33600dcc46cSmarc 	};
33700dcc46cSmarc 
33800dcc46cSmarc 	struct color_buf {
33900dcc46cSmarc 
34000dcc46cSmarc 	    char status;		/* load request/service status */
34100dcc46cSmarc 	    short count;		/* number of entries to br loaded */
34200dcc46cSmarc 	    struct rgb rgb[256];
34300dcc46cSmarc 	};
34400dcc46cSmarc 
34500dcc46cSmarc #define LOAD_COLOR_MAP	0x0001
34600dcc46cSmarc 
34700dcc46cSmarc /******************************************************************
34800dcc46cSmarc *
34900dcc46cSmarc *	SCROLL ASSIST DEFINITIONS
35000dcc46cSmarc *
35100dcc46cSmarc ******************************************************************/
35200dcc46cSmarc 
35300dcc46cSmarc 	struct scroll {
35400dcc46cSmarc 
35500dcc46cSmarc 	    short status;
35600dcc46cSmarc 	    short viper_constant;
35700dcc46cSmarc 	    short y_scroll_constant;
35800dcc46cSmarc 	    short y_offset;
35900dcc46cSmarc 	    short x_index_pending;
36000dcc46cSmarc 	    short y_index_pending;
36100dcc46cSmarc 	};
36200dcc46cSmarc 
36300dcc46cSmarc #define LOAD_REGS	0x0001
36400dcc46cSmarc #define LOAD_INDEX	0x0002
36500dcc46cSmarc 
36600dcc46cSmarc /******************************************************************
36700dcc46cSmarc *
36800dcc46cSmarc *	MOUSE/TABLET/KBD PROGRAMMING DEFINITIONS
36900dcc46cSmarc *
37000dcc46cSmarc ******************************************************************/
37100dcc46cSmarc 
37200dcc46cSmarc /*-----------------------------------
37300dcc46cSmarc * LK201 programmming definitions  */
37400dcc46cSmarc 
37500dcc46cSmarc #define LK_UPDOWN 	0x86		/* bits for setting lk201 modes */
37600dcc46cSmarc #define LK_AUTODOWN 	0x82
37700dcc46cSmarc #define LK_DOWN 	0x80
37800dcc46cSmarc #define LK_DEFAULTS 	0xD3		/* reset (some) default settings */
37900dcc46cSmarc #define LK_AR_ENABLE 	0xE3		/* global auto repeat enable */
38000dcc46cSmarc #define LK_CL_ENABLE 	0x1B		/* keyclick enable */
38100dcc46cSmarc #define LK_KBD_ENABLE 	0x8B		/* keyboard enable */
38200dcc46cSmarc #define LK_BELL_ENABLE 	0x23		/* the bell */
38300dcc46cSmarc #define LK_RING_BELL 	0xA7		/* ring keyboard bell */
38400dcc46cSmarc 
38500dcc46cSmarc #define LK_LED_ENABLE 	0x13		/* light led */
38600dcc46cSmarc #define LK_LED_DISABLE 	0x11		/* turn off led */
38700dcc46cSmarc #define LED_1 		0x81		/* led bits */
38800dcc46cSmarc #define LED_2 		0x82
38900dcc46cSmarc #define LED_3 		0x84
39000dcc46cSmarc #define LED_4 		0x88
39100dcc46cSmarc #define LED_ALL 	0x8F
39200dcc46cSmarc #define LK_LED_HOLD	LED_4
39300dcc46cSmarc #define LK_LED_LOCK	LED_3
39400dcc46cSmarc #define LK_LED_COMPOSE	LED_2
39500dcc46cSmarc #define LK_LED_WAIT 	LED_1
39600dcc46cSmarc 
39700dcc46cSmarc #define LK_KDOWN_ERROR	0x3D		/* key down on powerup error */
39800dcc46cSmarc #define LK_POWER_ERROR 	0x3E		/* keyboard failure on powerup test */
39900dcc46cSmarc #define LK_OUTPUT_ERROR	0xB5		/* keystrokes lost during inhibit */
40000dcc46cSmarc #define LK_INPUT_ERROR 	0xB6		/* garbage command to keyboard */
40100dcc46cSmarc #define LK_LOWEST	0x56		/* lowest significant keycode */
40200dcc46cSmarc #define LK_DIV6_START	0xAD		/* start of div 6 */
40300dcc46cSmarc #define LK_DIV5_END	0xB2		/* end of div 5 */
40400dcc46cSmarc 
40500dcc46cSmarc #define LAST_PARAM	0x80		/* "no more params" bit */
40600dcc46cSmarc 
40700dcc46cSmarc 	struct prgkbd {
40800dcc46cSmarc 
40900dcc46cSmarc 	    short cmd;			/* LK201 command opcode */
41000dcc46cSmarc 	    short param1;		/* 1st cmd parameter (can be null) */
41100dcc46cSmarc 	    short param2;		/* 2nd cmd parameter (can be null) */
41200dcc46cSmarc 	};
41300dcc46cSmarc 
41400dcc46cSmarc /*-------------------------
41500dcc46cSmarc * "special" LK-201 keys */
41600dcc46cSmarc 
41700dcc46cSmarc #define SHIFT		174
41800dcc46cSmarc #define LOCK		176
41900dcc46cSmarc #define REPEAT		180
42000dcc46cSmarc #define CNTRL		175
42100dcc46cSmarc #define ALLUP		179
42200dcc46cSmarc 
42300dcc46cSmarc /*--------------------------------
42400dcc46cSmarc * cursor programming structure */
42500dcc46cSmarc 
42600dcc46cSmarc 	struct prg_cursor {
42700dcc46cSmarc 
42800dcc46cSmarc 	    unsigned short acc_factor;	/* cursor aceleration factor */
42900dcc46cSmarc 	    unsigned short threshold;	/* threshold to trigger acc at */
43000dcc46cSmarc 	};
43100dcc46cSmarc 
43200dcc46cSmarc /*---------------------
43300dcc46cSmarc * mouse definitions */
43400dcc46cSmarc 
43500dcc46cSmarc #define INC_STREAM_MODE	'R'		/* stream mode reports (55 hz) */
43600dcc46cSmarc #define PROMPT_MODE	'D'		/* report when prompted */
43700dcc46cSmarc #define REQUEST_POS	'P'		/* request position report */
43800dcc46cSmarc #define SELF_TEST	'T'		/* request self test */
43900dcc46cSmarc 
44000dcc46cSmarc #define MOUSE_ID	0x2		/* mouse ID in lo 4 bits */
44100dcc46cSmarc 
44200dcc46cSmarc #define START_FRAME	0x80		/* start of report frame bit */
44300dcc46cSmarc #define X_SIGN		0x10		/* position sign bits */
44400dcc46cSmarc #define Y_SIGN		0x08
44500dcc46cSmarc 
44600dcc46cSmarc #define RIGHT_BUTTON	0x01		/* mouse buttons */
44700dcc46cSmarc #define MIDDLE_BUTTON	0x02
44800dcc46cSmarc #define LEFT_BUTTON	0x04
44900dcc46cSmarc 
45000dcc46cSmarc 	/* mouse report structure definition */
45100dcc46cSmarc 
45200dcc46cSmarc 	struct mouse_report {
45300dcc46cSmarc 
45400dcc46cSmarc 	    char state;		/* buttons and sign bits */
45500dcc46cSmarc 	    short dx;		/* delta X since last change */
45600dcc46cSmarc 	    short dy;		/* delta Y since last change */
45700dcc46cSmarc 	    char bytcnt;	/* mouse report byte count */
45800dcc46cSmarc 	};
45900dcc46cSmarc 
46000dcc46cSmarc /*-----------------------------------------
46100dcc46cSmarc * tablet command/interface definitions  */
46200dcc46cSmarc 
46300dcc46cSmarc #define T_STREAM	'R'		/* continuous stream report mode */
46400dcc46cSmarc #define T_POINT	 	'D'		/* enter report-on-request mode */
46500dcc46cSmarc #define T_REQUEST	'P'		/* request position report */
46600dcc46cSmarc 
46700dcc46cSmarc #define T_BAUD		'B'		/* increase baud to 9600 from 4800 */
46800dcc46cSmarc #define T_RATE_55	'K'		/* report rate: 55/sec */
46900dcc46cSmarc #define T_RATE_72	'L'		/* report rate: 72/sec */
47000dcc46cSmarc #define T_RATE_120	'M'		/* report rate: 120/sec (9600 only) */
47100dcc46cSmarc 
47200dcc46cSmarc #define T_TEST		SELF_TEST	/* do self test */
47300dcc46cSmarc 
47400dcc46cSmarc #define TABLET_ID	0x4		/* tablet ID in lo 4 bits */
47500dcc46cSmarc 
47600dcc46cSmarc #define T_START_FRAME	0x80		/* start of report frame bit */
47700dcc46cSmarc #define T_PROXIMITY	0x01		/* state pointer in proximity */
47800dcc46cSmarc 
47900dcc46cSmarc #define T_LEFT_BUTTON	0x02		/* puck buttons */
48000dcc46cSmarc #define T_FRONT_BUTTON	0x04
48100dcc46cSmarc #define T_RIGHT_BUTTON	0x08
48200dcc46cSmarc #define T_BACK_BUTTON	0x10
48300dcc46cSmarc 
48400dcc46cSmarc #define T_BARREL_BUTTON T_LEFT_BUTTON		/* stylus buttons */
48500dcc46cSmarc #define T_TIP_BUTTON	T_FRONT_BUTTON
48600dcc46cSmarc 
487