1 /* uba.c 4.42 82/03/31 */ 2 3 #include "../h/param.h" 4 #include "../h/systm.h" 5 #include "../h/cpu.h" 6 #include "../h/map.h" 7 #include "../h/pte.h" 8 #include "../h/buf.h" 9 #include "../h/vm.h" 10 #include "../h/ubareg.h" 11 #include "../h/ubavar.h" 12 #include "../h/dir.h" 13 #include "../h/user.h" 14 #include "../h/proc.h" 15 #include "../h/conf.h" 16 #include "../h/mtpr.h" 17 #include "../h/nexus.h" 18 #include "../h/dk.h" 19 20 #if VAX780 21 char ubasr_bits[] = UBASR_BITS; 22 #endif 23 24 /* 25 * Do transfer on device argument. The controller 26 * and uba involved are implied by the device. 27 * We queue for resource wait in the uba code if necessary. 28 * We return 1 if the transfer was started, 0 if it was not. 29 * If you call this routine with the head of the queue for a 30 * UBA, it will automatically remove the device from the UBA 31 * queue before it returns. If some other device is given 32 * as argument, it will be added to the request queue if the 33 * request cannot be started immediately. This means that 34 * passing a device which is on the queue but not at the head 35 * of the request queue is likely to be a disaster. 36 */ 37 ubago(ui) 38 register struct uba_device *ui; 39 { 40 register struct uba_ctlr *um = ui->ui_mi; 41 register struct uba_hd *uh; 42 register int s, unit; 43 44 uh = &uba_hd[um->um_ubanum]; 45 s = spl6(); 46 if (um->um_driver->ud_xclu && uh->uh_users > 0 || uh->uh_xclu) 47 goto rwait; 48 um->um_ubinfo = ubasetup(um->um_ubanum, um->um_tab.b_actf->b_actf, 49 UBA_NEEDBDP|UBA_CANTWAIT); 50 if (um->um_ubinfo == 0) 51 goto rwait; 52 uh->uh_users++; 53 if (um->um_driver->ud_xclu) 54 uh->uh_xclu = 1; 55 splx(s); 56 if (ui->ui_dk >= 0) { 57 unit = ui->ui_dk; 58 dk_busy |= 1<<unit; 59 dk_xfer[unit]++; 60 dk_wds[unit] += um->um_tab.b_actf->b_actf->b_bcount>>6; 61 } 62 if (uh->uh_actf == ui) 63 uh->uh_actf = ui->ui_forw; 64 (*um->um_driver->ud_dgo)(um); 65 return (1); 66 rwait: 67 if (uh->uh_actf != ui) { 68 ui->ui_forw = NULL; 69 if (uh->uh_actf == NULL) 70 uh->uh_actf = ui; 71 else 72 uh->uh_actl->ui_forw = ui; 73 uh->uh_actl = ui; 74 } 75 splx(s); 76 return (0); 77 } 78 79 ubadone(um) 80 register struct uba_ctlr *um; 81 { 82 register struct uba_hd *uh = &uba_hd[um->um_ubanum]; 83 84 if (um->um_driver->ud_xclu) 85 uh->uh_xclu = 0; 86 uh->uh_users--; 87 ubarelse(um->um_ubanum, &um->um_ubinfo); 88 } 89 90 /* 91 * Allocate and setup UBA map registers, and bdp's 92 * Flags says whether bdp is needed, whether the caller can't 93 * wait (e.g. if the caller is at interrupt level). 94 * 95 * Return value: 96 * Bits 0-8 Byte offset 97 * Bits 9-17 Start map reg. no. 98 * Bits 18-27 No. mapping reg's 99 * Bits 28-31 BDP no. 100 */ 101 ubasetup(uban, bp, flags) 102 struct buf *bp; 103 { 104 register struct uba_hd *uh = &uba_hd[uban]; 105 register int temp, i; 106 int npf, reg, bdp; 107 unsigned v; 108 register struct pte *pte, *io; 109 struct proc *rp; 110 int a, o, ubinfo; 111 112 #if VAX7ZZ 113 if (cpu == VAX_7ZZ) 114 flags &= ~UBA_NEEDBDP; 115 #endif 116 v = btop(bp->b_un.b_addr); 117 o = (int)bp->b_un.b_addr & PGOFSET; 118 npf = btoc(bp->b_bcount + o) + 1; 119 a = spl6(); 120 while ((reg = rmalloc(uh->uh_map, npf)) == 0) { 121 if (flags & UBA_CANTWAIT) { 122 splx(a); 123 return (0); 124 } 125 uh->uh_mrwant++; 126 sleep((caddr_t)uh->uh_map, PSWP); 127 } 128 bdp = 0; 129 if (flags & UBA_NEEDBDP) { 130 while ((bdp = ffs(uh->uh_bdpfree)) == 0) { 131 if (flags & UBA_CANTWAIT) { 132 rmfree(uh->uh_map, npf, reg); 133 splx(a); 134 return (0); 135 } 136 uh->uh_bdpwant++; 137 sleep((caddr_t)uh->uh_map, PSWP); 138 } 139 uh->uh_bdpfree &= ~(1 << (bdp-1)); 140 } else if (flags & UBA_HAVEBDP) 141 bdp = (flags >> 28) & 0xf; 142 splx(a); 143 reg--; 144 ubinfo = (bdp << 28) | (npf << 18) | (reg << 9) | o; 145 temp = (bdp << 21) | UBAMR_MRV; 146 if (bdp && (o & 01)) 147 temp |= UBAMR_BO; 148 rp = bp->b_flags&B_DIRTY ? &proc[2] : bp->b_proc; 149 if ((bp->b_flags & B_PHYS) == 0) 150 pte = &Sysmap[btop(((int)bp->b_un.b_addr)&0x7fffffff)]; 151 else if (bp->b_flags & B_UAREA) 152 pte = &rp->p_addr[v]; 153 else if (bp->b_flags & B_PAGET) 154 pte = &Usrptmap[btokmx((struct pte *)bp->b_un.b_addr)]; 155 else 156 pte = vtopte(rp, v); 157 io = &uh->uh_uba->uba_map[reg]; 158 while (--npf != 0) { 159 if (pte->pg_pfnum == 0) 160 panic("uba zero uentry"); 161 *(int *)io++ = pte++->pg_pfnum | temp; 162 } 163 *(int *)io++ = 0; 164 return (ubinfo); 165 } 166 167 /* 168 * Non buffer setup interface... set up a buffer and call ubasetup. 169 */ 170 uballoc(uban, addr, bcnt, flags) 171 int uban; 172 caddr_t addr; 173 int bcnt, flags; 174 { 175 struct buf ubabuf; 176 177 ubabuf.b_un.b_addr = addr; 178 ubabuf.b_flags = B_BUSY; 179 ubabuf.b_bcount = bcnt; 180 /* that's all the fields ubasetup() needs */ 181 return (ubasetup(uban, &ubabuf, flags)); 182 } 183 184 /* 185 * Release resources on uba uban, and then unblock resource waiters. 186 * The map register parameter is by value since we need to block 187 * against uba resets on 11/780's. 188 */ 189 ubarelse(uban, amr) 190 int *amr; 191 { 192 register struct uba_hd *uh = &uba_hd[uban]; 193 register int bdp, reg, npf, s; 194 int mr; 195 196 /* 197 * Carefully see if we should release the space, since 198 * it may be released asynchronously at uba reset time. 199 */ 200 s = spl6(); 201 mr = *amr; 202 if (mr == 0) { 203 /* 204 * A ubareset() occurred before we got around 205 * to releasing the space... no need to bother. 206 */ 207 splx(s); 208 return; 209 } 210 *amr = 0; 211 splx(s); /* let interrupts in, we're safe for a while */ 212 bdp = (mr >> 28) & 0x0f; 213 if (bdp) { 214 switch (cpu) { 215 #if VAX780 216 case VAX_780: 217 uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE; 218 break; 219 #endif 220 #if VAX750 221 case VAX_750: 222 uh->uh_uba->uba_dpr[bdp] |= 223 UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE; 224 break; 225 #endif 226 } 227 uh->uh_bdpfree |= 1 << (bdp-1); /* atomic */ 228 if (uh->uh_bdpwant) { 229 uh->uh_bdpwant = 0; 230 wakeup((caddr_t)uh->uh_map); 231 } 232 } 233 /* 234 * Put back the registers in the resource map. 235 * The map code must not be reentered, so we do this 236 * at high ipl. 237 */ 238 npf = (mr >> 18) & 0x3ff; 239 reg = ((mr >> 9) & 0x1ff) + 1; 240 s = spl6(); 241 rmfree(uh->uh_map, npf, reg); 242 splx(s); 243 244 /* 245 * Wakeup sleepers for map registers, 246 * and also, if there are processes blocked in dgo(), 247 * give them a chance at the UNIBUS. 248 */ 249 if (uh->uh_mrwant) { 250 uh->uh_mrwant = 0; 251 wakeup((caddr_t)uh->uh_map); 252 } 253 while (uh->uh_actf && ubago(uh->uh_actf)) 254 ; 255 } 256 257 ubapurge(um) 258 register struct uba_ctlr *um; 259 { 260 register struct uba_hd *uh = um->um_hd; 261 register int bdp = (um->um_ubinfo >> 28) & 0x0f; 262 263 switch (cpu) { 264 #if VAX780 265 case VAX_780: 266 uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE; 267 break; 268 #endif 269 #if VAX750 270 case VAX_750: 271 uh->uh_uba->uba_dpr[bdp] |= UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE; 272 break; 273 #endif 274 } 275 } 276 277 /* 278 * Generate a reset on uba number uban. Then 279 * call each device in the character device table, 280 * giving it a chance to clean up so as to be able to continue. 281 */ 282 ubareset(uban) 283 int uban; 284 { 285 register struct cdevsw *cdp; 286 register struct uba_hd *uh = &uba_hd[uban]; 287 int s; 288 289 s = spl6(); 290 uh->uh_users = 0; 291 uh->uh_zvcnt = 0; 292 uh->uh_xclu = 0; 293 uh->uh_hangcnt = 0; 294 uh->uh_actf = uh->uh_actl = 0; 295 uh->uh_bdpwant = 0; 296 uh->uh_mrwant = 0; 297 wakeup((caddr_t)&uh->uh_bdpwant); 298 wakeup((caddr_t)&uh->uh_mrwant); 299 printf("uba%d: reset", uban); 300 ubainit(uh->uh_uba); 301 for (cdp = cdevsw; cdp->d_open; cdp++) 302 (*cdp->d_reset)(uban); 303 #ifdef INET 304 ifubareset(uban); 305 #endif 306 printf("\n"); 307 splx(s); 308 } 309 310 /* 311 * Init a uba. This is called with a pointer 312 * rather than a virtual address since it is called 313 * by code which runs with memory mapping disabled. 314 * In these cases we really don't need the interrupts 315 * enabled, but since we run with ipl high, we don't care 316 * if they are, they will never happen anyways. 317 */ 318 ubainit(uba) 319 register struct uba_regs *uba; 320 { 321 322 switch (cpu) { 323 #if VAX780 324 case VAX_780: 325 uba->uba_cr = UBACR_ADINIT; 326 uba->uba_cr = UBACR_IFS|UBACR_BRIE|UBACR_USEFIE|UBACR_SUEFIE; 327 while ((uba->uba_cnfgr & UBACNFGR_UBIC) == 0) 328 ; 329 break; 330 #endif 331 #if VAX750 332 case VAX_750: 333 #endif 334 #if VAX7ZZ 335 case VAX_7ZZ: 336 #endif 337 #if defined(VAX750) || defined(VAX7ZZ) 338 mtpr(IUR, 0); 339 /* give devices time to recover from power fail */ 340 /* THIS IS PROBABLY UNNECESSARY */ 341 DELAY(500000); 342 /* END PROBABLY UNNECESSARY */ 343 break; 344 #endif 345 } 346 } 347 348 #if VAX780 349 /* 350 * Check to make sure the UNIBUS adaptor is not hung, 351 * with an interrupt in the register to be presented, 352 * but not presenting it for an extended period (5 seconds). 353 */ 354 unhang() 355 { 356 register int uban; 357 358 for (uban = 0; uban < numuba; uban++) { 359 register struct uba_hd *uh = &uba_hd[uban]; 360 register struct uba_regs *up = uh->uh_uba; 361 362 if (up->uba_sr == 0) 363 return; 364 up->uba_sr = UBASR_CRD|UBASR_LEB; 365 uh->uh_hangcnt++; 366 if (uh->uh_hangcnt > 5*hz) { 367 uh->uh_hangcnt = 0; 368 printf("uba%d: hung\n", uban); 369 ubareset(uban); 370 } 371 } 372 } 373 374 /* 375 * This is a timeout routine which decrements the ``i forgot to 376 * interrupt'' counts, on an 11/780. This prevents slowly growing 377 * counts from causing a UBA reset since we are interested only 378 * in hang situations. 379 */ 380 ubawatch() 381 { 382 register struct uba_hd *uh; 383 register int uban; 384 385 if (panicstr) 386 return; 387 for (uban = 0; uban < numuba; uban++) { 388 uh = &uba_hd[uban]; 389 if (uh->uh_hangcnt) 390 uh->uh_hangcnt--; 391 } 392 } 393 394 int ubawedgecnt = 10; 395 int ubacrazy = 500; 396 /* 397 * This routine is called by the locore code to 398 * process a UBA error on an 11/780. The arguments are passed 399 * on the stack, and value-result (through some trickery). 400 * In particular, the uvec argument is used for further 401 * uba processing so the result aspect of it is very important. 402 * It must not be declared register. 403 */ 404 /*ARGSUSED*/ 405 ubaerror(uban, uh, xx, uvec, uba) 406 register int uban; 407 register struct uba_hd *uh; 408 int uvec; 409 register struct uba_regs *uba; 410 { 411 register sr, s; 412 413 if (uvec == 0) { 414 uh->uh_zvcnt++; 415 if (uh->uh_zvcnt > 250000) { 416 printf("uba%d: too many zero vectors\n"); 417 ubareset(uban); 418 } 419 uvec = 0; 420 return; 421 } 422 if (uba->uba_cnfgr & NEX_CFGFLT) { 423 printf("uba%d: sbi fault sr=%b cnfgr=%b\n", 424 uban, uba->uba_sr, ubasr_bits, 425 uba->uba_cnfgr, NEXFLT_BITS); 426 ubareset(uban); 427 uvec = 0; 428 return; 429 } 430 sr = uba->uba_sr; 431 s = spl7(); 432 printf("uba%d: uba error sr=%b fmer=%x fubar=%o\n", 433 uban, uba->uba_sr, ubasr_bits, uba->uba_fmer, 4*uba->uba_fubar); 434 splx(s); 435 uba->uba_sr = sr; 436 uvec &= UBABRRVR_DIV; 437 if (++uh->uh_errcnt % ubawedgecnt == 0) { 438 if (uh->uh_errcnt > ubacrazy) 439 panic("uba crazy"); 440 printf("ERROR LIMIT "); 441 ubareset(uban); 442 uvec = 0; 443 return; 444 } 445 return; 446 } 447 #endif 448 449 #ifdef notdef 450 /* 451 * This routine allows remapping of previously 452 * allocated UNIBUS bdp and map resources 453 * onto different memory addresses. 454 * It should only be used by routines which need 455 * small fixed length mappings for long periods of time 456 * (like the ARPANET ACC IMP interface). 457 * It only maps kernel addresses. 458 */ 459 ubaremap(uban, ubinfo, addr) 460 int uban; 461 register unsigned ubinfo; 462 caddr_t addr; 463 { 464 register struct uba_hd *uh = &uba_hd[uban]; 465 register struct pte *pte, *io; 466 register int temp, bdp; 467 int npf, o; 468 469 o = (int)addr & PGOFSET; 470 bdp = (ubinfo >> 28) & 0xf; 471 npf = (ubinfo >> 18) & 0x3ff; 472 io = &uh->uh_uba->uba_map[(ubinfo >> 9) & 0x1ff]; 473 temp = (bdp << 21) | UBAMR_MRV; 474 475 /* 476 * If using buffered data path initiate purge 477 * of old data and set byte offset bit if next 478 * transfer will be from odd address. 479 */ 480 if (bdp) { 481 switch (cpu) { 482 #if VAX780 483 case VAX_780: 484 uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE; 485 break; 486 #endif 487 #if VAX750 488 case VAX_750: 489 uh->uh_uba->uba_dpr[bdp] |= 490 UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE; 491 break; 492 #endif 493 } 494 if (o & 1) 495 temp |= UBAMR_BO; 496 } 497 498 /* 499 * Set up the map registers, leaving an invalid reg 500 * at the end to guard against wild unibus transfers. 501 */ 502 pte = &Sysmap[btop(((int)addr)&0x7fffffff)]; 503 while (--npf != 0) 504 *(int *)io++ = pte++->pg_pfnum | temp; 505 *(int *)io = 0; 506 507 /* 508 * Return effective UNIBUS address. 509 */ 510 return (ubinfo | o); 511 } 512 #endif 513