1 /* uba.c 4.31 81/05/12 */ 2 3 #include "../h/param.h" 4 #include "../h/systm.h" 5 #include "../h/cpu.h" 6 #include "../h/map.h" 7 #include "../h/pte.h" 8 #include "../h/buf.h" 9 #include "../h/vm.h" 10 #include "../h/ubareg.h" 11 #include "../h/ubavar.h" 12 #include "../h/dir.h" 13 #include "../h/user.h" 14 #include "../h/proc.h" 15 #include "../h/conf.h" 16 #include "../h/mtpr.h" 17 #include "../h/nexus.h" 18 #include "../h/dk.h" 19 20 #if VAX780 21 char ubasr_bits[] = UBASR_BITS; 22 #endif 23 24 /* 25 * Do transfer on device argument. The controller 26 * and uba involved are implied by the device. 27 * We queue for resource wait in the uba code if necessary. 28 * We return 1 if the transfer was started, 0 if it was not. 29 * If you call this routine with the head of the queue for a 30 * UBA, it will automatically remove the device from the UBA 31 * queue before it returns. If some other device is given 32 * as argument, it will be added to the request queue if the 33 * request cannot be started immediately. This means that 34 * passing a device which is on the queue but not at the head 35 * of the request queue is likely to be a disaster. 36 */ 37 ubago(ui) 38 register struct uba_device *ui; 39 { 40 register struct uba_ctlr *um = ui->ui_mi; 41 register struct uba_hd *uh; 42 register int s, unit; 43 44 uh = &uba_hd[um->um_ubanum]; 45 s = spl6(); 46 if (um->um_driver->ud_xclu && uh->uh_users > 0 || uh->uh_xclu) 47 goto rwait; 48 um->um_ubinfo = ubasetup(um->um_ubanum, um->um_tab.b_actf->b_actf, 49 UBA_NEEDBDP|UBA_CANTWAIT); 50 if (um->um_ubinfo == 0) 51 goto rwait; 52 uh->uh_users++; 53 if (um->um_driver->ud_xclu) 54 uh->uh_xclu = 1; 55 splx(s); 56 if (ui->ui_dk >= 0) { 57 unit = ui->ui_dk; 58 dk_busy |= 1<<unit; 59 } 60 if (uh->uh_actf == ui) 61 uh->uh_actf = ui->ui_forw; 62 (*um->um_driver->ud_dgo)(um); 63 if (ui->ui_dk >= 0) { 64 dk_xfer[unit]++; 65 dk_wds[unit] += um->um_tab.b_actf->b_actf->b_bcount>>6; 66 } 67 return (1); 68 rwait: 69 if (uh->uh_actf != ui) { 70 ui->ui_forw = NULL; 71 if (uh->uh_actf == NULL) 72 uh->uh_actf = ui; 73 else 74 uh->uh_actl->ui_forw = ui; 75 uh->uh_actl = ui; 76 } 77 splx(s); 78 return (0); 79 } 80 81 ubadone(um) 82 register struct uba_ctlr *um; 83 { 84 register struct uba_hd *uh = &uba_hd[um->um_ubanum]; 85 86 if (um->um_driver->ud_xclu) 87 uh->uh_xclu = 0; 88 uh->uh_users--; 89 ubarelse(um->um_ubanum, &um->um_ubinfo); 90 } 91 92 /* 93 * Allocate and setup UBA map registers, and bdp's 94 * Flags says whether bdp is needed, whether the caller can't 95 * wait (e.g. if the caller is at interrupt level). 96 * 97 * Return value: 98 * Bits 0-8 Byte offset 99 * Bits 9-17 Start map reg. no. 100 * Bits 18-27 No. mapping reg's 101 * Bits 28-31 BDP no. 102 */ 103 ubasetup(uban, bp, flags) 104 struct buf *bp; 105 { 106 register struct uba_hd *uh = &uba_hd[uban]; 107 register int temp, i; 108 int npf, reg, bdp; 109 unsigned v; 110 register struct pte *pte, *io; 111 struct proc *rp; 112 int a, o, ubinfo; 113 114 #if VAX7ZZ 115 if (cpu == VAX_7ZZ) 116 flags &= ~UBA_NEEDBDP; 117 #endif 118 v = btop(bp->b_un.b_addr); 119 o = (int)bp->b_un.b_addr & PGOFSET; 120 npf = btoc(bp->b_bcount + o) + 1; 121 a = spl6(); 122 while ((reg = rmalloc(uh->uh_map, npf)) == 0) { 123 if (flags & UBA_CANTWAIT) 124 return (0); 125 uh->uh_mrwant++; 126 sleep((caddr_t)uh->uh_map, PSWP); 127 } 128 bdp = 0; 129 if (flags & UBA_NEEDBDP) { 130 while ((bdp = ffs(uh->uh_bdpfree)) == 0) { 131 if (flags & UBA_CANTWAIT) { 132 rmfree(uh->uh_map, npf, reg); 133 return (0); 134 } 135 uh->uh_bdpwant++; 136 sleep((caddr_t)uh->uh_map, PSWP); 137 } 138 uh->uh_bdpfree &= ~(1 << (bdp-1)); 139 } 140 splx(a); 141 reg--; 142 ubinfo = (bdp << 28) | (npf << 18) | (reg << 9) | o; 143 io = &uh->uh_uba->uba_map[reg]; 144 temp = (bdp << 21) | UBAMR_MRV; 145 rp = bp->b_flags&B_DIRTY ? &proc[2] : bp->b_proc; 146 if (bdp && (o & 01)) 147 temp |= UBAMR_BO; 148 if (bp->b_flags & B_UAREA) { 149 for (i = UPAGES - bp->b_bcount / NBPG; i < UPAGES; i++) { 150 if (rp->p_addr[i].pg_pfnum == 0) 151 panic("uba: zero upage"); 152 *(int *)io++ = rp->p_addr[i].pg_pfnum | temp; 153 } 154 } else if ((bp->b_flags & B_PHYS) == 0) { 155 pte = &Sysmap[btop(((int)bp->b_un.b_addr)&0x7fffffff)]; 156 while (--npf != 0) 157 *(int *)io++ = pte++->pg_pfnum | temp; 158 } else { 159 if (bp->b_flags & B_PAGET) 160 pte = &Usrptmap[btokmx((struct pte *)bp->b_un.b_addr)]; 161 else 162 pte = vtopte(rp, v); 163 while (--npf != 0) { 164 if (pte->pg_pfnum == 0) 165 panic("uba zero uentry"); 166 *(int *)io++ = pte++->pg_pfnum | temp; 167 } 168 } 169 *(int *)io++ = 0; 170 return (ubinfo); 171 } 172 173 /* 174 * Non buffer setup interface... set up a buffer and call ubasetup. 175 */ 176 uballoc(uban, addr, bcnt, flags) 177 int uban; 178 caddr_t addr; 179 int bcnt, flags; 180 { 181 struct buf ubabuf; 182 183 ubabuf.b_un.b_addr = addr; 184 ubabuf.b_flags = B_BUSY; 185 ubabuf.b_bcount = bcnt; 186 /* that's all the fields ubasetup() needs */ 187 return (ubasetup(uban, &ubabuf, flags)); 188 } 189 190 /* 191 * Release resources on uba uban, and then unblock resource waiters. 192 * The map register parameter is by value since we need to block 193 * against uba resets on 11/780's. 194 */ 195 ubarelse(uban, amr) 196 int *amr; 197 { 198 register struct uba_hd *uh = &uba_hd[uban]; 199 register int bdp, reg, npf, s; 200 int mr; 201 202 /* 203 * Carefully see if we should release the space, since 204 * it may be released asynchronously at uba reset time. 205 */ 206 s = spl6(); 207 mr = *amr; 208 if (mr == 0) { 209 /* 210 * A ubareset() occurred before we got around 211 * to releasing the space... no need to bother. 212 */ 213 splx(s); 214 return; 215 } 216 *amr = 0; 217 splx(s); /* let interrupts in, we're safe for a while */ 218 bdp = (mr >> 28) & 0x0f; 219 if (bdp) { 220 switch (cpu) { 221 #if VAX780 222 case VAX_780: 223 uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE; 224 break; 225 #endif 226 #if VAX750 227 case VAX_750: 228 uh->uh_uba->uba_dpr[bdp] |= 229 UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE; 230 break; 231 #endif 232 } 233 uh->uh_bdpfree |= 1 << (bdp-1); /* atomic */ 234 if (uh->uh_bdpwant) { 235 uh->uh_bdpwant = 0; 236 wakeup((caddr_t)uh->uh_map); 237 } 238 } 239 /* 240 * Put back the registers in the resource map. 241 * The map code must not be reentered, so we do this 242 * at high ipl. 243 */ 244 npf = (mr >> 18) & 0x3ff; 245 reg = ((mr >> 9) & 0x1ff) + 1; 246 s = spl6(); 247 rmfree(uh->uh_map, npf, reg); 248 splx(s); 249 250 /* 251 * Wakeup sleepers for map registers, 252 * and also, if there are processes blocked in dgo(), 253 * give them a chance at the UNIBUS. 254 */ 255 if (uh->uh_mrwant) { 256 uh->uh_mrwant = 0; 257 wakeup((caddr_t)uh->uh_map); 258 } 259 while (uh->uh_actf && ubago(uh->uh_actf)) 260 ; 261 } 262 263 ubapurge(um) 264 register struct uba_ctlr *um; 265 { 266 register struct uba_hd *uh = um->um_hd; 267 register int bdp = (um->um_ubinfo >> 28) & 0x0f; 268 269 switch (cpu) { 270 #if VAX780 271 case VAX_780: 272 uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE; 273 break; 274 #endif 275 #if VAX750 276 case VAX_750: 277 uh->uh_uba->uba_dpr[bdp] |= UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE; 278 break; 279 #endif 280 } 281 } 282 283 /* 284 * Generate a reset on uba number uban. Then 285 * call each device in the character device table, 286 * giving it a chance to clean up so as to be able to continue. 287 */ 288 ubareset(uban) 289 int uban; 290 { 291 register struct cdevsw *cdp; 292 register struct uba_hd *uh = &uba_hd[uban]; 293 int s; 294 295 s = spl6(); 296 uh->uh_users = 0; 297 uh->uh_zvcnt = 0; 298 uh->uh_xclu = 0; 299 uh->uh_hangcnt = 0; 300 uh->uh_actf = uh->uh_actl = 0; 301 uh->uh_bdpwant = 0; 302 uh->uh_mrwant = 0; 303 wakeup((caddr_t)&uh->uh_bdpwant); 304 wakeup((caddr_t)&uh->uh_mrwant); 305 printf("uba%d: reset", uban); 306 ubainit(uh->uh_uba); 307 for (cdp = cdevsw; cdp->d_open; cdp++) 308 (*cdp->d_reset)(uban); 309 printf("\n"); 310 splx(s); 311 } 312 313 /* 314 * Init a uba. This is called with a pointer 315 * rather than a virtual address since it is called 316 * by code which runs with memory mapping disabled. 317 * In these cases we really don't need the interrupts 318 * enabled, but since we run with ipl high, we don't care 319 * if they are, they will never happen anyways. 320 */ 321 ubainit(uba) 322 register struct uba_regs *uba; 323 { 324 325 switch (cpu) { 326 #if VAX780 327 case VAX_780: 328 uba->uba_cr = UBACR_ADINIT; 329 uba->uba_cr = UBACR_IFS|UBACR_BRIE|UBACR_USEFIE|UBACR_SUEFIE; 330 while ((uba->uba_cnfgr & UBACNFGR_UBIC) == 0) 331 ; 332 break; 333 #endif 334 #if VAX750 335 case VAX_750: 336 #endif 337 #if VAX7ZZ 338 case VAX_7ZZ: 339 #endif 340 #if defined(VAX750) || defined(VAX7ZZ) 341 mtpr(IUR, 0); 342 /* give devices time to recover from power fail */ 343 /* THIS IS PROBABLY UNNECESSARY */ 344 DELAY(500000); 345 /* END PROBABLY UNNECESSARY */ 346 break; 347 #endif 348 } 349 } 350 351 #if VAX780 352 /* 353 * Check to make sure the UNIBUS adaptor is not hung, 354 * with an interrupt in the register to be presented, 355 * but not presenting it for an extended period (5 seconds). 356 */ 357 unhang() 358 { 359 register int uban; 360 361 for (uban = 0; uban < numuba; uban++) { 362 register struct uba_hd *uh = &uba_hd[uban]; 363 register struct uba_regs *up = uh->uh_uba; 364 365 if (up->uba_sr == 0) 366 return; 367 uh->uh_hangcnt++; 368 if (uh->uh_hangcnt > 5*hz) { 369 uh->uh_hangcnt = 0; 370 printf("uba%d: hung\n", uban); 371 ubareset(uban); 372 } 373 } 374 } 375 376 /* 377 * This is a timeout routine which decrements the ``i forgot to 378 * interrupt'' counts, on an 11/780. This prevents slowly growing 379 * counts from causing a UBA reset since we are interested only 380 * in hang situations. 381 */ 382 ubawatch() 383 { 384 register struct uba_hd *uh; 385 register int uban; 386 387 if (panicstr) 388 return; 389 for (uban = 0; uban < numuba; uban++) { 390 uh = &uba_hd[uban]; 391 if (uh->uh_hangcnt) 392 uh->uh_hangcnt--; 393 } 394 } 395 396 /* 397 * This routine is called by the locore code to 398 * process a UBA error on an 11/780. The arguments are passed 399 * on the stack, and value-result (through some trickery). 400 * In particular, the uvec argument is used for further 401 * uba processing so the result aspect of it is very important. 402 * It must not be declared register. 403 */ 404 /*ARGSUSED*/ 405 ubaerror(uban, uh, xx, uvec, uba) 406 register int uban; 407 register struct uba_hd *uh; 408 int uvec; 409 register struct uba_regs *uba; 410 { 411 register sr, s; 412 413 if (uvec == 0) { 414 uh->uh_zvcnt++; 415 if (uh->uh_zvcnt > 250000) { 416 printf("uba%d: too many zero vectors\n"); 417 ubareset(uban); 418 } 419 uvec = 0; 420 return; 421 } 422 if (uba->uba_cnfgr & NEX_CFGFLT) { 423 printf("uba%d: sbi fault sr=%b cnfgr=%b\n", 424 uban, uba->uba_sr, ubasr_bits, 425 uba->uba_cnfgr, NEXFLT_BITS); 426 ubareset(uban); 427 uvec = 0; 428 return; 429 } 430 sr = uba->uba_sr; 431 s = spl7(); 432 printf("uba%d: uba error sr=%b fmer=%x fubar=%o\n", 433 uban, uba->uba_sr, ubasr_bits, uba->uba_fmer, 4*uba->uba_fubar); 434 splx(s); 435 uba->uba_sr = sr; 436 uvec &= UBABRRVR_DIV; 437 return; 438 } 439 #endif 440 441 #ifdef BBNNET 442 /* 443 * This routine allows remapping of previously 444 * allocated UNIBUS bdp and map resources 445 * onto different memory addresses. 446 * It should only be used by routines which need 447 * small fixed length mappings for long periods of time 448 * (like the ARPANET ACC IMP interface). 449 * It only maps kernel addresses. 450 */ 451 ubaremap(uban, ubinfo, addr) 452 int uban; 453 register unsigned ubinfo; 454 caddr_t addr; 455 { 456 register struct uba_hd *uh = &uba_hd[uban]; 457 register struct pte *pte, *io; 458 register int temp, bdp; 459 int npf, o; 460 461 o = (int)addr & PGOFSET; 462 bdp = (ubinfo >> 28) & 0xf; 463 npf = (ubinfo >> 18) & 0x3ff; 464 io = &uh->uh_uba->uba_map[(ubinfo >> 9) & 0x1ff]; 465 temp = (bdp << 21) | UBAMR_MRV; 466 467 /* 468 * If using buffered data path initiate purge 469 * of old data and set byte offset bit if next 470 * transfer will be from odd address. 471 */ 472 if (bdp) { 473 switch (cpu) { 474 #if VAX780 475 case VAX_780: 476 uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE; 477 break; 478 #endif 479 #if VAX750 480 case VAX_750: 481 uh->uh_uba->uba_dpr[bdp] |= 482 UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE; 483 break; 484 #endif 485 } 486 if (o & 1) 487 temp |= UBAMR_BO; 488 } 489 490 /* 491 * Set up the map registers, leaving an invalid reg 492 * at the end to guard against wild unibus transfers. 493 */ 494 pte = &Sysmap[btop(((int)addr)&0x7fffffff)]; 495 while (--npf != 0) 496 *(int *)io++ = pte++->pg_pfnum | temp; 497 *(int *)io = 0; 498 499 /* 500 * Return effective UNIBUS address. 501 */ 502 return (ubinfo | o); 503 } 504 #endif 505