1 /*- 2 * Copyright (c) 1982, 1986 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * @(#)ubareg.h 7.8 (Berkeley) 05/09/91 8 */ 9 10 /* 11 * VAX UNIBUS adapter registers 12 */ 13 14 /* 15 * "UNIBUS" adaptor types. 16 * This code is used for both UNIBUSes and Q-buses 17 * with different types of adaptors. 18 * Definition of a type includes support code for that type. 19 */ 20 #if VAX780 || VAX8600 21 #define DW780 1 /* has adaptor regs, sr: 780/785/8600 */ 22 #endif 23 24 #if VAX750 25 #define DW750 2 /* has adaptor regs, no sr: 750, 730 */ 26 #endif 27 28 #if VAX730 29 #define DW730 3 /* has adaptor regs, no sr: 750, 730 */ 30 #endif 31 32 #if VAX630 || VAX650 33 #define QBA 4 /* 22-bit Q-bus, no adaptor regs: uVAX II */ 34 #endif 35 36 #if VAX8200 || VAX8500 || VAX8800 37 #define DWBUA 5 /* BI UNIBUS adaptor: 8200/8500/8800 */ 38 #endif 39 40 /* 41 * Size of unibus memory address space in pages 42 * (also number of map registers). 43 * QBAPAGES should be 8192, but we don't need nearly that much 44 * address space, and the return from the allocation routine 45 * can accommodate at most 2047 (ubavar.h: UBA_MAXMR); 46 * QBAPAGES must be at least UBAPAGES. Choose pragmatically. 47 */ 48 #define UBAPAGES 496 49 #define NUBMREG 496 50 #if defined(GATEWAY) && !defined(QNIVERT) 51 #define QBAPAGES 1024 52 #else 53 #define QBAPAGES UBAPAGES 54 #endif 55 #define UBAIOADDR 0760000 /* start of I/O page */ 56 #define UBAIOPAGES 16 57 58 #ifndef LOCORE 59 /* 60 * DWBUA hardware registers. 61 */ 62 struct dwbua_regs { 63 int pad1[456]; /* actually bii regs + pad */ 64 int bua_csr; /* control and status register */ 65 int bua_offset; /* vector offset register */ 66 int bua_fubar; /* failed UNIBUS address register */ 67 int bua_bifar; /* BI failed address register */ 68 int bua_udiag[5]; /* micro diagnostics (R/O) */ 69 int pad2[3]; 70 /* dpr[0] is for DDP; dpr's 1 through 5 are for BPD's 1 through 5 */ 71 int bua_dpr[6]; /* data path registers */ 72 int pad3[10]; 73 int bua_bdps[20]; /* buffered data path space *//*???*/ 74 int pad4[8]; 75 struct pte bua_map[UBAPAGES]; /* unibus map registers */ 76 int pad5[UBAIOPAGES]; /* no maps for device address space */ 77 }; 78 79 #ifdef DWBUA 80 /* bua_csr */ 81 #define BUACSR_ERR 0x80000000 /* composite error */ 82 #define BUACSR_BIF 0x10000000 /* BI failure */ 83 #define BUACSR_SSYNTO 0x08000000 /* slave sync timeout */ 84 #define BUACSR_UIE 0x04000000 /* unibus interlock error */ 85 #define BUACSR_IVMR 0x02000000 /* invalid map register */ 86 #define BUACSR_BADBDP 0x01000000 /* bad BDP select */ 87 #define BUACSR_BUAEIE 0x00100000 /* bua error interrupt enable (?) */ 88 #define BUACSR_UPI 0x00020000 /* unibus power init */ 89 #define BUACSR_UREGDUMP 0x00010000 /* microdiag register dump */ 90 #define BUACSR_IERRNO 0x000000ff /* mask for internal errror number */ 91 92 /* bua_offset */ 93 #define BUAOFFSET_MASK 0x00003e00 /* hence max offset = 15872 */ 94 95 /* bua_dpr */ 96 #define BUADPR_DPSEL 0x00e00000 /* data path select (?) */ 97 #define BUADPR_PURGE 0x00000001 /* purge bdp */ 98 99 /* bua_map -- in particular, those bits that are not in DW780s & DW750s */ 100 #define BUAMR_IOADR 0x40000000 /* I/O address space */ 101 #define BUAMR_LAE 0x04000000 /* longword access enable */ 102 /* I see no reason to use either one, though ... act 6 Aug 1987 */ 103 104 #define UBA_PURGEBUA(uba, bdp) \ 105 (((struct dwbua_regs *)(uba))->bua_dpr[bdp] |= BUADPR_PURGE) 106 #else 107 #define UBA_PURGEBUA(uba, bdp) 108 #endif 109 110 /* 111 * DW780/DW750 hardware registers 112 */ 113 struct uba_regs { 114 int uba_cnfgr; /* configuration register */ 115 int uba_cr; /* control register */ 116 int uba_sr; /* status register */ 117 int uba_dcr; /* diagnostic control register */ 118 int uba_fmer; /* failed map entry register */ 119 int uba_fubar; /* failed UNIBUS address register */ 120 int pad1[2]; 121 int uba_brsvr[4]; 122 int uba_brrvr[4]; /* receive vector registers */ 123 int uba_dpr[16]; /* buffered data path register */ 124 int pad2[480]; 125 struct pte uba_map[UBAPAGES]; /* unibus map register */ 126 int pad3[UBAIOPAGES]; /* no maps for device address space */ 127 }; 128 #endif 129 130 #ifdef DW780 131 /* uba_cnfgr */ 132 #define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */ 133 #define UBACNFGR_UBPDN 0x00020000 /* unibus power down */ 134 #define UBACNFGR_UBIC 0x00010000 /* unibus init complete */ 135 136 #define UBACNFGR_BITS \ 137 "\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC" 138 139 /* uba_cr */ 140 #define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */ 141 #define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */ 142 #define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */ 143 #define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */ 144 #define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */ 145 #define UBACR_IFS 0x00000040 /* interrupt field switch */ 146 #define UBACR_BRIE 0x00000020 /* BR interrupt enable */ 147 #define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */ 148 #define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */ 149 #define UBACR_CNFIE 0x00000004 /* configuration IE */ 150 #define UBACR_UPF 0x00000002 /* UNIBUS power fail */ 151 #define UBACR_ADINIT 0x00000001 /* adapter init */ 152 153 /* uba_sr */ 154 #define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */ 155 #define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */ 156 #define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */ 157 #define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */ 158 #define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */ 159 #define UBASR_RDS 0x00000200 /* read data substitute */ 160 #define UBASR_CRD 0x00000100 /* corrected read data */ 161 #define UBASR_CXTER 0x00000080 /* command transmit error */ 162 #define UBASR_CXTMO 0x00000040 /* command transmit timeout */ 163 #define UBASR_DPPE 0x00000020 /* data path parity error */ 164 #define UBASR_IVMR 0x00000010 /* invalid map register */ 165 #define UBASR_MRPF 0x00000008 /* map register parity failure */ 166 #define UBASR_LEB 0x00000004 /* lost error */ 167 #define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */ 168 #define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */ 169 170 #define UBASR_BITS \ 171 "\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO" 172 173 /* uba_brrvr[] */ 174 #define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */ 175 #define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */ 176 #endif 177 178 /* uba_dpr */ 179 #ifdef DW780 180 #define UBADPR_BNE 0x80000000 /* buffer not empty - purge */ 181 #define UBADPR_BTE 0x40000000 /* buffer transfer error */ 182 #define UBADPR_DPF 0x20000000 /* DP function (RO) */ 183 #define UBADPR_BS 0x007f0000 /* buffer state field */ 184 #define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */ 185 #define UBA_PURGE780(uba, bdp) \ 186 ((uba)->uba_dpr[bdp] |= UBADPR_BNE) 187 #else 188 #define UBA_PURGE780(uba, bdp) 189 #endif 190 #ifdef DW750 191 #define UBADPR_ERROR 0x80000000 /* error occurred */ 192 #define UBADPR_NXM 0x40000000 /* nxm from memory */ 193 #define UBADPR_UCE 0x20000000 /* uncorrectable error */ 194 #define UBADPR_PURGE 0x00000001 /* purge bdp */ 195 /* the DELAY is for a hardware problem */ 196 #define UBA_PURGE750(uba, bdp) { \ 197 ((uba)->uba_dpr[bdp] |= (UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE)); \ 198 DELAY(8); \ 199 } 200 #else 201 #define UBA_PURGE750(uba, bdp) 202 #endif 203 204 /* 205 * Macros for fast buffered data path purging in time-critical routines. 206 * 207 * Too bad C pre-processor doesn't have the power of LISP in macro 208 * expansion... 209 */ 210 211 /* THIS IS WRONG, should use pointer to uba_hd */ 212 #if DWBUA || DW780 || DW750 213 #define UBAPURGE(uba, bdp) { \ 214 switch (cpu) { \ 215 case VAX_8200: UBA_PURGEBUA(uba, bdp); break; \ 216 case VAX_8600: case VAX_780: UBA_PURGE780((uba), (bdp)); break; \ 217 case VAX_750: UBA_PURGE750((uba), (bdp)); break; \ 218 } \ 219 } 220 #else 221 #define UBAPURGE(uba, bdp) 222 #endif 223 224 225 226 /* uba_mr[] */ 227 #define UBAMR_MRV 0x80000000 /* map register valid */ 228 #define UBAMR_BO 0x02000000 /* byte offset bit */ 229 #define UBAMR_DPDB 0x01e00000 /* data path designator field */ 230 #define UBAMR_SBIPFN 0x001fffff /* SBI page address field */ 231 232 #define UBAMR_DPSHIFT 21 /* shift to data path designator */ 233 234 /* 235 * Number of unibus buffered data paths and possible uba's per cpu type. 236 */ 237 #define NBDP8600 15 238 #define NBDP780 15 239 #define NBDPBUA 5 240 #define NBDP750 3 241 #define NBDP730 0 242 #define MAXNBDP 15 243 244 /* 245 * Symbolic BUS addresses for UBAs. 246 */ 247 248 #if VAX630 || VAX650 249 #define QBAMAP630 ((struct pte *)0x20088000) 250 #define QMEM630 0x30000000 251 #define QIOPAGE630 0x20000000 252 /* 253 * Q-bus control registers 254 */ 255 #define QIPCR 0x1f40 /* from start of iopage */ 256 /* bits in QIPCR */ 257 #define Q_DBIRQ 0x0001 /* doorbell interrupt request */ 258 #define Q_LMEAE 0x0020 /* local mem external access enable */ 259 #define Q_DBIIE 0x0040 /* doorbell interrupt enable */ 260 #define Q_AUXHLT 0x0100 /* auxiliary processor halt */ 261 #define Q_DMAQPE 0x8000 /* Q22 bus address space parity error */ 262 #endif 263 264 #if VAX730 265 #define UMEM730 0xfc0000 266 #endif 267 268 #if VAX750 269 #define UMEM750(i) (0xfc0000-(i)*0x40000) 270 #endif 271 272 #if VAX780 273 #define UMEM780(i) (0x20100000+(i)*0x40000) 274 #endif 275 276 #if VAX8200 /* BEWARE, argument is node, not ubanum */ 277 #define UMEM8200(i) (0x20400000+(i)*0x40000) 278 #endif 279 280 #if VAX8600 281 #define UMEMA8600(i) (0x20100000+(i)*0x40000) 282 #define UMEMB8600(i) (0x22100000+(i)*0x40000) 283 #endif 284 285 /* 286 * Macro to offset a UNIBUS device address, often expressed as 287 * something like 0172520, by forcing it into the last 8K 288 * of UNIBUS memory space. 289 */ 290 #define ubdevreg(addr) ((addr) & 017777) 291