1 /* utreg.h 4.4 81/11/11 */ 2 3 /* 4 * System Industries Model 9700 Tape Drive 5 * emulates TU45 on the UNIBUS 6 */ 7 8 struct utdevice { 9 u_short utcs1; /* control status register 1 */ 10 short utwc; /* word count register */ 11 u_short utba; /* low 16-bits of bus address */ 12 short utfc; /* frame counter */ 13 u_short utcs2; /* control status register 2 */ 14 u_short utds; /* drive status register */ 15 u_short uter; /* error register */ 16 u_short utas; /* attention status register */ 17 u_short utcc; /* NRZI CRC character for validation */ 18 u_short utdb; /* data buffer reg (not emulated) */ 19 u_short utmr; /* maintenance reg (not emulated) */ 20 u_short utdt; /* drive type register (not emulated) */ 21 u_short utsn; /* serial number reg (not emulated) */ 22 u_short uttc; /* tape control register */ 23 u_short utbae; /* buffer address extension register */ 24 u_short utcs3; /* control and status register 3 */ 25 }; 26 27 /* 28 * utcs1 -- 29 * cmds, interrupt enable, extended address bits, and status 30 */ 31 #define UT_GO 0x0001 /* go bit */ 32 /* function codes reside in bits 5-1 */ 33 #define UT_NOP 0x0000 /* no operation */ 34 #define UT_REWOFFL 0x0002 /* rewind offline */ 35 #define UT_LOOP 0x0004 /* loop read/write */ 36 #define UT_REW 0x0006 /* rewind */ 37 #define UT_CLEAR 0x0008 /* drive clear */ 38 #define UT_SENSE 0x000a /* drive sense */ 39 #define UT_PRESET 0x0010 /* read in preset */ 40 #define UT_DIAGN 0x0012 /* diagnostic mode set */ 41 #define UT_ERASE 0x0014 /* erase */ 42 #define UT_WEOF 0x0016 /* write tape mark */ 43 #define UT_SFORW 0x0018 /* forward space block */ 44 #define UT_SREV 0x001a /* reverse space block */ 45 #define UT_SFORWF 0x001c /* forward space file */ 46 #define UT_SREVF 0x001e /* reverse space file */ 47 #define UT_WCHFORW 0x0028 /* write check forward */ 48 #define UT_WCHREV 0x002e /* write check reverse */ 49 #define UT_WCOM 0x0030 /* write forward */ 50 #define UT_RCOM 0x0038 /* read forward */ 51 #define UT_RREV 0x003e /* read reverse */ 52 /* the remainder are control and status bits */ 53 #define UT_IE 0x0040 /* interrupt-enable */ 54 #define UT_RDY 0x0080 /* controller ready */ 55 #define UT_EADDR 0x0300 /* extended address bits */ 56 /* bit 10 unused */ 57 #define UT_DVA 0x0800 /* drive available */ 58 /* bit 12 unused */ 59 /* bit 13 - massbus control parity error not emulated */ 60 #define UT_TRE 0x4000 /* transfer error */ 61 #define UT_SC 0x8000 /* special condition */ 62 63 #define UT_BITS \ 64 "\10\20SC\17TRE\14DVA\10RDY\7IE\1GO" 65 66 /* 67 * utcs2 -- 68 * controller clear, error flags, and unit select 69 */ 70 /* bits 0-2 are unit select */ 71 #define UTCS2_BAI 0x0008 /* UNIBUS address increment inhibit */ 72 #define UTCS2_PAT 0x0010 /* parity test */ 73 #define UTCS2_CLR 0x0020 /* controller clear */ 74 #define UTCS2_IR 0x0040 /* input ready (not emulated) */ 75 #define UTCS2_OR 0x0080 /* output ready (not emulated) */ 76 #define UTCS2_RPE 0x0100 /* rom parity error */ 77 #define UTCS2_MXF 0x0200 /* missed transfer */ 78 #define UTCS2_NEM 0x0400 /* non existant memory */ 79 #define UTCS2_PGE 0x0800 /* program error */ 80 #define UTCS2_NED 0x1000 /* non existent drive */ 81 #define UTCS2_PE 0x2000 /* parity error */ 82 #define UTCS2_WCE 0x4000 /* write check error */ 83 #define UTCS2_DLT 0x8000 /* data late */ 84 85 #define UTCS2_BITS \ 86 "\10\20DLT\17WCE\16PE\15NED\14\NEM\13\PGE\12\MXF\11RPE\10OR\7IR\6CLR\5PAT\4\BAI" 87 88 /* 89 * utds -- 90 * beginning of tape, end of tape, error summary bit, plus lots more 91 */ 92 #define UTDS_SLA 0x0001 /* slave attention */ 93 #define UTDS_BOT 0x0002 /* beginning of tape */ 94 #define UTDS_TM 0x0004 /* tape mark */ 95 #define UTDS_IDB 0x0008 /* identification burst */ 96 #define UTDS_SDWN 0x0010 /* slowing down */ 97 #define UTDS_PES 0x0020 /* phase encode status */ 98 #define UTDS_SSC 0x0040 /* slave status change */ 99 #define UTDS_DRY 0x0080 /* drive ready */ 100 #define UTDS_DPR 0x0100 /* drive present (always 1) */ 101 #define UTDS_GCR 0x0200 /* GCR status */ 102 #define UTDS_EOT 0x0400 /* end of tape */ 103 #define UTDS_WRL 0x0800 /* write lock */ 104 #define UTDS_MOL 0x1000 /* medium on line */ 105 #define UTDS_PIP 0x2000 /* positioning in progress */ 106 #define UTDS_ERR 0x4000 /* composite error */ 107 #define UTDS_ATA 0x8000 /* attention active */ 108 109 #define UTDS_BITS \ 110 "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13EOT\12GCR\11DPR\10DRY\ 111 \7SSC\6PES\5SDWN\4IDB\3TM\2BOT\1SLA" 112 113 /* 114 * uter -- 115 * detailed breakdown of error summary bit from cs2 116 */ 117 #define UTER_ILF 0x0001 /* illegal function */ 118 #define UTER_ILR 0x0002 /* illegal register (always 0) */ 119 #define UTER_RMR 0x0004 /* register modification refused */ 120 #define UTER_RPE 0x0008 /* read data parity error */ 121 #define UTER_FMT 0x0010 /* format error */ 122 #define UTER_DPAR 0x0020 /* data bus parity error */ 123 #define UTER_INC 0x0040 /* incorrectable data */ 124 #define UTER_PEF 0x0080 /* PE format error */ 125 #define UTER_NSG 0x0100 /* non standard gap */ 126 #define UTER_FCE 0x0200 /* frame count error */ 127 #define UTER_CS 0x0400 /* correctable skew */ 128 #define UTER_NEF 0x0800 /* non executable function */ 129 #define UTER_DTE 0x1000 /* drive timing error */ 130 #define UTER_OPI 0x2000 /* operation incomplete */ 131 #define UTER_UNS 0x4000 /* unsafe */ 132 #define UTER_COR 0x8000 /* correctible data error */ 133 134 /* 135 * These errors we consider "hard"; UTER_OPI and UTER_RPE 136 * are considered "soft", at least for the moment. 137 */ 138 #define UTER_HARD (UTER_UNS|UTER_NEF|UTER_DPAR|UTER_FMT|UTER_RMR|\ 139 UTER_ILR|UTER_ILF) 140 141 #define UTER_BITS \ 142 "\10\20COR\17UNS\16OPI\15DTE\14NEF\13CS\12FCE\11NSG\10PEF\ 143 \7INC\6DPAR\5FMT\4RPE\3RMR\2ILR\1ILF" 144 145 /* 146 * uttc -- 147 * tape format and density 148 */ 149 /* bits 0-2 are slave select */ 150 #define UTTC_EVPAR 0x0008 /* even parity */ 151 #define UTTC_FMT 0x00f0 /* format select (see below) */ 152 #define UTTC_DEN 0x0700 /* density select (see below) */ 153 /* bit 11 not used */ 154 #define UTTC_EAODTE 0x1000 /* (not emulated) */ 155 #define UTTC_TCW 0x2000 /* tape control write */ 156 #define UTTC_FCS 0x4000 /* frame count status */ 157 #define UTTC_ACCL 0x8000 /* acceleration */ 158 159 /* the bits to stuff in UTTC_DEN */ 160 #define UT_NRZI 0x0000 /* 800 bpi code */ 161 #define UT_PE 0x0400 /* 1600 bpi code */ 162 #define UT_GCR 0x0500 /* 6250 bpi code */ 163 164 /* tape formats - only PDP-11 standard is supported */ 165 #define PDP11FMT 0x00c0 /* PDP-11 standard */ 166 167 #define b_repcnt b_bcount 168 #define b_command b_resid 169 #define b_state b_active 170