1 /* 2 * Copyright (c) 1988 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Mt. Xinu. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)ka650.h 7.5 (Berkeley) 06/28/90 11 */ 12 13 /* 14 * 15 * Definitions specific to the ka650 (uVAX 3600/3602) cpu card. 16 */ 17 18 #ifdef VAX650 19 /* 20 * CAER: Memory System Error Register (IPR 39) 21 */ 22 #define CAER_DAL 0x00000040 /* CDAL or level 2 cache data parity */ 23 #define CAER_MCD 0x00000020 /* mcheck due to DAL parity error */ 24 #define CAER_MCC 0x00000010 /* mcheck due to 1st lev cache parity */ 25 #define CAER_DAT 0x00000002 /* data parity in 1st level cache */ 26 #define CAER_TAG 0x00000001 /* tag parity in 1st level cache */ 27 28 /* 29 * CADR: Cache Disable Register (IPR 37) 30 */ 31 #define CADR_STMASK 0x000000f0 /* 1st level cache state mask */ 32 #define CADR_SEN2 0x00000080 /* 1st level cache set 2 enabled */ 33 #define CADR_SEN1 0x00000040 /* 1st level cache set 1 enabled */ 34 #define CADR_CENI 0x00000020 /* 1st level I-stream caching enabled */ 35 #define CADR_CEND 0x00000010 /* 1st level D-stream caching enabled */ 36 37 /* 38 * Internal State Info 2: (for mcheck recovery) 39 */ 40 #define IS2_VCR 0x00008000 /* VAX Can't Restart flag */ 41 42 /* 43 * DMA System Error Register (merr_dser) 44 */ 45 #define DSER_QNXM 0x00000080 /* Q-22 Bus NXM */ 46 #define DSER_QPE 0x00000020 /* Q-22 Bus parity Error */ 47 #define DSER_MEM 0x00000010 /* Main mem err due to ext dev DMA */ 48 #define DSER_LOST 0x00000008 /* Lost error: DSER <7,5,4,0> set */ 49 #define DSER_NOGRANT 0x00000004 /* No Grant timeout on cpu demand R/W */ 50 #define DSER_DNXM 0x00000001 /* DMA NXM */ 51 #define DSER_CLEAR (DSER_QNXM | DSER_QPE | DSER_MEM | \ 52 DSER_LOST | DSER_NOGRANT | DSER_DNXM) 53 #define DMASER_BITS \ 54 "\20\20BHALT\17DCNEG\10QBNXM\6QBPE\5MEMERR\4LOSTERR\3NOGRANT\1DMANXM" 55 56 #ifndef LOCORE 57 /* 58 * Local registers (in I/O space) 59 * This is done in disjoint sections. Map names are set in locore.s 60 * and they are mapped in routine configcpu() 61 */ 62 63 /* 64 * memory error & configuration registers 65 */ 66 struct ka650_merr { 67 u_long merr_scr; /* System Config Register */ 68 u_long merr_dser; /* DMA System Error Register */ 69 u_long merr_qbear; /* QBus Error Address Register */ 70 u_long merr_dear; /* DMA Error Address Register */ 71 u_long merr_qbmbr; /* Q Bus Map Base address Register */ 72 u_long pad[59]; 73 u_long merr_csr[16]; /* Main Memory Config Regs (16 banks) */ 74 u_long merr_errstat; /* Main Memory Error Status */ 75 u_long merr_cont; /* Main Memory Control */ 76 }; 77 #define KA650_MERR 0x20080000 78 79 /* 80 * Main Memory Error Status Register (merr_errstat) 81 */ 82 #define MEM_EMASK 0xe0000180 /* mask of all err bits */ 83 #define MEM_RDS 0x80000000 /* uncorrectable main memory */ 84 #define MEM_RDSHIGH 0x40000000 /* high rate RDS errors */ 85 #define MEM_CRD 0x20000000 /* correctable main memory */ 86 #define MEM_DMA 0x00000100 /* DMA read or write error */ 87 #define MEM_CDAL 0x00000080 /* CDAL Parity error on write */ 88 #define MEM_PAGE 0x1ffffe00 /* Offending Page Number */ 89 #define MEM_PAGESHFT 9 /* Shift to normalize page number */ 90 91 /* 92 * Main Memory Control & Diag Status Reg (merr_cont) 93 */ 94 #define MEM_CRDINT 0x00001000 /* CRD interrupts enabled */ 95 #define MEM_REFRESH 0x00000800 /* Forced memory refresh */ 96 #define MEM_ERRDIS 0x00000400 /* error detect disable */ 97 #define MEM_DIAG 0x00000080 /* Diagnostics mode */ 98 #define MEM_CHECK 0x0000007f /* check bits for diagnostic mode */ 99 100 /* 101 * Main Memory Config Regs (merr_csr[0-15]) 102 */ 103 #define MEM_BNKENBLE 0x80000000 /* Bank Enable */ 104 #define MEM_BNKNUM 0x03c00000 /* Physical map Bank number */ 105 #define MEM_BNKUSAGE 0x00000003 /* Bank Usage */ 106 107 /* 108 * Cache Control & Boot/Diag registers 109 */ 110 struct ka650_cbd { 111 u_char cbd_cacr; /* Low byte: Cache Enable & Parity Err detect */ 112 u_char cbd_cdf1; /* Cache diagnostic field (unused) */ 113 u_char cbd_cdf2; /* Cache diagnostic field (unused) */ 114 u_char pad; 115 u_long cbd_bdr; /* Boot & Diagnostic Register (unused) */ 116 }; 117 #define KA650_CBD 0x20084000 118 119 /* 120 * CACR: Cache Control Register (2nd level cache) (cbd_cacr) 121 */ 122 #define CACR_CEN 0x00000010 /* Cache enable */ 123 #define CACR_CPE 0x00000020 /* Cache Parity Error */ 124 125 /* 126 * System Support Chip (SSC) registers 127 */ 128 struct ka650_ssc { 129 u_long ssc_sscbr; /* SSC Base Addr Register */ 130 u_long pad1[3]; 131 u_long ssc_ssccr; /* SSC Configuration Register */ 132 u_long pad2[3]; 133 u_long ssc_cbtcr; /* CDAL Bus Timeout Control Register */ 134 u_long pad3[55]; 135 u_long ssc_tcr0; /* timer control reg 0 */ 136 u_long ssc_tir0; /* timer interval reg 0 */ 137 u_long ssc_tnir0; /* timer next interval reg 0 */ 138 u_long ssc_tivr0; /* timer interrupt vector reg 0 */ 139 u_long ssc_tcr1; /* timer control reg 1 */ 140 u_long ssc_tir1; /* timer interval reg 1 */ 141 u_long ssc_tnir1; /* timer next interval reg 1 */ 142 u_long ssc_tivr1; /* timer interrupt vector reg 1 */ 143 u_long pad4[184]; 144 u_char ssc_cpmbx; /* Console Program Mail Box: Lang & Hact */ 145 u_char ssc_terminfo; /* TTY info: Video Dev, MCS, CRT & ROM flags */ 146 u_char ssc_keyboard; /* Keyboard code */ 147 }; 148 #define KA650_SSC 0x20140000 149 150 /* 151 * CBTCR: CDAL Bus Timeout Control Register (ssc_cbtcr) 152 */ 153 #define CBTCR_BTO 0x80000000 /* r/w unimp IPR or unack intr */ 154 #define CBTCR_RWT 0x40000000 /* CDAL Bus Timeout on CPU or DMA */ 155 156 /* 157 * TCR0/TCR1: Programable Timer Control Registers (ssc_tcr[01]) 158 * (The rest of the bits are the same as in the standard VAX 159 * Interval timer and are defined in clock.h) 160 */ 161 #define TCR_STP 0x00000004 /* Stop after time-out */ 162 163 /* 164 * Flags for Console Program Mail Box 165 */ 166 #define CPMB650_HALTACT 0x03 /* Field for halt action */ 167 #define CPMB650_RESTART 0x01 /* Restart */ 168 #define CPMB650_REBOOT 0x02 /* Reboot */ 169 #define CPMB650_HALT 0x03 /* Halt */ 170 #define CPMB650_BIP 0x04 /* Bootstrap in progress */ 171 #define CPMB650_RIP 0x08 /* Restart in progress */ 172 #define CPMB650_LANG 0xf0 /* Language field */ 173 174 /* 175 * Inter Processor Communication Register 176 * To determine if memory error was from QBUS device DMA (as opposed to cpu). 177 */ 178 struct ka650_ipcr { 179 u_long pad[80]; 180 u_short ipcr0; /* InterProcessor Comm Reg for arbiter */ 181 }; 182 #define KA650_IPCR 0x20001e00 183 184 #ifndef STANDALONE 185 /* 186 * External declarations of the map names (declared in spt.s) 187 * for the local register space. 188 */ 189 extern struct pte KA650MERRmap[]; 190 extern struct ka650_merr ka650merr; /* mem err & mem config regs */ 191 extern struct pte KA650CBDmap[]; 192 extern struct ka650_cbd ka650cbd; /* cache control & boot/diag regs */ 193 extern struct pte KA650SSCmap[]; 194 extern struct ka650_ssc ka650ssc; /* SSC regs (& console prog mail box) */ 195 extern struct pte KA650IPCRmap[]; 196 extern struct ka650_ipcr ka650ipcr; /* InterProcessor Com Regs */ 197 extern struct pte KA650CACHEmap[]; 198 extern int ka650cache[]; /* Cache Diagnostic space (for flush) */ 199 #endif STANDALONE 200 #endif LOCORE 201 202 /* 203 * Physical start address of the Qbus memory. 204 * The q-bus memory size is 4 meg. 205 * Physical start address of the I/O space (where the 8Kbyte I/O page is). 206 */ 207 #define KA650_QMEM 0x30000000 208 #define KA650_QMEMSIZE (512*8192) 209 #define KA650_QDEVADDR 0x20000000 210 211 /* 212 * Mapping info for Cache Entries, including 213 * Size (in bytes) of 2nd Level Cache for cache flush operation 214 */ 215 #define KA650_CACHE 0x10000000 216 #define KA650_CACHESIZE (64*1024) 217 218 /* 219 * Useful ROM addresses 220 */ 221 #define KA650ROM_SIDEX 0x20060004 /* system ID extension */ 222 #define KA650ROM_GETC 0x20060008 /* (jsb) get character from console */ 223 #define KA650ROM_PUTS 0x2006000c /* (jsb) put string to console */ 224 #define KA650ROM_GETS 0x20060010 /* (jsb) read string with prompt */ 225 #define KA650_CONSTYPE 0x20140401 /* byte at which console type resides */ 226 #endif 227