1 /* 2 * Copyright (c) 1988 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Mt. Xinu. 7 * 8 * Redistribution and use in source and binary forms are permitted 9 * provided that the above copyright notice and this paragraph are 10 * duplicated in all such forms and that any documentation, 11 * advertising materials, and other materials related to such 12 * distribution and use acknowledge that the software was developed 13 * by the University of California, Berkeley. The name of the 14 * University may not be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 18 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 19 * 20 * @(#)ka650.h 7.4 (Berkeley) 11/02/88 21 */ 22 23 /* 24 * 25 * Definitions specific to the ka650 (uVAX 3600/3602) cpu card. 26 */ 27 28 #ifdef VAX650 29 /* 30 * CAER: Memory System Error Register (IPR 39) 31 */ 32 #define CAER_DAL 0x00000040 /* CDAL or level 2 cache data parity */ 33 #define CAER_MCD 0x00000020 /* mcheck due to DAL parity error */ 34 #define CAER_MCC 0x00000010 /* mcheck due to 1st lev cache parity */ 35 #define CAER_DAT 0x00000002 /* data parity in 1st level cache */ 36 #define CAER_TAG 0x00000001 /* tag parity in 1st level cache */ 37 38 /* 39 * CADR: Cache Disable Register (IPR 37) 40 */ 41 #define CADR_STMASK 0x000000f0 /* 1st level cache state mask */ 42 #define CADR_SEN2 0x00000080 /* 1st level cache set 2 enabled */ 43 #define CADR_SEN1 0x00000040 /* 1st level cache set 1 enabled */ 44 #define CADR_CENI 0x00000020 /* 1st level I-stream caching enabled */ 45 #define CADR_CEND 0x00000010 /* 1st level D-stream caching enabled */ 46 47 /* 48 * Internal State Info 2: (for mcheck recovery) 49 */ 50 #define IS2_VCR 0x00008000 /* VAX Can't Restart flag */ 51 52 /* 53 * DMA System Error Register (merr_dser) 54 */ 55 #define DSER_QNXM 0x00000080 /* Q-22 Bus NXM */ 56 #define DSER_QPE 0x00000020 /* Q-22 Bus parity Error */ 57 #define DSER_MEM 0x00000010 /* Main mem err due to ext dev DMA */ 58 #define DSER_LOST 0x00000008 /* Lost error: DSER <7,5,4,0> set */ 59 #define DSER_NOGRANT 0x00000004 /* No Grant timeout on cpu demand R/W */ 60 #define DSER_DNXM 0x00000001 /* DMA NXM */ 61 #define DSER_CLEAR (DSER_QNXM | DSER_QPE | DSER_MEM | \ 62 DSER_LOST | DSER_NOGRANT | DSER_DNXM) 63 #define DMASER_BITS \ 64 "\20\20BHALT\17DCNEG\10QBNXM\6QBPE\5MEMERR\4LOSTERR\3NOGRANT\1DMANXM" 65 66 #ifndef LOCORE 67 /* 68 * Local registers (in I/O space) 69 * This is done in disjoint sections. Map names are set in locore.s 70 * and they are mapped in routine configcpu() 71 */ 72 73 /* 74 * memory error & configuration registers 75 */ 76 struct ka650_merr { 77 u_long merr_scr; /* System Config Register */ 78 u_long merr_dser; /* DMA System Error Register */ 79 u_long merr_qbear; /* QBus Error Address Register */ 80 u_long merr_dear; /* DMA Error Address Register */ 81 u_long merr_qbmbr; /* Q Bus Map Base address Register */ 82 u_long pad[59]; 83 u_long merr_csr[16]; /* Main Memory Config Regs (16 banks) */ 84 u_long merr_errstat; /* Main Memory Error Status */ 85 u_long merr_cont; /* Main Memory Control */ 86 }; 87 #define KA650_MERR 0x20080000 88 89 /* 90 * Main Memory Error Status Register (merr_errstat) 91 */ 92 #define MEM_EMASK 0xe0000180 /* mask of all err bits */ 93 #define MEM_RDS 0x80000000 /* uncorrectable main memory */ 94 #define MEM_RDSHIGH 0x40000000 /* high rate RDS errors */ 95 #define MEM_CRD 0x20000000 /* correctable main memory */ 96 #define MEM_DMA 0x00000100 /* DMA read or write error */ 97 #define MEM_CDAL 0x00000080 /* CDAL Parity error on write */ 98 #define MEM_PAGE 0x1ffffe00 /* Offending Page Number */ 99 #define MEM_PAGESHFT 9 /* Shift to normalize page number */ 100 101 /* 102 * Main Memory Control & Diag Status Reg (merr_cont) 103 */ 104 #define MEM_CRDINT 0x00001000 /* CRD interrupts enabled */ 105 #define MEM_REFRESH 0x00000800 /* Forced memory refresh */ 106 #define MEM_ERRDIS 0x00000400 /* error detect disable */ 107 #define MEM_DIAG 0x00000080 /* Diagnostics mode */ 108 #define MEM_CHECK 0x0000007f /* check bits for diagnostic mode */ 109 110 /* 111 * Main Memory Config Regs (merr_csr[0-15]) 112 */ 113 #define MEM_BNKENBLE 0x80000000 /* Bank Enable */ 114 #define MEM_BNKNUM 0x03c00000 /* Physical map Bank number */ 115 #define MEM_BNKUSAGE 0x00000003 /* Bank Usage */ 116 117 /* 118 * Cache Control & Boot/Diag registers 119 */ 120 struct ka650_cbd { 121 u_char cbd_cacr; /* Low byte: Cache Enable & Parity Err detect */ 122 u_char cbd_cdf1; /* Cache diagnostic field (unused) */ 123 u_char cbd_cdf2; /* Cache diagnostic field (unused) */ 124 u_char pad; 125 u_long cbd_bdr; /* Boot & Diagnostic Register (unused) */ 126 }; 127 #define KA650_CBD 0x20084000 128 129 /* 130 * CACR: Cache Control Register (2nd level cache) (cbd_cacr) 131 */ 132 #define CACR_CEN 0x00000010 /* Cache enable */ 133 #define CACR_CPE 0x00000020 /* Cache Parity Error */ 134 135 /* 136 * System Support Chip (SSC) registers 137 */ 138 struct ka650_ssc { 139 u_long ssc_sscbr; /* SSC Base Addr Register */ 140 u_long pad1[3]; 141 u_long ssc_ssccr; /* SSC Configuration Register */ 142 u_long pad2[3]; 143 u_long ssc_cbtcr; /* CDAL Bus Timeout Control Register */ 144 u_long pad3[55]; 145 u_long ssc_tcr0; /* timer control reg 0 */ 146 u_long ssc_tir0; /* timer interval reg 0 */ 147 u_long ssc_tnir0; /* timer next interval reg 0 */ 148 u_long ssc_tivr0; /* timer interrupt vector reg 0 */ 149 u_long ssc_tcr1; /* timer control reg 1 */ 150 u_long ssc_tir1; /* timer interval reg 1 */ 151 u_long ssc_tnir1; /* timer next interval reg 1 */ 152 u_long ssc_tivr1; /* timer interrupt vector reg 1 */ 153 u_long pad4[184]; 154 u_char ssc_cpmbx; /* Console Program Mail Box: Lang & Hact */ 155 u_char ssc_terminfo; /* TTY info: Video Dev, MCS, CRT & ROM flags */ 156 u_char ssc_keyboard; /* Keyboard code */ 157 }; 158 #define KA650_SSC 0x20140000 159 160 /* 161 * CBTCR: CDAL Bus Timeout Control Register (ssc_cbtcr) 162 */ 163 #define CBTCR_BTO 0x80000000 /* r/w unimp IPR or unack intr */ 164 #define CBTCR_RWT 0x40000000 /* CDAL Bus Timeout on CPU or DMA */ 165 166 /* 167 * TCR0/TCR1: Programable Timer Control Registers (ssc_tcr[01]) 168 * (The rest of the bits are the same as in the standard VAX 169 * Interval timer and are defined in clock.h) 170 */ 171 #define TCR_STP 0x00000004 /* Stop after time-out */ 172 173 /* 174 * Flags for Console Program Mail Box 175 */ 176 #define CPMB650_HALTACT 0x03 /* Field for halt action */ 177 #define CPMB650_RESTART 0x01 /* Restart */ 178 #define CPMB650_REBOOT 0x02 /* Reboot */ 179 #define CPMB650_HALT 0x03 /* Halt */ 180 #define CPMB650_BIP 0x04 /* Bootstrap in progress */ 181 #define CPMB650_RIP 0x08 /* Restart in progress */ 182 #define CPMB650_LANG 0xf0 /* Language field */ 183 184 /* 185 * Inter Processor Communication Register 186 * To determine if memory error was from QBUS device DMA (as opposed to cpu). 187 */ 188 struct ka650_ipcr { 189 u_long pad[80]; 190 u_short ipcr0; /* InterProcessor Comm Reg for arbiter */ 191 }; 192 #define KA650_IPCR 0x20001e00 193 194 #ifndef STANDALONE 195 /* 196 * External declarations of the map names (declared in spt.s) 197 * for the local register space. 198 */ 199 extern struct pte KA650MERRmap[]; 200 extern struct ka650_merr ka650merr; /* mem err & mem config regs */ 201 extern struct pte KA650CBDmap[]; 202 extern struct ka650_cbd ka650cbd; /* cache control & boot/diag regs */ 203 extern struct pte KA650SSCmap[]; 204 extern struct ka650_ssc ka650ssc; /* SSC regs (& console prog mail box) */ 205 extern struct pte KA650IPCRmap[]; 206 extern struct ka650_ipcr ka650ipcr; /* InterProcessor Com Regs */ 207 extern struct pte KA650CACHEmap[]; 208 extern int ka650cache[]; /* Cache Diagnostic space (for flush) */ 209 #endif STANDALONE 210 #endif LOCORE 211 212 /* 213 * Physical start address of the Qbus memory. 214 * The q-bus memory size is 4 meg. 215 * Physical start address of the I/O space (where the 8Kbyte I/O page is). 216 */ 217 #define KA650_QMEM 0x30000000 218 #define KA650_QMEMSIZE (512*8192) 219 #define KA650_QDEVADDR 0x20000000 220 221 /* 222 * Mapping info for Cache Entries, including 223 * Size (in bytes) of 2nd Level Cache for cache flush operation 224 */ 225 #define KA650_CACHE 0x10000000 226 #define KA650_CACHESIZE (64*1024) 227 228 /* 229 * Useful ROM addresses 230 */ 231 #define KA650ROM_SIDEX 0x20060004 /* system ID extension */ 232 #define KA650ROM_GETC 0x20060008 /* (jsb) get character from console */ 233 #define KA650ROM_PUTS 0x2006000c /* (jsb) put string to console */ 234 #define KA650ROM_GETS 0x20060010 /* (jsb) read string with prompt */ 235 #define KA650_CONSTYPE 0x20140401 /* byte at which console type resides */ 236 #endif 237