1 /* 2 * Copyright (c) 1988 Regents of the University of California. 3 * All rights reserved. The Berkeley software License Agreement 4 * specifies the terms and conditions for redistribution. 5 * 6 * @(#)ka650.h 7.2 (Berkeley) 09/22/88 7 */ 8 9 /* 10 * 11 * Definitions specific to the ka650 (uVAX 3600/3602) cpu card. 12 */ 13 14 #ifdef VAX650 15 /* 16 * CAER: Memory System Error Register (IPR 39) 17 */ 18 #define CAER_DAL 0x00000040 /* CDAL or level 2 cache data parity */ 19 #define CAER_MCD 0x00000020 /* mcheck due to DAL parity error */ 20 #define CAER_MCC 0x00000010 /* mcheck due to 1st lev cache parity */ 21 #define CAER_DAT 0x00000002 /* data parity in 1st level cache */ 22 #define CAER_TAG 0x00000001 /* tag parity in 1st level cache */ 23 24 /* 25 * CADR: Cache Disable Register (IPR 37) 26 */ 27 #define CADR_STMASK 0x000000f0 /* 1st level cache state mask */ 28 #define CADR_SEN2 0x00000080 /* 1st level cache set 2 enabled */ 29 #define CADR_SEN1 0x00000040 /* 1st level cache set 1 enabled */ 30 #define CADR_CENI 0x00000020 /* 1st level I-stream caching enabled */ 31 #define CADR_CEND 0x00000010 /* 1st level D-stream caching enabled */ 32 33 /* 34 * Internal State Info 2: (for mcheck recovery) 35 */ 36 #define IS2_VCR 0x00008000 /* VAX Can't Restart flag */ 37 38 /* 39 * DMA System Error Register (merr_dser) 40 */ 41 #define DSER_QNXM 0x00000080 /* Q-22 Bus NXM */ 42 #define DSER_QPE 0x00000020 /* Q-22 Bus parity Error */ 43 #define DSER_MEM 0x00000010 /* Main mem err due to ext dev DMA */ 44 #define DSER_LOST 0x00000008 /* Lost error: DSER <7,5,4,0> set */ 45 #define DSER_NOGRANT 0x00000004 /* No Grant timeout on cpu demand R/W */ 46 #define DSER_DNXM 0x00000001 /* DMA NXM */ 47 #define DSER_CLEAR (DSER_QNXM | DSER_QPE | DSER_MEM | \ 48 DSER_LOST | DSER_NOGRANT | DSER_DNXM) 49 #define DMASER_BITS \ 50 "\20\20BHALT\17DCNEG\10QBNXM\6QBPE\5MEMERR\4LOSTERR\3NOGRANT\1DMANXM" 51 52 #ifndef LOCORE 53 /* 54 * Local registers (in I/O space) 55 * This is done in disjoint sections. Map names are set in locore.s 56 * and they are mapped in routine configcpu() 57 */ 58 59 /* 60 * memory error & configuration registers 61 */ 62 struct ka650_merr { 63 u_long merr_scr; /* System Config Register */ 64 u_long merr_dser; /* DMA System Error Register */ 65 u_long merr_qbear; /* QBus Error Address Register */ 66 u_long merr_dear; /* DMA Error Address Register */ 67 u_long merr_qbmbr; /* Q Bus Map Base address Register */ 68 u_long pad[59]; 69 u_long merr_csr[16]; /* Main Memory Config Regs (16 banks) */ 70 u_long merr_errstat; /* Main Memory Error Status */ 71 u_long merr_cont; /* Main Memory Control */ 72 }; 73 #define KA650_MERR 0x20080000 74 75 /* 76 * Main Memory Error Status Register (merr_errstat) 77 */ 78 #define MEM_EMASK 0xe0000180 /* mask of all err bits */ 79 #define MEM_RDS 0x80000000 /* uncorrectable main memory */ 80 #define MEM_RDSHIGH 0x40000000 /* high rate RDS errors */ 81 #define MEM_CRD 0x20000000 /* correctable main memory */ 82 #define MEM_DMA 0x00000100 /* DMA read or write error */ 83 #define MEM_CDAL 0x00000080 /* CDAL Parity error on write */ 84 #define MEM_PAGE 0x1ffffe00 /* Offending Page Number */ 85 #define MEM_PAGESHFT 9 /* Shift to normalize page number */ 86 87 /* 88 * Main Memory Control & Diag Status Reg (merr_cont) 89 */ 90 #define MEM_CRDINT 0x00001000 /* CRD interrupts enabled */ 91 #define MEM_REFRESH 0x00000800 /* Forced memory refresh */ 92 #define MEM_ERRDIS 0x00000400 /* error detect disable */ 93 #define MEM_DIAG 0x00000080 /* Diagnostics mode */ 94 #define MEM_CHECK 0x0000007f /* check bits for diagnostic mode */ 95 96 /* 97 * Main Memory Config Regs (merr_csr[0-15]) 98 */ 99 #define MEM_BNKENBLE 0x80000000 /* Bank Enable */ 100 #define MEM_BNKNUM 0x03c00000 /* Physical map Bank number */ 101 #define MEM_BNKUSAGE 0x00000003 /* Bank Usage */ 102 103 /* 104 * Cache Control & Boot/Diag registers 105 */ 106 struct ka650_cbd { 107 u_char cbd_cacr; /* Low byte: Cache Enable & Parity Err detect */ 108 u_char cbd_cdf1; /* Cache diagnostic field (unused) */ 109 u_char cbd_cdf2; /* Cache diagnostic field (unused) */ 110 u_char pad; 111 u_long cbd_bdr; /* Boot & Diagnostic Register (unused) */ 112 }; 113 #define KA650_CBD 0x20084000 114 115 /* 116 * CACR: Cache Control Register (2nd level cache) (cbd_cacr) 117 */ 118 #define CACR_CEN 0x00000010 /* Cache enable */ 119 #define CACR_CPE 0x00000020 /* Cache Parity Error */ 120 121 /* 122 * System Support Chip (SSC) registers 123 */ 124 struct ka650_ssc { 125 u_long ssc_sscbr; /* SSC Base Addr Register */ 126 u_long pad1[3]; 127 u_long ssc_ssccr; /* SSC Configuration Register */ 128 u_long pad2[3]; 129 u_long ssc_cbtcr; /* CDAL Bus Timeout Control Register */ 130 u_long pad3[55]; 131 u_long ssc_tcr0; /* timer control reg 0 */ 132 u_long ssc_tir0; /* timer interval reg 0 */ 133 u_long ssc_tnir0; /* timer next interval reg 0 */ 134 u_long ssc_tivr0; /* timer interrupt vector reg 0 */ 135 u_long ssc_tcr1; /* timer control reg 1 */ 136 u_long ssc_tir1; /* timer interval reg 1 */ 137 u_long ssc_tnir1; /* timer next interval reg 1 */ 138 u_long ssc_tivr1; /* timer interrupt vector reg 1 */ 139 u_long pad4[184]; 140 u_char ssc_cpmbx; /* Console Program Mail Box: Lang & Hact */ 141 u_char ssc_terminfo; /* TTY info: Video Dev, MCS, CRT & ROM flags */ 142 u_char ssc_keyboard; /* Keyboard code */ 143 }; 144 #define KA650_SSC 0x20140000 145 146 /* 147 * CBTCR: CDAL Bus Timeout Control Register (ssc_cbtcr) 148 */ 149 #define CBTCR_BTO 0x80000000 /* r/w unimp IPR or unack intr */ 150 #define CBTCR_RWT 0x40000000 /* CDAL Bus Timeout on CPU or DMA */ 151 152 /* 153 * TCR0/TCR1: Programable Timer Control Registers (ssc_tcr[01]) 154 * (The rest of the bits are the same as in the standard VAX 155 * Interval timer and are defined in clock.h) 156 */ 157 #define TCR_STP 0x00000004 /* Stop after time-out */ 158 159 /* 160 * Flags for Console Program Mail Box 161 */ 162 #define CPMB650_HALTACT 0x03 /* Field for halt action */ 163 #define CPMB650_RESTART 0x01 /* Restart */ 164 #define CPMB650_REBOOT 0x02 /* Reboot */ 165 #define CPMB650_HALT 0x03 /* Halt */ 166 #define CPMB650_BIP 0x04 /* Bootstrap in progress */ 167 #define CPMB650_RIP 0x08 /* Restart in progress */ 168 #define CPMB650_LANG 0xf0 /* Language field */ 169 170 /* 171 * Inter Processor Communication Register 172 * To determine if memory error was from QBUS device DMA (as opposed to cpu). 173 */ 174 struct ka650_ipcr { 175 u_long pad[80]; 176 u_short ipcr0; /* InterProcessor Comm Reg for arbiter */ 177 }; 178 #define KA650_IPCR 0x20001e00 179 180 #ifndef STANDALONE 181 /* 182 * External declarations of the map names (declared in spt.s) 183 * for the local register space. 184 */ 185 extern struct pte KA650MERRmap[]; 186 extern struct ka650_merr ka650merr; /* mem err & mem config regs */ 187 extern struct pte KA650CBDmap[]; 188 extern struct ka650_cbd ka650cbd; /* cache control & boot/diag regs */ 189 extern struct pte KA650SSCmap[]; 190 extern struct ka650_ssc ka650ssc; /* SSC regs (& console prog mail box) */ 191 extern struct pte KA650IPCRmap[]; 192 extern struct ka650_ipcr ka650ipcr; /* InterProcessor Com Regs */ 193 extern struct pte KA650CACHEmap[]; 194 extern int ka650cache[]; /* Cache Diagnostic space (for flush) */ 195 #endif STANDALONE 196 #endif LOCORE 197 198 /* 199 * Physical start address of the Qbus memory. 200 * The q-bus memory size is 4 meg. 201 * Physical start address of the I/O space (where the 8Kbyte I/O page is). 202 */ 203 #define KA650_QMEM 0x30000000 204 #define KA650_QMEMSIZE (512*8192) 205 #define KA650_QDEVADDR 0x20000000 206 207 /* 208 * Mapping info for Cache Entries, including 209 * Size (in bytes) of 2nd Level Cache for cache flush operation 210 */ 211 #define KA650_CACHE 0x10000000 212 #define KA650_CACHESIZE (64*1024) 213 214 /* 215 * Useful ROM addresses 216 */ 217 #define KA650ROM_SIDEX 0x20060004 /* system ID extension */ 218 #define KA650ROM_GETC 0x20060008 /* (jsb) get character from console */ 219 #define KA650ROM_PUTS 0x2006000c /* (jsb) put string to console */ 220 #define KA650ROM_GETS 0x20060010 /* (jsb) read string with prompt */ 221 #define KA650_CONSTYPE 0x20140401 /* byte at which console type resides */ 222 #endif 223