1 /* 2 * Copyright (c) 1988 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Chris Torek. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)ka820.h 7.3 (Berkeley) 06/28/90 11 */ 12 13 /* 14 * Definitions specific to the ka820 cpu. 15 */ 16 17 #if VAX8200 18 19 /* 20 * Device addresses. 21 */ 22 #define KA820_PORTADDR 0x20088000 /* port controller */ 23 #define KA820_BRAMADDR 0x20090000 /* boot ram */ 24 #define KA820_EEPROMADDR 0x20098000 /* eeprom */ 25 #define KA820_RX50ADDR 0x200b0000 /* rcx50 */ 26 #define KA820_CLOCKADDR 0x200b8000 /* watch chip */ 27 28 /* 29 * Sizes. The port controller, RCX50, and watch chip are all one page. 30 */ 31 #define KA820_BRPAGES 16 /* 8K */ 32 #define KA820_EEPAGES 64 /* 32K */ 33 34 /* port controller CSR bit values */ 35 #define KA820PORT_RSTHALT 0x80000000 /* restart halt */ 36 #define KA820PORT_LCONS 0x40000000 /* logical console */ 37 #define KA820PORT_LCONSEN 0x20000000 /* logical console enable */ 38 #define KA820PORT_BIRESET 0x10000000 /* BI reset */ 39 #define KA820PORT_BISTF 0x08000000 /* ??? */ 40 #define KA820PORT_ENBAPT 0x04000000 /* ??? */ 41 #define KA820PORT_STPASS 0x02000000 /* self test pass */ 42 #define KA820PORT_RUN 0x01000000 /* run */ 43 #define KA820PORT_WWPE 0x00800000 /* ??? parity even? */ 44 #define KA820PORT_EVLCK 0x00400000 /* event lock */ 45 #define KA820PORT_WMEM 0x00200000 /* write mem */ 46 #define KA820PORT_EV4 0x00100000 /* event 4 */ 47 #define KA820PORT_EV3 0x00080000 /* event 3 */ 48 #define KA820PORT_EV2 0x00040000 /* event 2 */ 49 #define KA820PORT_EV1 0x00020000 /* event 1 */ 50 #define KA820PORT_EV0 0x00010000 /* event 0 */ 51 #define KA820PORT_WWPO 0x00008000 /* ??? parity odd? */ 52 #define KA820PORT_PERH 0x00004000 /* parity error H */ 53 #define KA820PORT_ENBPIPE 0x00002000 /* enable? pipe */ 54 #define KA820PORT_TIMEOUT 0x00001000 /* timeout */ 55 #define KA820PORT_RSVD 0x00000800 /* reserved */ 56 #define KA820PORT_CONSEN 0x00000400 /* console interrupt enable */ 57 #define KA820PORT_CONSCLR 0x00000200 /* clear console interrupt */ 58 #define KA820PORT_CONSINTR 0x00000100 /* console interrupt req */ 59 #define KA820PORT_RXIE 0x00000080 /* RX50 interrupt enable */ 60 #define KA820PORT_RXCLR 0x00000040 /* clear RX50 interrupt */ 61 #define KA820PORT_RXIRQ 0x00000020 /* RX50 interrupt request */ 62 #define KA820PORT_IPCLR 0x00000010 /* clear IP interrupt */ 63 #define KA820PORT_IPINTR 0x00000008 /* IP interrupt request */ 64 #define KA820PORT_CRDEN 0x00000004 /* enable CRD interrupts */ 65 #define KA820PORT_CRDCLR 0x00000002 /* clear CRD interrupt */ 66 #define KA820PORT_CRDINTR 0x00000001 /* CRD interrupt request */ 67 68 /* what the heck */ 69 #define KA820PORT_BITS \ 70 "\20\40RSTHALT\37LCONS\36LCONSEN\35BIRESET\34BISTF\33ENBAPT\32STPASS\31RUN\ 71 \30WWPE\27EVLCK\26WMEM\25EV4\24EV3\23EV2\22EV1\21EV\20WWPO\17PERH\16ENBPIPE\ 72 \15TIMEOUT\13CONSEN\12CONSCLR\11CONSINTR\10RXIE\7RXCLR\6RXIRQ\5IPCLR\4IPINTR\ 73 \3CRDEN\2CLRCLR\1CRDINTR" 74 75 /* clock CSR bit values, per csr */ 76 #define KA820CLK_0_BUSY 0x01 /* busy (time changing) */ 77 #define KA820CLK_1_GO 0x0c /* run */ 78 #define KA820CLK_1_SET 0x0d /* set the time */ 79 #define KA820CLK_3_VALID 0x01 /* clock is valid */ 80 81 #ifndef LOCORE 82 struct ka820port { 83 u_long csr; 84 /* that seems to be all.... */ 85 }; 86 87 struct ka820clock { 88 u_char sec; 89 u_char pad0; 90 u_char secalrm; 91 u_char pad1; 92 u_char min; 93 u_char pad2; 94 u_char minalrm; 95 u_char pad3; 96 u_char hr; 97 u_char pad4; 98 u_char hralrm; 99 u_char pad5; 100 u_char dayofwk; 101 u_char pad6; 102 u_char day; 103 u_char pad7; 104 u_char mon; 105 u_char pad8; 106 u_char yr; 107 u_char pad9; 108 u_short csr0; 109 u_short csr1; 110 u_short csr2; 111 u_short csr3; 112 }; 113 #endif 114 #endif 115