1 /* 2 * @(#)ka820.h 7.1 (Berkeley) 05/21/88 3 * 4 * Definitions specific to the ka820 cpu. 5 */ 6 7 #if VAX8200 8 9 /* 10 * Device addresses. 11 */ 12 #define KA820_PORTADDR 0x20088000 /* port controller */ 13 #define KA820_BRAMADDR 0x20090000 /* boot ram */ 14 #define KA820_EEPROMADDR 0x20098000 /* eeprom */ 15 #define KA820_RX50ADDR 0x200b0000 /* rcx50 */ 16 #define KA820_CLOCKADDR 0x200b8000 /* watch chip */ 17 18 /* 19 * Sizes. The port controller, RCX50, and watch chip are all one page. 20 */ 21 #define KA820_BRPAGES 16 /* 8K */ 22 #define KA820_EEPAGES 64 /* 32K */ 23 24 /* port controller CSR bit values */ 25 #define KA820PORT_RSTHALT 0x80000000 /* restart halt */ 26 #define KA820PORT_LCONS 0x40000000 /* logical console */ 27 #define KA820PORT_LCONSEN 0x20000000 /* logical console enable */ 28 #define KA820PORT_BIRESET 0x10000000 /* BI reset */ 29 #define KA820PORT_BISTF 0x08000000 /* ??? */ 30 #define KA820PORT_ENBAPT 0x04000000 /* ??? */ 31 #define KA820PORT_STPASS 0x02000000 /* self test pass */ 32 #define KA820PORT_RUN 0x01000000 /* run */ 33 #define KA820PORT_WWPE 0x00800000 /* ??? parity even? */ 34 #define KA820PORT_EVLCK 0x00400000 /* event lock */ 35 #define KA820PORT_WMEM 0x00200000 /* write mem */ 36 #define KA820PORT_EV4 0x00100000 /* event 4 */ 37 #define KA820PORT_EV3 0x00080000 /* event 3 */ 38 #define KA820PORT_EV2 0x00040000 /* event 2 */ 39 #define KA820PORT_EV1 0x00020000 /* event 1 */ 40 #define KA820PORT_EV0 0x00010000 /* event 0 */ 41 #define KA820PORT_WWPO 0x00008000 /* ??? parity odd? */ 42 #define KA820PORT_PERH 0x00004000 /* parity error H */ 43 #define KA820PORT_ENBPIPE 0x00002000 /* enable? pipe */ 44 #define KA820PORT_TIMEOUT 0x00001000 /* timeout */ 45 #define KA820PORT_RSVD 0x00000800 /* reserved */ 46 #define KA820PORT_CONSEN 0x00000400 /* console interrupt enable */ 47 #define KA820PORT_CONSCLR 0x00000200 /* clear console interrupt */ 48 #define KA820PORT_CONSINTR 0x00000100 /* console interrupt req */ 49 #define KA820PORT_RXIE 0x00000080 /* RX50 interrupt enable */ 50 #define KA820PORT_RXCLR 0x00000040 /* clear RX50 interrupt */ 51 #define KA820PORT_RXIRQ 0x00000020 /* RX50 interrupt request */ 52 #define KA820PORT_IPCLR 0x00000010 /* clear IP interrupt */ 53 #define KA820PORT_IPINTR 0x00000008 /* IP interrupt request */ 54 #define KA820PORT_CRDEN 0x00000004 /* enable CRD interrupts */ 55 #define KA820PORT_CRDCLR 0x00000002 /* clear CRD interrupt */ 56 #define KA820PORT_CRDINTR 0x00000001 /* CRD interrupt request */ 57 58 /* what the heck */ 59 #define KA820PORT_BITS \ 60 "\20\40RSTHALT\37LCONS\36LCONSEN\35BIRESET\34BISTF\33ENBAPT\32STPASS\31RUN\ 61 \30WWPE\27EVLCK\26WMEM\25EV4\24EV3\23EV2\22EV1\21EV\20WWPO\17PERH\16ENBPIPE\ 62 \15TIMEOUT\13CONSEN\12CONSCLR\11CONSINTR\10RXIE\7RXCLR\6RXIRQ\5IPCLR\4IPINTR\ 63 \3CRDEN\2CLRCLR\1CRDINTR" 64 65 /* clock CSR bit values, per csr */ 66 #define KA820CLK_0_BUSY 0x01 /* busy (time changing) */ 67 #define KA820CLK_1_GO 0x0c /* run */ 68 #define KA820CLK_1_SET 0x0d /* set the time */ 69 #define KA820CLK_3_VALID 0x01 /* clock is valid */ 70 71 #ifndef LOCORE 72 struct ka820port { 73 u_long csr; 74 /* that seems to be all.... */ 75 }; 76 77 struct ka820clock { 78 u_char sec; 79 u_char pad0; 80 u_char secalrm; 81 u_char pad1; 82 u_char min; 83 u_char pad2; 84 u_char minalrm; 85 u_char pad3; 86 u_char hr; 87 u_char pad4; 88 u_char hralrm; 89 u_char pad5; 90 u_char dayofwk; 91 u_char pad6; 92 u_char day; 93 u_char pad7; 94 u_char mon; 95 u_char pad8; 96 u_char yr; 97 u_char pad9; 98 u_short csr0; 99 u_short csr1; 100 u_short csr2; 101 u_short csr3; 102 }; 103 #endif 104 #endif 105