1/* scb.s 4.14 82/03/19 */ 2 3/* 4 * System control block 5 */ 6 .set INTSTK,1 # handle this interrupt on the interrupt stack 7 .set HALT,3 # halt if this interrupt occurs 8 9_scb: .globl _scb 10 11#define STRAY .long _Xstray+INTSTK 12#define STRAY8 STRAY;STRAY;STRAY;STRAY;STRAY;STRAY;STRAY;STRAY 13#define STRAY15 STRAY;STRAY;STRAY;STRAY;STRAY;STRAY;STRAY;STRAY8 14#define KS(a) .long _X/**/a 15#define IS(a) .long _X/**/a+INTSTK 16#define STOP(a) .long _X/**/a+HALT 17 18/* 000 */ STRAY; IS(machcheck); IS(kspnotval); STOP(powfail); 19/* 010 */ KS(privinflt); KS(xfcflt); KS(resopflt); KS(resadflt); 20/* 020 */ KS(protflt); KS(transflt); KS(tracep); KS(bptflt); 21/* 030 */ KS(compatflt); KS(arithtrap); STRAY; STRAY; 22/* 040 */ KS(syscall); KS(chme); KS(chms); KS(chmu); 23/* 050 */ STRAY; IS(cmrd); STRAY; STRAY; 24/* 060 */ IS(wtime); STRAY; STRAY; STRAY; 25/* 070 */ STRAY; STRAY; STRAY; STRAY; 26/* 080 */ STRAY; STRAY; KS(astflt); STRAY; 27/* 090 */ STRAY; STRAY; STRAY; STRAY; 28/* 0a0 */ IS(softclock); STRAY; STRAY; STRAY; 29/* 0b0 */ IS(netintr); STRAY; STRAY; STRAY; 30/* 0c0 */ IS(hardclock); STRAY; STRAY; STRAY; 31/* 0d0 */ STRAY; STRAY; STRAY; STRAY; 32/* 0e0 */ STRAY; STRAY; STRAY; STRAY; 33/* 0f0 */ IS(consdin); IS(consdout); IS(cnrint); IS(cnxint); 34/* 100 */ IS(nexzvec); STRAY15; /* ipl 0x14, nexus 0-15 */ 35/* 140 */ IS(nexzvec); STRAY15; /* ipl 0x15, nexus 0-15 */ 36/* 180 */ IS(nexzvec); STRAY15; /* ipl 0x16, nexus 0-15 */ 37/* 1c0 */ IS(nexzvec); STRAY15; /* ipl 0x17, nexus 0-15 */ 38 39 .globl _UNIvec 40_UNIvec: .space 512 # 750 unibus intr vector 41 # 1st UBA jump table on 780's 42