1 /* 2 * User emulator execution 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "hw/core/tcg-cpu-ops.h" 21 #include "disas/disas.h" 22 #include "exec/exec-all.h" 23 #include "tcg/tcg.h" 24 #include "qemu/bitops.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/translate-all.h" 27 #include "exec/helper-proto.h" 28 #include "qemu/atomic128.h" 29 #include "trace/trace-root.h" 30 #include "trace/mem.h" 31 32 #undef EAX 33 #undef ECX 34 #undef EDX 35 #undef EBX 36 #undef ESP 37 #undef EBP 38 #undef ESI 39 #undef EDI 40 #undef EIP 41 #ifdef __linux__ 42 #include <sys/ucontext.h> 43 #endif 44 45 __thread uintptr_t helper_retaddr; 46 47 //#define DEBUG_SIGNAL 48 49 /* exit the current TB from a signal handler. The host registers are 50 restored in a state compatible with the CPU emulator 51 */ 52 static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, 53 sigset_t *old_set) 54 { 55 /* XXX: use siglongjmp ? */ 56 sigprocmask(SIG_SETMASK, old_set, NULL); 57 cpu_loop_exit_noexc(cpu); 58 } 59 60 /* 'pc' is the host PC at which the exception was raised. 'address' is 61 the effective address of the memory exception. 'is_write' is 1 if a 62 write caused the exception and otherwise 0'. 'old_set' is the 63 signal set which should be restored */ 64 static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, 65 int is_write, sigset_t *old_set) 66 { 67 CPUState *cpu = current_cpu; 68 CPUClass *cc; 69 unsigned long address = (unsigned long)info->si_addr; 70 MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; 71 72 switch (helper_retaddr) { 73 default: 74 /* 75 * Fault during host memory operation within a helper function. 76 * The helper's host return address, saved here, gives us a 77 * pointer into the generated code that will unwind to the 78 * correct guest pc. 79 */ 80 pc = helper_retaddr; 81 break; 82 83 case 0: 84 /* 85 * Fault during host memory operation within generated code. 86 * (Or, a unrelated bug within qemu, but we can't tell from here). 87 * 88 * We take the host pc from the signal frame. However, we cannot 89 * use that value directly. Within cpu_restore_state_from_tb, we 90 * assume PC comes from GETPC(), as used by the helper functions, 91 * so we adjust the address by -GETPC_ADJ to form an address that 92 * is within the call insn, so that the address does not accidentally 93 * match the beginning of the next guest insn. However, when the 94 * pc comes from the signal frame it points to the actual faulting 95 * host memory insn and not the return from a call insn. 96 * 97 * Therefore, adjust to compensate for what will be done later 98 * by cpu_restore_state_from_tb. 99 */ 100 pc += GETPC_ADJ; 101 break; 102 103 case 1: 104 /* 105 * Fault during host read for translation, or loosely, "execution". 106 * 107 * The guest pc is already pointing to the start of the TB for which 108 * code is being generated. If the guest translator manages the 109 * page crossings correctly, this is exactly the correct address 110 * (and if the translator doesn't handle page boundaries correctly 111 * there's little we can do about that here). Therefore, do not 112 * trigger the unwinder. 113 * 114 * Like tb_gen_code, release the memory lock before cpu_loop_exit. 115 */ 116 pc = 0; 117 access_type = MMU_INST_FETCH; 118 mmap_unlock(); 119 break; 120 } 121 122 /* For synchronous signals we expect to be coming from the vCPU 123 * thread (so current_cpu should be valid) and either from running 124 * code or during translation which can fault as we cross pages. 125 * 126 * If neither is true then something has gone wrong and we should 127 * abort rather than try and restart the vCPU execution. 128 */ 129 if (!cpu || !cpu->running) { 130 printf("qemu:%s received signal outside vCPU context @ pc=0x%" 131 PRIxPTR "\n", __func__, pc); 132 abort(); 133 } 134 135 #if defined(DEBUG_SIGNAL) 136 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 137 pc, address, is_write, *(unsigned long *)old_set); 138 #endif 139 /* XXX: locking issue */ 140 /* Note that it is important that we don't call page_unprotect() unless 141 * this is really a "write to nonwriteable page" fault, because 142 * page_unprotect() assumes that if it is called for an access to 143 * a page that's writeable this means we had two threads racing and 144 * another thread got there first and already made the page writeable; 145 * so we will retry the access. If we were to call page_unprotect() 146 * for some other kind of fault that should really be passed to the 147 * guest, we'd end up in an infinite loop of retrying the faulting 148 * access. 149 */ 150 if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR && 151 h2g_valid(address)) { 152 switch (page_unprotect(h2g(address), pc)) { 153 case 0: 154 /* Fault not caused by a page marked unwritable to protect 155 * cached translations, must be the guest binary's problem. 156 */ 157 break; 158 case 1: 159 /* Fault caused by protection of cached translation; TBs 160 * invalidated, so resume execution. Retain helper_retaddr 161 * for a possible second fault. 162 */ 163 return 1; 164 case 2: 165 /* Fault caused by protection of cached translation, and the 166 * currently executing TB was modified and must be exited 167 * immediately. Clear helper_retaddr for next execution. 168 */ 169 clear_helper_retaddr(); 170 cpu_exit_tb_from_sighandler(cpu, old_set); 171 /* NORETURN */ 172 173 default: 174 g_assert_not_reached(); 175 } 176 } 177 178 /* Convert forcefully to guest address space, invalid addresses 179 are still valid segv ones */ 180 address = h2g_nocheck(address); 181 182 /* 183 * There is no way the target can handle this other than raising 184 * an exception. Undo signal and retaddr state prior to longjmp. 185 */ 186 sigprocmask(SIG_SETMASK, old_set, NULL); 187 clear_helper_retaddr(); 188 189 cc = CPU_GET_CLASS(cpu); 190 cc->tcg_ops->tlb_fill(cpu, address, 0, access_type, 191 MMU_USER_IDX, false, pc); 192 g_assert_not_reached(); 193 } 194 195 static int probe_access_internal(CPUArchState *env, target_ulong addr, 196 int fault_size, MMUAccessType access_type, 197 bool nonfault, uintptr_t ra) 198 { 199 int flags; 200 201 switch (access_type) { 202 case MMU_DATA_STORE: 203 flags = PAGE_WRITE; 204 break; 205 case MMU_DATA_LOAD: 206 flags = PAGE_READ; 207 break; 208 case MMU_INST_FETCH: 209 flags = PAGE_EXEC; 210 break; 211 default: 212 g_assert_not_reached(); 213 } 214 215 if (!guest_addr_valid_untagged(addr) || 216 page_check_range(addr, 1, flags) < 0) { 217 if (nonfault) { 218 return TLB_INVALID_MASK; 219 } else { 220 CPUState *cpu = env_cpu(env); 221 CPUClass *cc = CPU_GET_CLASS(cpu); 222 cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type, 223 MMU_USER_IDX, false, ra); 224 g_assert_not_reached(); 225 } 226 } 227 return 0; 228 } 229 230 int probe_access_flags(CPUArchState *env, target_ulong addr, 231 MMUAccessType access_type, int mmu_idx, 232 bool nonfault, void **phost, uintptr_t ra) 233 { 234 int flags; 235 236 flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra); 237 *phost = flags ? NULL : g2h(env_cpu(env), addr); 238 return flags; 239 } 240 241 void *probe_access(CPUArchState *env, target_ulong addr, int size, 242 MMUAccessType access_type, int mmu_idx, uintptr_t ra) 243 { 244 int flags; 245 246 g_assert(-(addr | TARGET_PAGE_MASK) >= size); 247 flags = probe_access_internal(env, addr, size, access_type, false, ra); 248 g_assert(flags == 0); 249 250 return size ? g2h(env_cpu(env), addr) : NULL; 251 } 252 253 #if defined(__i386__) 254 255 #if defined(__NetBSD__) 256 #include <ucontext.h> 257 258 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) 259 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 260 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 261 #define MASK_sig(context) ((context)->uc_sigmask) 262 #elif defined(__FreeBSD__) || defined(__DragonFly__) 263 #include <ucontext.h> 264 265 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) 266 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 267 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 268 #define MASK_sig(context) ((context)->uc_sigmask) 269 #elif defined(__OpenBSD__) 270 #define EIP_sig(context) ((context)->sc_eip) 271 #define TRAP_sig(context) ((context)->sc_trapno) 272 #define ERROR_sig(context) ((context)->sc_err) 273 #define MASK_sig(context) ((context)->sc_mask) 274 #else 275 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) 276 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 277 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 278 #define MASK_sig(context) ((context)->uc_sigmask) 279 #endif 280 281 int cpu_signal_handler(int host_signum, void *pinfo, 282 void *puc) 283 { 284 siginfo_t *info = pinfo; 285 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 286 ucontext_t *uc = puc; 287 #elif defined(__OpenBSD__) 288 struct sigcontext *uc = puc; 289 #else 290 ucontext_t *uc = puc; 291 #endif 292 unsigned long pc; 293 int trapno; 294 295 #ifndef REG_EIP 296 /* for glibc 2.1 */ 297 #define REG_EIP EIP 298 #define REG_ERR ERR 299 #define REG_TRAPNO TRAPNO 300 #endif 301 pc = EIP_sig(uc); 302 trapno = TRAP_sig(uc); 303 return handle_cpu_signal(pc, info, 304 trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 305 &MASK_sig(uc)); 306 } 307 308 #elif defined(__x86_64__) 309 310 #ifdef __NetBSD__ 311 #define PC_sig(context) _UC_MACHINE_PC(context) 312 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 313 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 314 #define MASK_sig(context) ((context)->uc_sigmask) 315 #elif defined(__OpenBSD__) 316 #define PC_sig(context) ((context)->sc_rip) 317 #define TRAP_sig(context) ((context)->sc_trapno) 318 #define ERROR_sig(context) ((context)->sc_err) 319 #define MASK_sig(context) ((context)->sc_mask) 320 #elif defined(__FreeBSD__) || defined(__DragonFly__) 321 #include <ucontext.h> 322 323 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) 324 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 325 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 326 #define MASK_sig(context) ((context)->uc_sigmask) 327 #else 328 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) 329 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 330 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 331 #define MASK_sig(context) ((context)->uc_sigmask) 332 #endif 333 334 int cpu_signal_handler(int host_signum, void *pinfo, 335 void *puc) 336 { 337 siginfo_t *info = pinfo; 338 unsigned long pc; 339 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 340 ucontext_t *uc = puc; 341 #elif defined(__OpenBSD__) 342 struct sigcontext *uc = puc; 343 #else 344 ucontext_t *uc = puc; 345 #endif 346 347 pc = PC_sig(uc); 348 return handle_cpu_signal(pc, info, 349 TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 350 &MASK_sig(uc)); 351 } 352 353 #elif defined(_ARCH_PPC) 354 355 /*********************************************************************** 356 * signal context platform-specific definitions 357 * From Wine 358 */ 359 #ifdef linux 360 /* All Registers access - only for local access */ 361 #define REG_sig(reg_name, context) \ 362 ((context)->uc_mcontext.regs->reg_name) 363 /* Gpr Registers access */ 364 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) 365 /* Program counter */ 366 #define IAR_sig(context) REG_sig(nip, context) 367 /* Machine State Register (Supervisor) */ 368 #define MSR_sig(context) REG_sig(msr, context) 369 /* Count register */ 370 #define CTR_sig(context) REG_sig(ctr, context) 371 /* User's integer exception register */ 372 #define XER_sig(context) REG_sig(xer, context) 373 /* Link register */ 374 #define LR_sig(context) REG_sig(link, context) 375 /* Condition register */ 376 #define CR_sig(context) REG_sig(ccr, context) 377 378 /* Float Registers access */ 379 #define FLOAT_sig(reg_num, context) \ 380 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) 381 #define FPSCR_sig(context) \ 382 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) 383 /* Exception Registers access */ 384 #define DAR_sig(context) REG_sig(dar, context) 385 #define DSISR_sig(context) REG_sig(dsisr, context) 386 #define TRAP_sig(context) REG_sig(trap, context) 387 #endif /* linux */ 388 389 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 390 #include <ucontext.h> 391 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) 392 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) 393 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) 394 #define XER_sig(context) ((context)->uc_mcontext.mc_xer) 395 #define LR_sig(context) ((context)->uc_mcontext.mc_lr) 396 #define CR_sig(context) ((context)->uc_mcontext.mc_cr) 397 /* Exception Registers access */ 398 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar) 399 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) 400 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) 401 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */ 402 403 int cpu_signal_handler(int host_signum, void *pinfo, 404 void *puc) 405 { 406 siginfo_t *info = pinfo; 407 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 408 ucontext_t *uc = puc; 409 #else 410 ucontext_t *uc = puc; 411 #endif 412 unsigned long pc; 413 int is_write; 414 415 pc = IAR_sig(uc); 416 is_write = 0; 417 #if 0 418 /* ppc 4xx case */ 419 if (DSISR_sig(uc) & 0x00800000) { 420 is_write = 1; 421 } 422 #else 423 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { 424 is_write = 1; 425 } 426 #endif 427 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 428 } 429 430 #elif defined(__alpha__) 431 432 int cpu_signal_handler(int host_signum, void *pinfo, 433 void *puc) 434 { 435 siginfo_t *info = pinfo; 436 ucontext_t *uc = puc; 437 uint32_t *pc = uc->uc_mcontext.sc_pc; 438 uint32_t insn = *pc; 439 int is_write = 0; 440 441 /* XXX: need kernel patch to get write flag faster */ 442 switch (insn >> 26) { 443 case 0x0d: /* stw */ 444 case 0x0e: /* stb */ 445 case 0x0f: /* stq_u */ 446 case 0x24: /* stf */ 447 case 0x25: /* stg */ 448 case 0x26: /* sts */ 449 case 0x27: /* stt */ 450 case 0x2c: /* stl */ 451 case 0x2d: /* stq */ 452 case 0x2e: /* stl_c */ 453 case 0x2f: /* stq_c */ 454 is_write = 1; 455 } 456 457 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 458 } 459 #elif defined(__sparc__) 460 461 int cpu_signal_handler(int host_signum, void *pinfo, 462 void *puc) 463 { 464 siginfo_t *info = pinfo; 465 int is_write; 466 uint32_t insn; 467 #if !defined(__arch64__) || defined(CONFIG_SOLARIS) 468 uint32_t *regs = (uint32_t *)(info + 1); 469 void *sigmask = (regs + 20); 470 /* XXX: is there a standard glibc define ? */ 471 unsigned long pc = regs[1]; 472 #else 473 #ifdef __linux__ 474 struct sigcontext *sc = puc; 475 unsigned long pc = sc->sigc_regs.tpc; 476 void *sigmask = (void *)sc->sigc_mask; 477 #elif defined(__OpenBSD__) 478 struct sigcontext *uc = puc; 479 unsigned long pc = uc->sc_pc; 480 void *sigmask = (void *)(long)uc->sc_mask; 481 #elif defined(__NetBSD__) 482 ucontext_t *uc = puc; 483 unsigned long pc = _UC_MACHINE_PC(uc); 484 void *sigmask = (void *)&uc->uc_sigmask; 485 #endif 486 #endif 487 488 /* XXX: need kernel patch to get write flag faster */ 489 is_write = 0; 490 insn = *(uint32_t *)pc; 491 if ((insn >> 30) == 3) { 492 switch ((insn >> 19) & 0x3f) { 493 case 0x05: /* stb */ 494 case 0x15: /* stba */ 495 case 0x06: /* sth */ 496 case 0x16: /* stha */ 497 case 0x04: /* st */ 498 case 0x14: /* sta */ 499 case 0x07: /* std */ 500 case 0x17: /* stda */ 501 case 0x0e: /* stx */ 502 case 0x1e: /* stxa */ 503 case 0x24: /* stf */ 504 case 0x34: /* stfa */ 505 case 0x27: /* stdf */ 506 case 0x37: /* stdfa */ 507 case 0x26: /* stqf */ 508 case 0x36: /* stqfa */ 509 case 0x25: /* stfsr */ 510 case 0x3c: /* casa */ 511 case 0x3e: /* casxa */ 512 is_write = 1; 513 break; 514 } 515 } 516 return handle_cpu_signal(pc, info, is_write, sigmask); 517 } 518 519 #elif defined(__arm__) 520 521 #if defined(__NetBSD__) 522 #include <ucontext.h> 523 #include <sys/siginfo.h> 524 #endif 525 526 int cpu_signal_handler(int host_signum, void *pinfo, 527 void *puc) 528 { 529 siginfo_t *info = pinfo; 530 #if defined(__NetBSD__) 531 ucontext_t *uc = puc; 532 siginfo_t *si = pinfo; 533 #else 534 ucontext_t *uc = puc; 535 #endif 536 unsigned long pc; 537 uint32_t fsr; 538 int is_write; 539 540 #if defined(__NetBSD__) 541 pc = uc->uc_mcontext.__gregs[_REG_R15]; 542 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) 543 pc = uc->uc_mcontext.gregs[R15]; 544 #else 545 pc = uc->uc_mcontext.arm_pc; 546 #endif 547 548 #ifdef __NetBSD__ 549 fsr = si->si_trap; 550 #else 551 fsr = uc->uc_mcontext.error_code; 552 #endif 553 /* 554 * In the FSR, bit 11 is WnR, assuming a v6 or 555 * later processor. On v5 we will always report 556 * this as a read, which will fail later. 557 */ 558 is_write = extract32(fsr, 11, 1); 559 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 560 } 561 562 #elif defined(__aarch64__) 563 564 #if defined(__NetBSD__) 565 566 #include <ucontext.h> 567 #include <sys/siginfo.h> 568 569 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) 570 { 571 ucontext_t *uc = puc; 572 siginfo_t *si = pinfo; 573 unsigned long pc; 574 int is_write; 575 uint32_t esr; 576 577 pc = uc->uc_mcontext.__gregs[_REG_PC]; 578 esr = si->si_trap; 579 580 /* 581 * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC 582 * is 0b10010x: then bit 6 is the WnR bit 583 */ 584 is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; 585 return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); 586 } 587 588 #else 589 590 #ifndef ESR_MAGIC 591 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ 592 #define ESR_MAGIC 0x45535201 593 struct esr_context { 594 struct _aarch64_ctx head; 595 uint64_t esr; 596 }; 597 #endif 598 599 static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) 600 { 601 return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; 602 } 603 604 static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) 605 { 606 return (struct _aarch64_ctx *)((char *)hdr + hdr->size); 607 } 608 609 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) 610 { 611 siginfo_t *info = pinfo; 612 ucontext_t *uc = puc; 613 uintptr_t pc = uc->uc_mcontext.pc; 614 bool is_write; 615 struct _aarch64_ctx *hdr; 616 struct esr_context const *esrctx = NULL; 617 618 /* Find the esr_context, which has the WnR bit in it */ 619 for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { 620 if (hdr->magic == ESR_MAGIC) { 621 esrctx = (struct esr_context const *)hdr; 622 break; 623 } 624 } 625 626 if (esrctx) { 627 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ 628 uint64_t esr = esrctx->esr; 629 is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; 630 } else { 631 /* 632 * Fall back to parsing instructions; will only be needed 633 * for really ancient (pre-3.16) kernels. 634 */ 635 uint32_t insn = *(uint32_t *)pc; 636 637 is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ 638 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ 639 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ 640 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ 641 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ 642 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ 643 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ 644 /* Ignore bits 10, 11 & 21, controlling indexing. */ 645 || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ 646 || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ 647 /* Ignore bits 23 & 24, controlling indexing. */ 648 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ 649 } 650 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 651 } 652 #endif 653 654 #elif defined(__s390__) 655 656 int cpu_signal_handler(int host_signum, void *pinfo, 657 void *puc) 658 { 659 siginfo_t *info = pinfo; 660 ucontext_t *uc = puc; 661 unsigned long pc; 662 uint16_t *pinsn; 663 int is_write = 0; 664 665 pc = uc->uc_mcontext.psw.addr; 666 667 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead 668 of the normal 2 arguments. The 3rd argument contains the "int_code" 669 from the hardware which does in fact contain the is_write value. 670 The rt signal handler, as far as I can tell, does not give this value 671 at all. Not that we could get to it from here even if it were. */ 672 /* ??? This is not even close to complete, since it ignores all 673 of the read-modify-write instructions. */ 674 pinsn = (uint16_t *)pc; 675 switch (pinsn[0] >> 8) { 676 case 0x50: /* ST */ 677 case 0x42: /* STC */ 678 case 0x40: /* STH */ 679 is_write = 1; 680 break; 681 case 0xc4: /* RIL format insns */ 682 switch (pinsn[0] & 0xf) { 683 case 0xf: /* STRL */ 684 case 0xb: /* STGRL */ 685 case 0x7: /* STHRL */ 686 is_write = 1; 687 } 688 break; 689 case 0xe3: /* RXY format insns */ 690 switch (pinsn[2] & 0xff) { 691 case 0x50: /* STY */ 692 case 0x24: /* STG */ 693 case 0x72: /* STCY */ 694 case 0x70: /* STHY */ 695 case 0x8e: /* STPQ */ 696 case 0x3f: /* STRVH */ 697 case 0x3e: /* STRV */ 698 case 0x2f: /* STRVG */ 699 is_write = 1; 700 } 701 break; 702 } 703 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 704 } 705 706 #elif defined(__mips__) 707 708 #if defined(__misp16) || defined(__mips_micromips) 709 #error "Unsupported encoding" 710 #endif 711 712 int cpu_signal_handler(int host_signum, void *pinfo, 713 void *puc) 714 { 715 siginfo_t *info = pinfo; 716 ucontext_t *uc = puc; 717 uintptr_t pc = uc->uc_mcontext.pc; 718 uint32_t insn = *(uint32_t *)pc; 719 int is_write = 0; 720 721 /* Detect all store instructions at program counter. */ 722 switch((insn >> 26) & 077) { 723 case 050: /* SB */ 724 case 051: /* SH */ 725 case 052: /* SWL */ 726 case 053: /* SW */ 727 case 054: /* SDL */ 728 case 055: /* SDR */ 729 case 056: /* SWR */ 730 case 070: /* SC */ 731 case 071: /* SWC1 */ 732 case 074: /* SCD */ 733 case 075: /* SDC1 */ 734 case 077: /* SD */ 735 #if !defined(__mips_isa_rev) || __mips_isa_rev < 6 736 case 072: /* SWC2 */ 737 case 076: /* SDC2 */ 738 #endif 739 is_write = 1; 740 break; 741 case 023: /* COP1X */ 742 /* Required in all versions of MIPS64 since 743 MIPS64r1 and subsequent versions of MIPS32r2. */ 744 switch (insn & 077) { 745 case 010: /* SWXC1 */ 746 case 011: /* SDXC1 */ 747 case 015: /* SUXC1 */ 748 is_write = 1; 749 } 750 break; 751 } 752 753 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 754 } 755 756 #elif defined(__riscv) 757 758 int cpu_signal_handler(int host_signum, void *pinfo, 759 void *puc) 760 { 761 siginfo_t *info = pinfo; 762 ucontext_t *uc = puc; 763 greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; 764 uint32_t insn = *(uint32_t *)pc; 765 int is_write = 0; 766 767 /* Detect store by reading the instruction at the program 768 counter. Note: we currently only generate 32-bit 769 instructions so we thus only detect 32-bit stores */ 770 switch (((insn >> 0) & 0b11)) { 771 case 3: 772 switch (((insn >> 2) & 0b11111)) { 773 case 8: 774 switch (((insn >> 12) & 0b111)) { 775 case 0: /* sb */ 776 case 1: /* sh */ 777 case 2: /* sw */ 778 case 3: /* sd */ 779 case 4: /* sq */ 780 is_write = 1; 781 break; 782 default: 783 break; 784 } 785 break; 786 case 9: 787 switch (((insn >> 12) & 0b111)) { 788 case 2: /* fsw */ 789 case 3: /* fsd */ 790 case 4: /* fsq */ 791 is_write = 1; 792 break; 793 default: 794 break; 795 } 796 break; 797 default: 798 break; 799 } 800 } 801 802 /* Check for compressed instructions */ 803 switch (((insn >> 13) & 0b111)) { 804 case 7: 805 switch (insn & 0b11) { 806 case 0: /*c.sd */ 807 case 2: /* c.sdsp */ 808 is_write = 1; 809 break; 810 default: 811 break; 812 } 813 break; 814 case 6: 815 switch (insn & 0b11) { 816 case 0: /* c.sw */ 817 case 3: /* c.swsp */ 818 is_write = 1; 819 break; 820 default: 821 break; 822 } 823 break; 824 default: 825 break; 826 } 827 828 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 829 } 830 831 #else 832 833 #error host CPU specific signal handler needed 834 835 #endif 836 837 /* The softmmu versions of these helpers are in cputlb.c. */ 838 839 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) 840 { 841 uint32_t ret; 842 uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, false); 843 844 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 845 ret = ldub_p(g2h(env_cpu(env), ptr)); 846 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 847 return ret; 848 } 849 850 int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) 851 { 852 int ret; 853 uint16_t meminfo = trace_mem_get_info(MO_SB, MMU_USER_IDX, false); 854 855 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 856 ret = ldsb_p(g2h(env_cpu(env), ptr)); 857 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 858 return ret; 859 } 860 861 uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr) 862 { 863 uint32_t ret; 864 uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false); 865 866 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 867 ret = lduw_be_p(g2h(env_cpu(env), ptr)); 868 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 869 return ret; 870 } 871 872 int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) 873 { 874 int ret; 875 uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false); 876 877 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 878 ret = ldsw_be_p(g2h(env_cpu(env), ptr)); 879 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 880 return ret; 881 } 882 883 uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) 884 { 885 uint32_t ret; 886 uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false); 887 888 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 889 ret = ldl_be_p(g2h(env_cpu(env), ptr)); 890 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 891 return ret; 892 } 893 894 uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) 895 { 896 uint64_t ret; 897 uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false); 898 899 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 900 ret = ldq_be_p(g2h(env_cpu(env), ptr)); 901 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 902 return ret; 903 } 904 905 uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr) 906 { 907 uint32_t ret; 908 uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false); 909 910 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 911 ret = lduw_le_p(g2h(env_cpu(env), ptr)); 912 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 913 return ret; 914 } 915 916 int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) 917 { 918 int ret; 919 uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false); 920 921 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 922 ret = ldsw_le_p(g2h(env_cpu(env), ptr)); 923 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 924 return ret; 925 } 926 927 uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) 928 { 929 uint32_t ret; 930 uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false); 931 932 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 933 ret = ldl_le_p(g2h(env_cpu(env), ptr)); 934 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 935 return ret; 936 } 937 938 uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) 939 { 940 uint64_t ret; 941 uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false); 942 943 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 944 ret = ldq_le_p(g2h(env_cpu(env), ptr)); 945 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 946 return ret; 947 } 948 949 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 950 { 951 uint32_t ret; 952 953 set_helper_retaddr(retaddr); 954 ret = cpu_ldub_data(env, ptr); 955 clear_helper_retaddr(); 956 return ret; 957 } 958 959 int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 960 { 961 int ret; 962 963 set_helper_retaddr(retaddr); 964 ret = cpu_ldsb_data(env, ptr); 965 clear_helper_retaddr(); 966 return ret; 967 } 968 969 uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 970 { 971 uint32_t ret; 972 973 set_helper_retaddr(retaddr); 974 ret = cpu_lduw_be_data(env, ptr); 975 clear_helper_retaddr(); 976 return ret; 977 } 978 979 int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 980 { 981 int ret; 982 983 set_helper_retaddr(retaddr); 984 ret = cpu_ldsw_be_data(env, ptr); 985 clear_helper_retaddr(); 986 return ret; 987 } 988 989 uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 990 { 991 uint32_t ret; 992 993 set_helper_retaddr(retaddr); 994 ret = cpu_ldl_be_data(env, ptr); 995 clear_helper_retaddr(); 996 return ret; 997 } 998 999 uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1000 { 1001 uint64_t ret; 1002 1003 set_helper_retaddr(retaddr); 1004 ret = cpu_ldq_be_data(env, ptr); 1005 clear_helper_retaddr(); 1006 return ret; 1007 } 1008 1009 uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1010 { 1011 uint32_t ret; 1012 1013 set_helper_retaddr(retaddr); 1014 ret = cpu_lduw_le_data(env, ptr); 1015 clear_helper_retaddr(); 1016 return ret; 1017 } 1018 1019 int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1020 { 1021 int ret; 1022 1023 set_helper_retaddr(retaddr); 1024 ret = cpu_ldsw_le_data(env, ptr); 1025 clear_helper_retaddr(); 1026 return ret; 1027 } 1028 1029 uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1030 { 1031 uint32_t ret; 1032 1033 set_helper_retaddr(retaddr); 1034 ret = cpu_ldl_le_data(env, ptr); 1035 clear_helper_retaddr(); 1036 return ret; 1037 } 1038 1039 uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1040 { 1041 uint64_t ret; 1042 1043 set_helper_retaddr(retaddr); 1044 ret = cpu_ldq_le_data(env, ptr); 1045 clear_helper_retaddr(); 1046 return ret; 1047 } 1048 1049 void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1050 { 1051 uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, true); 1052 1053 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1054 stb_p(g2h(env_cpu(env), ptr), val); 1055 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1056 } 1057 1058 void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1059 { 1060 uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true); 1061 1062 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1063 stw_be_p(g2h(env_cpu(env), ptr), val); 1064 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1065 } 1066 1067 void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1068 { 1069 uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true); 1070 1071 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1072 stl_be_p(g2h(env_cpu(env), ptr), val); 1073 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1074 } 1075 1076 void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val) 1077 { 1078 uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true); 1079 1080 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1081 stq_be_p(g2h(env_cpu(env), ptr), val); 1082 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1083 } 1084 1085 void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1086 { 1087 uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true); 1088 1089 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1090 stw_le_p(g2h(env_cpu(env), ptr), val); 1091 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1092 } 1093 1094 void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1095 { 1096 uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true); 1097 1098 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1099 stl_le_p(g2h(env_cpu(env), ptr), val); 1100 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1101 } 1102 1103 void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val) 1104 { 1105 uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true); 1106 1107 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1108 stq_le_p(g2h(env_cpu(env), ptr), val); 1109 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1110 } 1111 1112 void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, 1113 uint32_t val, uintptr_t retaddr) 1114 { 1115 set_helper_retaddr(retaddr); 1116 cpu_stb_data(env, ptr, val); 1117 clear_helper_retaddr(); 1118 } 1119 1120 void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr, 1121 uint32_t val, uintptr_t retaddr) 1122 { 1123 set_helper_retaddr(retaddr); 1124 cpu_stw_be_data(env, ptr, val); 1125 clear_helper_retaddr(); 1126 } 1127 1128 void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr, 1129 uint32_t val, uintptr_t retaddr) 1130 { 1131 set_helper_retaddr(retaddr); 1132 cpu_stl_be_data(env, ptr, val); 1133 clear_helper_retaddr(); 1134 } 1135 1136 void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr, 1137 uint64_t val, uintptr_t retaddr) 1138 { 1139 set_helper_retaddr(retaddr); 1140 cpu_stq_be_data(env, ptr, val); 1141 clear_helper_retaddr(); 1142 } 1143 1144 void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr, 1145 uint32_t val, uintptr_t retaddr) 1146 { 1147 set_helper_retaddr(retaddr); 1148 cpu_stw_le_data(env, ptr, val); 1149 clear_helper_retaddr(); 1150 } 1151 1152 void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, 1153 uint32_t val, uintptr_t retaddr) 1154 { 1155 set_helper_retaddr(retaddr); 1156 cpu_stl_le_data(env, ptr, val); 1157 clear_helper_retaddr(); 1158 } 1159 1160 void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, 1161 uint64_t val, uintptr_t retaddr) 1162 { 1163 set_helper_retaddr(retaddr); 1164 cpu_stq_le_data(env, ptr, val); 1165 clear_helper_retaddr(); 1166 } 1167 1168 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) 1169 { 1170 uint32_t ret; 1171 1172 set_helper_retaddr(1); 1173 ret = ldub_p(g2h_untagged(ptr)); 1174 clear_helper_retaddr(); 1175 return ret; 1176 } 1177 1178 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr ptr) 1179 { 1180 uint32_t ret; 1181 1182 set_helper_retaddr(1); 1183 ret = lduw_p(g2h_untagged(ptr)); 1184 clear_helper_retaddr(); 1185 return ret; 1186 } 1187 1188 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr ptr) 1189 { 1190 uint32_t ret; 1191 1192 set_helper_retaddr(1); 1193 ret = ldl_p(g2h_untagged(ptr)); 1194 clear_helper_retaddr(); 1195 return ret; 1196 } 1197 1198 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) 1199 { 1200 uint64_t ret; 1201 1202 set_helper_retaddr(1); 1203 ret = ldq_p(g2h_untagged(ptr)); 1204 clear_helper_retaddr(); 1205 return ret; 1206 } 1207 1208 /* Do not allow unaligned operations to proceed. Return the host address. */ 1209 static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, 1210 int size, uintptr_t retaddr) 1211 { 1212 /* Enforce qemu required alignment. */ 1213 if (unlikely(addr & (size - 1))) { 1214 cpu_loop_exit_atomic(env_cpu(env), retaddr); 1215 } 1216 void *ret = g2h(env_cpu(env), addr); 1217 set_helper_retaddr(retaddr); 1218 return ret; 1219 } 1220 1221 /* Macro to call the above, with local variables from the use context. */ 1222 #define ATOMIC_MMU_DECLS do {} while (0) 1223 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC()) 1224 #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) 1225 #define ATOMIC_MMU_IDX MMU_USER_IDX 1226 1227 #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) 1228 #define EXTRA_ARGS 1229 1230 #include "atomic_common.c.inc" 1231 1232 #define DATA_SIZE 1 1233 #include "atomic_template.h" 1234 1235 #define DATA_SIZE 2 1236 #include "atomic_template.h" 1237 1238 #define DATA_SIZE 4 1239 #include "atomic_template.h" 1240 1241 #ifdef CONFIG_ATOMIC64 1242 #define DATA_SIZE 8 1243 #include "atomic_template.h" 1244 #endif 1245 1246 /* The following is only callable from other helpers, and matches up 1247 with the softmmu version. */ 1248 1249 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128 1250 1251 #undef EXTRA_ARGS 1252 #undef ATOMIC_NAME 1253 #undef ATOMIC_MMU_LOOKUP 1254 1255 #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr 1256 #define ATOMIC_NAME(X) \ 1257 HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) 1258 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr) 1259 1260 #define DATA_SIZE 16 1261 #include "atomic_template.h" 1262 #endif 1263