1bdd6a90aSFam Zheng /* 2bdd6a90aSFam Zheng * NVMe block driver based on vfio 3bdd6a90aSFam Zheng * 4bdd6a90aSFam Zheng * Copyright 2016 - 2018 Red Hat, Inc. 5bdd6a90aSFam Zheng * 6bdd6a90aSFam Zheng * Authors: 7bdd6a90aSFam Zheng * Fam Zheng <famz@redhat.com> 8bdd6a90aSFam Zheng * Paolo Bonzini <pbonzini@redhat.com> 9bdd6a90aSFam Zheng * 10bdd6a90aSFam Zheng * This work is licensed under the terms of the GNU GPL, version 2 or later. 11bdd6a90aSFam Zheng * See the COPYING file in the top-level directory. 12bdd6a90aSFam Zheng */ 13bdd6a90aSFam Zheng 14bdd6a90aSFam Zheng #include "qemu/osdep.h" 15bdd6a90aSFam Zheng #include <linux/vfio.h> 16bdd6a90aSFam Zheng #include "qapi/error.h" 17bdd6a90aSFam Zheng #include "qapi/qmp/qdict.h" 18bdd6a90aSFam Zheng #include "qapi/qmp/qstring.h" 19bdd6a90aSFam Zheng #include "qemu/error-report.h" 20db725815SMarkus Armbruster #include "qemu/main-loop.h" 210b8fa32fSMarkus Armbruster #include "qemu/module.h" 22bdd6a90aSFam Zheng #include "qemu/cutils.h" 23922a01a0SMarkus Armbruster #include "qemu/option.h" 24bdd6a90aSFam Zheng #include "qemu/vfio-helpers.h" 25bdd6a90aSFam Zheng #include "block/block_int.h" 26e4ec5ad4SPavel Dovgalyuk #include "sysemu/replay.h" 27bdd6a90aSFam Zheng #include "trace.h" 28bdd6a90aSFam Zheng 29a3d9a352SFam Zheng #include "block/nvme.h" 30bdd6a90aSFam Zheng 31bdd6a90aSFam Zheng #define NVME_SQ_ENTRY_BYTES 64 32bdd6a90aSFam Zheng #define NVME_CQ_ENTRY_BYTES 16 33bdd6a90aSFam Zheng #define NVME_QUEUE_SIZE 128 34f6845323SPhilippe Mathieu-Daudé #define NVME_DOORBELL_SIZE 4096 35bdd6a90aSFam Zheng 361086e95dSStefan Hajnoczi /* 371086e95dSStefan Hajnoczi * We have to leave one slot empty as that is the full queue case where 381086e95dSStefan Hajnoczi * head == tail + 1. 391086e95dSStefan Hajnoczi */ 401086e95dSStefan Hajnoczi #define NVME_NUM_REQS (NVME_QUEUE_SIZE - 1) 411086e95dSStefan Hajnoczi 42b75fd5f5SStefan Hajnoczi typedef struct BDRVNVMeState BDRVNVMeState; 43b75fd5f5SStefan Hajnoczi 443214b0f0SPhilippe Mathieu-Daudé /* Same index is used for queues and IRQs */ 453214b0f0SPhilippe Mathieu-Daudé #define INDEX_ADMIN 0 463214b0f0SPhilippe Mathieu-Daudé #define INDEX_IO(n) (1 + n) 473214b0f0SPhilippe Mathieu-Daudé 483214b0f0SPhilippe Mathieu-Daudé /* This driver shares a single MSIX IRQ for the admin and I/O queues */ 493214b0f0SPhilippe Mathieu-Daudé enum { 503214b0f0SPhilippe Mathieu-Daudé MSIX_SHARED_IRQ_IDX = 0, 513214b0f0SPhilippe Mathieu-Daudé MSIX_IRQ_COUNT = 1 523214b0f0SPhilippe Mathieu-Daudé }; 533214b0f0SPhilippe Mathieu-Daudé 54bdd6a90aSFam Zheng typedef struct { 55bdd6a90aSFam Zheng int32_t head, tail; 56bdd6a90aSFam Zheng uint8_t *queue; 57bdd6a90aSFam Zheng uint64_t iova; 58bdd6a90aSFam Zheng /* Hardware MMIO register */ 59bdd6a90aSFam Zheng volatile uint32_t *doorbell; 60bdd6a90aSFam Zheng } NVMeQueue; 61bdd6a90aSFam Zheng 62bdd6a90aSFam Zheng typedef struct { 63bdd6a90aSFam Zheng BlockCompletionFunc *cb; 64bdd6a90aSFam Zheng void *opaque; 65bdd6a90aSFam Zheng int cid; 66bdd6a90aSFam Zheng void *prp_list_page; 67bdd6a90aSFam Zheng uint64_t prp_list_iova; 681086e95dSStefan Hajnoczi int free_req_next; /* q->reqs[] index of next free req */ 69bdd6a90aSFam Zheng } NVMeRequest; 70bdd6a90aSFam Zheng 71bdd6a90aSFam Zheng typedef struct { 72bdd6a90aSFam Zheng QemuMutex lock; 73bdd6a90aSFam Zheng 74b75fd5f5SStefan Hajnoczi /* Read from I/O code path, initialized under BQL */ 75b75fd5f5SStefan Hajnoczi BDRVNVMeState *s; 76bdd6a90aSFam Zheng int index; 77b75fd5f5SStefan Hajnoczi 78b75fd5f5SStefan Hajnoczi /* Fields protected by BQL */ 79bdd6a90aSFam Zheng uint8_t *prp_list_pages; 80bdd6a90aSFam Zheng 81bdd6a90aSFam Zheng /* Fields protected by @lock */ 82a5db74f3SStefan Hajnoczi CoQueue free_req_queue; 83bdd6a90aSFam Zheng NVMeQueue sq, cq; 84bdd6a90aSFam Zheng int cq_phase; 851086e95dSStefan Hajnoczi int free_req_head; 861086e95dSStefan Hajnoczi NVMeRequest reqs[NVME_NUM_REQS]; 87bdd6a90aSFam Zheng int need_kick; 88bdd6a90aSFam Zheng int inflight; 897838c67fSStefan Hajnoczi 907838c67fSStefan Hajnoczi /* Thread-safe, no lock necessary */ 917838c67fSStefan Hajnoczi QEMUBH *completion_bh; 92bdd6a90aSFam Zheng } NVMeQueuePair; 93bdd6a90aSFam Zheng 94b75fd5f5SStefan Hajnoczi struct BDRVNVMeState { 95bdd6a90aSFam Zheng AioContext *aio_context; 96bdd6a90aSFam Zheng QEMUVFIOState *vfio; 97f6845323SPhilippe Mathieu-Daudé /* Memory mapped registers */ 98f6845323SPhilippe Mathieu-Daudé volatile struct { 99f6845323SPhilippe Mathieu-Daudé uint32_t sq_tail; 100f6845323SPhilippe Mathieu-Daudé uint32_t cq_head; 101f6845323SPhilippe Mathieu-Daudé } *doorbells; 102bdd6a90aSFam Zheng /* The submission/completion queue pairs. 103bdd6a90aSFam Zheng * [0]: admin queue. 104bdd6a90aSFam Zheng * [1..]: io queues. 105bdd6a90aSFam Zheng */ 106bdd6a90aSFam Zheng NVMeQueuePair **queues; 1071b539bd6SPhilippe Mathieu-Daudé unsigned queue_count; 108bdd6a90aSFam Zheng size_t page_size; 109bdd6a90aSFam Zheng /* How many uint32_t elements does each doorbell entry take. */ 110bdd6a90aSFam Zheng size_t doorbell_scale; 111bdd6a90aSFam Zheng bool write_cache_supported; 112b111b3fcSPhilippe Mathieu-Daudé EventNotifier irq_notifier[MSIX_IRQ_COUNT]; 113118d1b6aSMaxim Levitsky 114bdd6a90aSFam Zheng uint64_t nsze; /* Namespace size reported by identify command */ 115bdd6a90aSFam Zheng int nsid; /* The namespace id to read/write data. */ 1161120407bSMax Reitz int blkshift; 117118d1b6aSMaxim Levitsky 118bdd6a90aSFam Zheng uint64_t max_transfer; 1192f0d8947SPaolo Bonzini bool plugged; 120bdd6a90aSFam Zheng 121e0dd95e3SMaxim Levitsky bool supports_write_zeroes; 122e87a09d6SMaxim Levitsky bool supports_discard; 123e0dd95e3SMaxim Levitsky 124bdd6a90aSFam Zheng CoMutex dma_map_lock; 125bdd6a90aSFam Zheng CoQueue dma_flush_queue; 126bdd6a90aSFam Zheng 127bdd6a90aSFam Zheng /* Total size of mapped qiov, accessed under dma_map_lock */ 128bdd6a90aSFam Zheng int dma_map_count; 129cc61b074SMax Reitz 130cc61b074SMax Reitz /* PCI address (required for nvme_refresh_filename()) */ 131cc61b074SMax Reitz char *device; 132f25e7ab2SPhilippe Mathieu-Daudé 133f25e7ab2SPhilippe Mathieu-Daudé struct { 134f25e7ab2SPhilippe Mathieu-Daudé uint64_t completion_errors; 135f25e7ab2SPhilippe Mathieu-Daudé uint64_t aligned_accesses; 136f25e7ab2SPhilippe Mathieu-Daudé uint64_t unaligned_accesses; 137f25e7ab2SPhilippe Mathieu-Daudé } stats; 138b75fd5f5SStefan Hajnoczi }; 139bdd6a90aSFam Zheng 140bdd6a90aSFam Zheng #define NVME_BLOCK_OPT_DEVICE "device" 141bdd6a90aSFam Zheng #define NVME_BLOCK_OPT_NAMESPACE "namespace" 142bdd6a90aSFam Zheng 1437838c67fSStefan Hajnoczi static void nvme_process_completion_bh(void *opaque); 1447838c67fSStefan Hajnoczi 145bdd6a90aSFam Zheng static QemuOptsList runtime_opts = { 146bdd6a90aSFam Zheng .name = "nvme", 147bdd6a90aSFam Zheng .head = QTAILQ_HEAD_INITIALIZER(runtime_opts.head), 148bdd6a90aSFam Zheng .desc = { 149bdd6a90aSFam Zheng { 150bdd6a90aSFam Zheng .name = NVME_BLOCK_OPT_DEVICE, 151bdd6a90aSFam Zheng .type = QEMU_OPT_STRING, 152bdd6a90aSFam Zheng .help = "NVMe PCI device address", 153bdd6a90aSFam Zheng }, 154bdd6a90aSFam Zheng { 155bdd6a90aSFam Zheng .name = NVME_BLOCK_OPT_NAMESPACE, 156bdd6a90aSFam Zheng .type = QEMU_OPT_NUMBER, 157bdd6a90aSFam Zheng .help = "NVMe namespace", 158bdd6a90aSFam Zheng }, 159bdd6a90aSFam Zheng { /* end of list */ } 160bdd6a90aSFam Zheng }, 161bdd6a90aSFam Zheng }; 162bdd6a90aSFam Zheng 163dfa9c6c6SPhilippe Mathieu-Daudé /* Returns true on success, false on failure. */ 164dfa9c6c6SPhilippe Mathieu-Daudé static bool nvme_init_queue(BDRVNVMeState *s, NVMeQueue *q, 1651b539bd6SPhilippe Mathieu-Daudé unsigned nentries, size_t entry_bytes, Error **errp) 166bdd6a90aSFam Zheng { 167bdd6a90aSFam Zheng size_t bytes; 168bdd6a90aSFam Zheng int r; 169bdd6a90aSFam Zheng 170*2387aaceSEric Auger bytes = ROUND_UP(nentries * entry_bytes, qemu_real_host_page_size); 171bdd6a90aSFam Zheng q->head = q->tail = 0; 172*2387aaceSEric Auger q->queue = qemu_try_memalign(qemu_real_host_page_size, bytes); 173bdd6a90aSFam Zheng if (!q->queue) { 174bdd6a90aSFam Zheng error_setg(errp, "Cannot allocate queue"); 175dfa9c6c6SPhilippe Mathieu-Daudé return false; 176bdd6a90aSFam Zheng } 1772ed84693SPhilippe Mathieu-Daudé memset(q->queue, 0, bytes); 178bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, q->queue, bytes, false, &q->iova); 179bdd6a90aSFam Zheng if (r) { 180bdd6a90aSFam Zheng error_setg(errp, "Cannot map queue"); 181dfa9c6c6SPhilippe Mathieu-Daudé return false; 182bdd6a90aSFam Zheng } 183dfa9c6c6SPhilippe Mathieu-Daudé return true; 184bdd6a90aSFam Zheng } 185bdd6a90aSFam Zheng 186b75fd5f5SStefan Hajnoczi static void nvme_free_queue_pair(NVMeQueuePair *q) 187bdd6a90aSFam Zheng { 1886e1e9ff2SPhilippe Mathieu-Daudé trace_nvme_free_queue_pair(q->index, q); 1897838c67fSStefan Hajnoczi if (q->completion_bh) { 1907838c67fSStefan Hajnoczi qemu_bh_delete(q->completion_bh); 1917838c67fSStefan Hajnoczi } 192bdd6a90aSFam Zheng qemu_vfree(q->prp_list_pages); 193bdd6a90aSFam Zheng qemu_vfree(q->sq.queue); 194bdd6a90aSFam Zheng qemu_vfree(q->cq.queue); 195bdd6a90aSFam Zheng qemu_mutex_destroy(&q->lock); 196bdd6a90aSFam Zheng g_free(q); 197bdd6a90aSFam Zheng } 198bdd6a90aSFam Zheng 199bdd6a90aSFam Zheng static void nvme_free_req_queue_cb(void *opaque) 200bdd6a90aSFam Zheng { 201bdd6a90aSFam Zheng NVMeQueuePair *q = opaque; 202bdd6a90aSFam Zheng 203bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 204bdd6a90aSFam Zheng while (qemu_co_enter_next(&q->free_req_queue, &q->lock)) { 205bdd6a90aSFam Zheng /* Retry all pending requests */ 206bdd6a90aSFam Zheng } 207bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 208bdd6a90aSFam Zheng } 209bdd6a90aSFam Zheng 2100a28b02eSPhilippe Mathieu-Daudé static NVMeQueuePair *nvme_create_queue_pair(BDRVNVMeState *s, 2110a28b02eSPhilippe Mathieu-Daudé AioContext *aio_context, 2121b539bd6SPhilippe Mathieu-Daudé unsigned idx, size_t size, 213bdd6a90aSFam Zheng Error **errp) 214bdd6a90aSFam Zheng { 215bdd6a90aSFam Zheng int i, r; 2160ea45f76SPhilippe Mathieu-Daudé NVMeQueuePair *q; 217bdd6a90aSFam Zheng uint64_t prp_list_iova; 218bdd6a90aSFam Zheng 2190ea45f76SPhilippe Mathieu-Daudé q = g_try_new0(NVMeQueuePair, 1); 2200ea45f76SPhilippe Mathieu-Daudé if (!q) { 2210ea45f76SPhilippe Mathieu-Daudé return NULL; 2220ea45f76SPhilippe Mathieu-Daudé } 2236e1e9ff2SPhilippe Mathieu-Daudé trace_nvme_create_queue_pair(idx, q, size, aio_context, 2246e1e9ff2SPhilippe Mathieu-Daudé event_notifier_get_fd(s->irq_notifier)); 22538e1f818SPhilippe Mathieu-Daudé q->prp_list_pages = qemu_try_memalign(s->page_size, 2260ea45f76SPhilippe Mathieu-Daudé s->page_size * NVME_NUM_REQS); 2270ea45f76SPhilippe Mathieu-Daudé if (!q->prp_list_pages) { 2280ea45f76SPhilippe Mathieu-Daudé goto fail; 2290ea45f76SPhilippe Mathieu-Daudé } 2302ed84693SPhilippe Mathieu-Daudé memset(q->prp_list_pages, 0, s->page_size * NVME_NUM_REQS); 231bdd6a90aSFam Zheng qemu_mutex_init(&q->lock); 232b75fd5f5SStefan Hajnoczi q->s = s; 233bdd6a90aSFam Zheng q->index = idx; 234bdd6a90aSFam Zheng qemu_co_queue_init(&q->free_req_queue); 2350a28b02eSPhilippe Mathieu-Daudé q->completion_bh = aio_bh_new(aio_context, nvme_process_completion_bh, q); 236bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, q->prp_list_pages, 2371086e95dSStefan Hajnoczi s->page_size * NVME_NUM_REQS, 238bdd6a90aSFam Zheng false, &prp_list_iova); 239bdd6a90aSFam Zheng if (r) { 240bdd6a90aSFam Zheng goto fail; 241bdd6a90aSFam Zheng } 2421086e95dSStefan Hajnoczi q->free_req_head = -1; 2431086e95dSStefan Hajnoczi for (i = 0; i < NVME_NUM_REQS; i++) { 244bdd6a90aSFam Zheng NVMeRequest *req = &q->reqs[i]; 245bdd6a90aSFam Zheng req->cid = i + 1; 2461086e95dSStefan Hajnoczi req->free_req_next = q->free_req_head; 2471086e95dSStefan Hajnoczi q->free_req_head = i; 248bdd6a90aSFam Zheng req->prp_list_page = q->prp_list_pages + i * s->page_size; 249bdd6a90aSFam Zheng req->prp_list_iova = prp_list_iova + i * s->page_size; 250bdd6a90aSFam Zheng } 2511086e95dSStefan Hajnoczi 252dfa9c6c6SPhilippe Mathieu-Daudé if (!nvme_init_queue(s, &q->sq, size, NVME_SQ_ENTRY_BYTES, errp)) { 253bdd6a90aSFam Zheng goto fail; 254bdd6a90aSFam Zheng } 255f6845323SPhilippe Mathieu-Daudé q->sq.doorbell = &s->doorbells[idx * s->doorbell_scale].sq_tail; 256bdd6a90aSFam Zheng 257dfa9c6c6SPhilippe Mathieu-Daudé if (!nvme_init_queue(s, &q->cq, size, NVME_CQ_ENTRY_BYTES, errp)) { 258bdd6a90aSFam Zheng goto fail; 259bdd6a90aSFam Zheng } 260f6845323SPhilippe Mathieu-Daudé q->cq.doorbell = &s->doorbells[idx * s->doorbell_scale].cq_head; 261bdd6a90aSFam Zheng 262bdd6a90aSFam Zheng return q; 263bdd6a90aSFam Zheng fail: 264b75fd5f5SStefan Hajnoczi nvme_free_queue_pair(q); 265bdd6a90aSFam Zheng return NULL; 266bdd6a90aSFam Zheng } 267bdd6a90aSFam Zheng 268bdd6a90aSFam Zheng /* With q->lock */ 269b75fd5f5SStefan Hajnoczi static void nvme_kick(NVMeQueuePair *q) 270bdd6a90aSFam Zheng { 271b75fd5f5SStefan Hajnoczi BDRVNVMeState *s = q->s; 272b75fd5f5SStefan Hajnoczi 273bdd6a90aSFam Zheng if (s->plugged || !q->need_kick) { 274bdd6a90aSFam Zheng return; 275bdd6a90aSFam Zheng } 276bdd6a90aSFam Zheng trace_nvme_kick(s, q->index); 277bdd6a90aSFam Zheng assert(!(q->sq.tail & 0xFF00)); 278bdd6a90aSFam Zheng /* Fence the write to submission queue entry before notifying the device. */ 279bdd6a90aSFam Zheng smp_wmb(); 280bdd6a90aSFam Zheng *q->sq.doorbell = cpu_to_le32(q->sq.tail); 281bdd6a90aSFam Zheng q->inflight += q->need_kick; 282bdd6a90aSFam Zheng q->need_kick = 0; 283bdd6a90aSFam Zheng } 284bdd6a90aSFam Zheng 285bdd6a90aSFam Zheng /* Find a free request element if any, otherwise: 286bdd6a90aSFam Zheng * a) if in coroutine context, try to wait for one to become available; 287bdd6a90aSFam Zheng * b) if not in coroutine, return NULL; 288bdd6a90aSFam Zheng */ 289bdd6a90aSFam Zheng static NVMeRequest *nvme_get_free_req(NVMeQueuePair *q) 290bdd6a90aSFam Zheng { 2911086e95dSStefan Hajnoczi NVMeRequest *req; 292bdd6a90aSFam Zheng 293bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 2941086e95dSStefan Hajnoczi 2951086e95dSStefan Hajnoczi while (q->free_req_head == -1) { 296bdd6a90aSFam Zheng if (qemu_in_coroutine()) { 29751e98b6dSPhilippe Mathieu-Daudé trace_nvme_free_req_queue_wait(q->s, q->index); 298bdd6a90aSFam Zheng qemu_co_queue_wait(&q->free_req_queue, &q->lock); 299bdd6a90aSFam Zheng } else { 300bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 301bdd6a90aSFam Zheng return NULL; 302bdd6a90aSFam Zheng } 303bdd6a90aSFam Zheng } 3041086e95dSStefan Hajnoczi 3051086e95dSStefan Hajnoczi req = &q->reqs[q->free_req_head]; 3061086e95dSStefan Hajnoczi q->free_req_head = req->free_req_next; 3071086e95dSStefan Hajnoczi req->free_req_next = -1; 3081086e95dSStefan Hajnoczi 309bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 310bdd6a90aSFam Zheng return req; 311bdd6a90aSFam Zheng } 312bdd6a90aSFam Zheng 3131086e95dSStefan Hajnoczi /* With q->lock */ 3141086e95dSStefan Hajnoczi static void nvme_put_free_req_locked(NVMeQueuePair *q, NVMeRequest *req) 3151086e95dSStefan Hajnoczi { 3161086e95dSStefan Hajnoczi req->free_req_next = q->free_req_head; 3171086e95dSStefan Hajnoczi q->free_req_head = req - q->reqs; 3181086e95dSStefan Hajnoczi } 3191086e95dSStefan Hajnoczi 3201086e95dSStefan Hajnoczi /* With q->lock */ 321b75fd5f5SStefan Hajnoczi static void nvme_wake_free_req_locked(NVMeQueuePair *q) 3221086e95dSStefan Hajnoczi { 3231086e95dSStefan Hajnoczi if (!qemu_co_queue_empty(&q->free_req_queue)) { 324b75fd5f5SStefan Hajnoczi replay_bh_schedule_oneshot_event(q->s->aio_context, 3251086e95dSStefan Hajnoczi nvme_free_req_queue_cb, q); 3261086e95dSStefan Hajnoczi } 3271086e95dSStefan Hajnoczi } 3281086e95dSStefan Hajnoczi 3291086e95dSStefan Hajnoczi /* Insert a request in the freelist and wake waiters */ 330b75fd5f5SStefan Hajnoczi static void nvme_put_free_req_and_wake(NVMeQueuePair *q, NVMeRequest *req) 3311086e95dSStefan Hajnoczi { 3321086e95dSStefan Hajnoczi qemu_mutex_lock(&q->lock); 3331086e95dSStefan Hajnoczi nvme_put_free_req_locked(q, req); 334b75fd5f5SStefan Hajnoczi nvme_wake_free_req_locked(q); 3351086e95dSStefan Hajnoczi qemu_mutex_unlock(&q->lock); 3361086e95dSStefan Hajnoczi } 3371086e95dSStefan Hajnoczi 338bdd6a90aSFam Zheng static inline int nvme_translate_error(const NvmeCqe *c) 339bdd6a90aSFam Zheng { 340bdd6a90aSFam Zheng uint16_t status = (le16_to_cpu(c->status) >> 1) & 0xFF; 341bdd6a90aSFam Zheng if (status) { 342bdd6a90aSFam Zheng trace_nvme_error(le32_to_cpu(c->result), 343bdd6a90aSFam Zheng le16_to_cpu(c->sq_head), 344bdd6a90aSFam Zheng le16_to_cpu(c->sq_id), 345bdd6a90aSFam Zheng le16_to_cpu(c->cid), 346bdd6a90aSFam Zheng le16_to_cpu(status)); 347bdd6a90aSFam Zheng } 348bdd6a90aSFam Zheng switch (status) { 349bdd6a90aSFam Zheng case 0: 350bdd6a90aSFam Zheng return 0; 351bdd6a90aSFam Zheng case 1: 352bdd6a90aSFam Zheng return -ENOSYS; 353bdd6a90aSFam Zheng case 2: 354bdd6a90aSFam Zheng return -EINVAL; 355bdd6a90aSFam Zheng default: 356bdd6a90aSFam Zheng return -EIO; 357bdd6a90aSFam Zheng } 358bdd6a90aSFam Zheng } 359bdd6a90aSFam Zheng 360bdd6a90aSFam Zheng /* With q->lock */ 361b75fd5f5SStefan Hajnoczi static bool nvme_process_completion(NVMeQueuePair *q) 362bdd6a90aSFam Zheng { 363b75fd5f5SStefan Hajnoczi BDRVNVMeState *s = q->s; 364bdd6a90aSFam Zheng bool progress = false; 365bdd6a90aSFam Zheng NVMeRequest *preq; 366bdd6a90aSFam Zheng NVMeRequest req; 367bdd6a90aSFam Zheng NvmeCqe *c; 368bdd6a90aSFam Zheng 369bdd6a90aSFam Zheng trace_nvme_process_completion(s, q->index, q->inflight); 3707838c67fSStefan Hajnoczi if (s->plugged) { 3717838c67fSStefan Hajnoczi trace_nvme_process_completion_queue_plugged(s, q->index); 372bdd6a90aSFam Zheng return false; 373bdd6a90aSFam Zheng } 3747838c67fSStefan Hajnoczi 3757838c67fSStefan Hajnoczi /* 3767838c67fSStefan Hajnoczi * Support re-entrancy when a request cb() function invokes aio_poll(). 3777838c67fSStefan Hajnoczi * Pending completions must be visible to aio_poll() so that a cb() 3787838c67fSStefan Hajnoczi * function can wait for the completion of another request. 3797838c67fSStefan Hajnoczi * 3807838c67fSStefan Hajnoczi * The aio_poll() loop will execute our BH and we'll resume completion 3817838c67fSStefan Hajnoczi * processing there. 3827838c67fSStefan Hajnoczi */ 3837838c67fSStefan Hajnoczi qemu_bh_schedule(q->completion_bh); 3847838c67fSStefan Hajnoczi 385bdd6a90aSFam Zheng assert(q->inflight >= 0); 386bdd6a90aSFam Zheng while (q->inflight) { 38704b3fb39SStefan Hajnoczi int ret; 388bdd6a90aSFam Zheng int16_t cid; 38904b3fb39SStefan Hajnoczi 390bdd6a90aSFam Zheng c = (NvmeCqe *)&q->cq.queue[q->cq.head * NVME_CQ_ENTRY_BYTES]; 391258867d1SMaxim Levitsky if ((le16_to_cpu(c->status) & 0x1) == q->cq_phase) { 392bdd6a90aSFam Zheng break; 393bdd6a90aSFam Zheng } 39404b3fb39SStefan Hajnoczi ret = nvme_translate_error(c); 395f25e7ab2SPhilippe Mathieu-Daudé if (ret) { 396f25e7ab2SPhilippe Mathieu-Daudé s->stats.completion_errors++; 397f25e7ab2SPhilippe Mathieu-Daudé } 398bdd6a90aSFam Zheng q->cq.head = (q->cq.head + 1) % NVME_QUEUE_SIZE; 399bdd6a90aSFam Zheng if (!q->cq.head) { 400bdd6a90aSFam Zheng q->cq_phase = !q->cq_phase; 401bdd6a90aSFam Zheng } 402bdd6a90aSFam Zheng cid = le16_to_cpu(c->cid); 403bdd6a90aSFam Zheng if (cid == 0 || cid > NVME_QUEUE_SIZE) { 40458ad6ae0SPhilippe Mathieu-Daudé warn_report("NVMe: Unexpected CID in completion queue: %"PRIu32", " 40558ad6ae0SPhilippe Mathieu-Daudé "queue size: %u", cid, NVME_QUEUE_SIZE); 406bdd6a90aSFam Zheng continue; 407bdd6a90aSFam Zheng } 408bdd6a90aSFam Zheng trace_nvme_complete_command(s, q->index, cid); 409bdd6a90aSFam Zheng preq = &q->reqs[cid - 1]; 410bdd6a90aSFam Zheng req = *preq; 411bdd6a90aSFam Zheng assert(req.cid == cid); 412bdd6a90aSFam Zheng assert(req.cb); 4131086e95dSStefan Hajnoczi nvme_put_free_req_locked(q, preq); 414bdd6a90aSFam Zheng preq->cb = preq->opaque = NULL; 4157838c67fSStefan Hajnoczi q->inflight--; 416bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 41704b3fb39SStefan Hajnoczi req.cb(req.opaque, ret); 418bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 419bdd6a90aSFam Zheng progress = true; 420bdd6a90aSFam Zheng } 421bdd6a90aSFam Zheng if (progress) { 422bdd6a90aSFam Zheng /* Notify the device so it can post more completions. */ 423bdd6a90aSFam Zheng smp_mb_release(); 424bdd6a90aSFam Zheng *q->cq.doorbell = cpu_to_le32(q->cq.head); 425b75fd5f5SStefan Hajnoczi nvme_wake_free_req_locked(q); 426bdd6a90aSFam Zheng } 4277838c67fSStefan Hajnoczi 4287838c67fSStefan Hajnoczi qemu_bh_cancel(q->completion_bh); 4297838c67fSStefan Hajnoczi 430bdd6a90aSFam Zheng return progress; 431bdd6a90aSFam Zheng } 432bdd6a90aSFam Zheng 4337838c67fSStefan Hajnoczi static void nvme_process_completion_bh(void *opaque) 4347838c67fSStefan Hajnoczi { 4357838c67fSStefan Hajnoczi NVMeQueuePair *q = opaque; 4367838c67fSStefan Hajnoczi 4377838c67fSStefan Hajnoczi /* 4387838c67fSStefan Hajnoczi * We're being invoked because a nvme_process_completion() cb() function 4397838c67fSStefan Hajnoczi * called aio_poll(). The callback may be waiting for further completions 4407838c67fSStefan Hajnoczi * so notify the device that it has space to fill in more completions now. 4417838c67fSStefan Hajnoczi */ 4427838c67fSStefan Hajnoczi smp_mb_release(); 4437838c67fSStefan Hajnoczi *q->cq.doorbell = cpu_to_le32(q->cq.head); 4447838c67fSStefan Hajnoczi nvme_wake_free_req_locked(q); 4457838c67fSStefan Hajnoczi 4467838c67fSStefan Hajnoczi nvme_process_completion(q); 4477838c67fSStefan Hajnoczi } 4487838c67fSStefan Hajnoczi 449bdd6a90aSFam Zheng static void nvme_trace_command(const NvmeCmd *cmd) 450bdd6a90aSFam Zheng { 451bdd6a90aSFam Zheng int i; 452bdd6a90aSFam Zheng 453e266f52cSPhilippe Mathieu-Daudé if (!trace_event_get_state_backends(TRACE_NVME_SUBMIT_COMMAND_RAW)) { 454e266f52cSPhilippe Mathieu-Daudé return; 455e266f52cSPhilippe Mathieu-Daudé } 456bdd6a90aSFam Zheng for (i = 0; i < 8; ++i) { 457bdd6a90aSFam Zheng uint8_t *cmdp = (uint8_t *)cmd + i * 8; 458bdd6a90aSFam Zheng trace_nvme_submit_command_raw(cmdp[0], cmdp[1], cmdp[2], cmdp[3], 459bdd6a90aSFam Zheng cmdp[4], cmdp[5], cmdp[6], cmdp[7]); 460bdd6a90aSFam Zheng } 461bdd6a90aSFam Zheng } 462bdd6a90aSFam Zheng 463b75fd5f5SStefan Hajnoczi static void nvme_submit_command(NVMeQueuePair *q, NVMeRequest *req, 464bdd6a90aSFam Zheng NvmeCmd *cmd, BlockCompletionFunc cb, 465bdd6a90aSFam Zheng void *opaque) 466bdd6a90aSFam Zheng { 467bdd6a90aSFam Zheng assert(!req->cb); 468bdd6a90aSFam Zheng req->cb = cb; 469bdd6a90aSFam Zheng req->opaque = opaque; 470bdd6a90aSFam Zheng cmd->cid = cpu_to_le32(req->cid); 471bdd6a90aSFam Zheng 472b75fd5f5SStefan Hajnoczi trace_nvme_submit_command(q->s, q->index, req->cid); 473bdd6a90aSFam Zheng nvme_trace_command(cmd); 474bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 475bdd6a90aSFam Zheng memcpy((uint8_t *)q->sq.queue + 476bdd6a90aSFam Zheng q->sq.tail * NVME_SQ_ENTRY_BYTES, cmd, sizeof(*cmd)); 477bdd6a90aSFam Zheng q->sq.tail = (q->sq.tail + 1) % NVME_QUEUE_SIZE; 478bdd6a90aSFam Zheng q->need_kick++; 479b75fd5f5SStefan Hajnoczi nvme_kick(q); 480b75fd5f5SStefan Hajnoczi nvme_process_completion(q); 481bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 482bdd6a90aSFam Zheng } 483bdd6a90aSFam Zheng 48408d54067SPhilippe Mathieu-Daudé static void nvme_admin_cmd_sync_cb(void *opaque, int ret) 485bdd6a90aSFam Zheng { 486bdd6a90aSFam Zheng int *pret = opaque; 487bdd6a90aSFam Zheng *pret = ret; 4884720cbeeSKevin Wolf aio_wait_kick(); 489bdd6a90aSFam Zheng } 490bdd6a90aSFam Zheng 49108d54067SPhilippe Mathieu-Daudé static int nvme_admin_cmd_sync(BlockDriverState *bs, NvmeCmd *cmd) 492bdd6a90aSFam Zheng { 49308d54067SPhilippe Mathieu-Daudé BDRVNVMeState *s = bs->opaque; 49408d54067SPhilippe Mathieu-Daudé NVMeQueuePair *q = s->queues[INDEX_ADMIN]; 495073a0697SPhilippe Mathieu-Daudé AioContext *aio_context = bdrv_get_aio_context(bs); 496bdd6a90aSFam Zheng NVMeRequest *req; 497bdd6a90aSFam Zheng int ret = -EINPROGRESS; 498bdd6a90aSFam Zheng req = nvme_get_free_req(q); 499bdd6a90aSFam Zheng if (!req) { 500bdd6a90aSFam Zheng return -EBUSY; 501bdd6a90aSFam Zheng } 50208d54067SPhilippe Mathieu-Daudé nvme_submit_command(q, req, cmd, nvme_admin_cmd_sync_cb, &ret); 503bdd6a90aSFam Zheng 504073a0697SPhilippe Mathieu-Daudé AIO_WAIT_WHILE(aio_context, ret == -EINPROGRESS); 505bdd6a90aSFam Zheng return ret; 506bdd6a90aSFam Zheng } 507bdd6a90aSFam Zheng 5087a5f00ddSPhilippe Mathieu-Daudé /* Returns true on success, false on failure. */ 5097a5f00ddSPhilippe Mathieu-Daudé static bool nvme_identify(BlockDriverState *bs, int namespace, Error **errp) 510bdd6a90aSFam Zheng { 511bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 5127a5f00ddSPhilippe Mathieu-Daudé bool ret = false; 5137d3b214aSPhilippe Mathieu-Daudé union { 5147d3b214aSPhilippe Mathieu-Daudé NvmeIdCtrl ctrl; 5157d3b214aSPhilippe Mathieu-Daudé NvmeIdNs ns; 5167d3b214aSPhilippe Mathieu-Daudé } *id; 517118d1b6aSMaxim Levitsky NvmeLBAF *lbaf; 518e0dd95e3SMaxim Levitsky uint16_t oncs; 5191120407bSMax Reitz int r; 520bdd6a90aSFam Zheng uint64_t iova; 521bdd6a90aSFam Zheng NvmeCmd cmd = { 522bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_IDENTIFY, 523bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(0x1), 524bdd6a90aSFam Zheng }; 5250aecd060SEric Auger size_t id_size = QEMU_ALIGN_UP(sizeof(*id), qemu_real_host_page_size); 526bdd6a90aSFam Zheng 5270aecd060SEric Auger id = qemu_try_memalign(qemu_real_host_page_size, id_size); 5284d980939SPhilippe Mathieu-Daudé if (!id) { 529bdd6a90aSFam Zheng error_setg(errp, "Cannot allocate buffer for identify response"); 530bdd6a90aSFam Zheng goto out; 531bdd6a90aSFam Zheng } 5320aecd060SEric Auger r = qemu_vfio_dma_map(s->vfio, id, id_size, true, &iova); 533bdd6a90aSFam Zheng if (r) { 534bdd6a90aSFam Zheng error_setg(errp, "Cannot map buffer for DMA"); 535bdd6a90aSFam Zheng goto out; 536bdd6a90aSFam Zheng } 537bdd6a90aSFam Zheng 5380aecd060SEric Auger memset(id, 0, id_size); 5392ed84693SPhilippe Mathieu-Daudé cmd.dptr.prp1 = cpu_to_le64(iova); 54008d54067SPhilippe Mathieu-Daudé if (nvme_admin_cmd_sync(bs, &cmd)) { 541bdd6a90aSFam Zheng error_setg(errp, "Failed to identify controller"); 542bdd6a90aSFam Zheng goto out; 543bdd6a90aSFam Zheng } 544bdd6a90aSFam Zheng 5457d3b214aSPhilippe Mathieu-Daudé if (le32_to_cpu(id->ctrl.nn) < namespace) { 546bdd6a90aSFam Zheng error_setg(errp, "Invalid namespace"); 547bdd6a90aSFam Zheng goto out; 548bdd6a90aSFam Zheng } 5497d3b214aSPhilippe Mathieu-Daudé s->write_cache_supported = le32_to_cpu(id->ctrl.vwc) & 0x1; 5507d3b214aSPhilippe Mathieu-Daudé s->max_transfer = (id->ctrl.mdts ? 1 << id->ctrl.mdts : 0) * s->page_size; 551bdd6a90aSFam Zheng /* For now the page list buffer per command is one page, to hold at most 552bdd6a90aSFam Zheng * s->page_size / sizeof(uint64_t) entries. */ 553bdd6a90aSFam Zheng s->max_transfer = MIN_NON_ZERO(s->max_transfer, 554bdd6a90aSFam Zheng s->page_size / sizeof(uint64_t) * s->page_size); 555bdd6a90aSFam Zheng 5567d3b214aSPhilippe Mathieu-Daudé oncs = le16_to_cpu(id->ctrl.oncs); 55769265150SKlaus Jensen s->supports_write_zeroes = !!(oncs & NVME_ONCS_WRITE_ZEROES); 558e87a09d6SMaxim Levitsky s->supports_discard = !!(oncs & NVME_ONCS_DSM); 559e0dd95e3SMaxim Levitsky 5600aecd060SEric Auger memset(id, 0, id_size); 561bdd6a90aSFam Zheng cmd.cdw10 = 0; 562bdd6a90aSFam Zheng cmd.nsid = cpu_to_le32(namespace); 56308d54067SPhilippe Mathieu-Daudé if (nvme_admin_cmd_sync(bs, &cmd)) { 564bdd6a90aSFam Zheng error_setg(errp, "Failed to identify namespace"); 565bdd6a90aSFam Zheng goto out; 566bdd6a90aSFam Zheng } 567bdd6a90aSFam Zheng 5687d3b214aSPhilippe Mathieu-Daudé s->nsze = le64_to_cpu(id->ns.nsze); 5697d3b214aSPhilippe Mathieu-Daudé lbaf = &id->ns.lbaf[NVME_ID_NS_FLBAS_INDEX(id->ns.flbas)]; 570bdd6a90aSFam Zheng 5717d3b214aSPhilippe Mathieu-Daudé if (NVME_ID_NS_DLFEAT_WRITE_ZEROES(id->ns.dlfeat) && 5727d3b214aSPhilippe Mathieu-Daudé NVME_ID_NS_DLFEAT_READ_BEHAVIOR(id->ns.dlfeat) == 573e0dd95e3SMaxim Levitsky NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES) { 574e0dd95e3SMaxim Levitsky bs->supported_write_flags |= BDRV_REQ_MAY_UNMAP; 575e0dd95e3SMaxim Levitsky } 576e0dd95e3SMaxim Levitsky 577118d1b6aSMaxim Levitsky if (lbaf->ms) { 578118d1b6aSMaxim Levitsky error_setg(errp, "Namespaces with metadata are not yet supported"); 579118d1b6aSMaxim Levitsky goto out; 580118d1b6aSMaxim Levitsky } 581118d1b6aSMaxim Levitsky 5821120407bSMax Reitz if (lbaf->ds < BDRV_SECTOR_BITS || lbaf->ds > 12 || 5831120407bSMax Reitz (1 << lbaf->ds) > s->page_size) 5841120407bSMax Reitz { 5851120407bSMax Reitz error_setg(errp, "Namespace has unsupported block size (2^%d)", 5861120407bSMax Reitz lbaf->ds); 587118d1b6aSMaxim Levitsky goto out; 588118d1b6aSMaxim Levitsky } 589118d1b6aSMaxim Levitsky 5907a5f00ddSPhilippe Mathieu-Daudé ret = true; 591118d1b6aSMaxim Levitsky s->blkshift = lbaf->ds; 592bdd6a90aSFam Zheng out: 5934d980939SPhilippe Mathieu-Daudé qemu_vfio_dma_unmap(s->vfio, id); 5944d980939SPhilippe Mathieu-Daudé qemu_vfree(id); 5957a5f00ddSPhilippe Mathieu-Daudé 5967a5f00ddSPhilippe Mathieu-Daudé return ret; 597bdd6a90aSFam Zheng } 598bdd6a90aSFam Zheng 5997a1fb2efSPhilippe Mathieu-Daudé static bool nvme_poll_queue(NVMeQueuePair *q) 600bdd6a90aSFam Zheng { 601bdd6a90aSFam Zheng bool progress = false; 602bdd6a90aSFam Zheng 6032446e0e2SStefan Hajnoczi const size_t cqe_offset = q->cq.head * NVME_CQ_ENTRY_BYTES; 6042446e0e2SStefan Hajnoczi NvmeCqe *cqe = (NvmeCqe *)&q->cq.queue[cqe_offset]; 6052446e0e2SStefan Hajnoczi 6061c914cd1SPhilippe Mathieu-Daudé trace_nvme_poll_queue(q->s, q->index); 6072446e0e2SStefan Hajnoczi /* 6082446e0e2SStefan Hajnoczi * Do an early check for completions. q->lock isn't needed because 6092446e0e2SStefan Hajnoczi * nvme_process_completion() only runs in the event loop thread and 6102446e0e2SStefan Hajnoczi * cannot race with itself. 6112446e0e2SStefan Hajnoczi */ 6122446e0e2SStefan Hajnoczi if ((le16_to_cpu(cqe->status) & 0x1) == q->cq_phase) { 6137a1fb2efSPhilippe Mathieu-Daudé return false; 6142446e0e2SStefan Hajnoczi } 6152446e0e2SStefan Hajnoczi 616bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 617b75fd5f5SStefan Hajnoczi while (nvme_process_completion(q)) { 618bdd6a90aSFam Zheng /* Keep polling */ 619bdd6a90aSFam Zheng progress = true; 620bdd6a90aSFam Zheng } 621bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 6227a1fb2efSPhilippe Mathieu-Daudé 6237a1fb2efSPhilippe Mathieu-Daudé return progress; 6247a1fb2efSPhilippe Mathieu-Daudé } 6257a1fb2efSPhilippe Mathieu-Daudé 6267a1fb2efSPhilippe Mathieu-Daudé static bool nvme_poll_queues(BDRVNVMeState *s) 6277a1fb2efSPhilippe Mathieu-Daudé { 6287a1fb2efSPhilippe Mathieu-Daudé bool progress = false; 6297a1fb2efSPhilippe Mathieu-Daudé int i; 6307a1fb2efSPhilippe Mathieu-Daudé 6311b539bd6SPhilippe Mathieu-Daudé for (i = 0; i < s->queue_count; i++) { 6327a1fb2efSPhilippe Mathieu-Daudé if (nvme_poll_queue(s->queues[i])) { 6337a1fb2efSPhilippe Mathieu-Daudé progress = true; 6347a1fb2efSPhilippe Mathieu-Daudé } 635bdd6a90aSFam Zheng } 636bdd6a90aSFam Zheng return progress; 637bdd6a90aSFam Zheng } 638bdd6a90aSFam Zheng 639bdd6a90aSFam Zheng static void nvme_handle_event(EventNotifier *n) 640bdd6a90aSFam Zheng { 641b111b3fcSPhilippe Mathieu-Daudé BDRVNVMeState *s = container_of(n, BDRVNVMeState, 642b111b3fcSPhilippe Mathieu-Daudé irq_notifier[MSIX_SHARED_IRQ_IDX]); 643bdd6a90aSFam Zheng 644bdd6a90aSFam Zheng trace_nvme_handle_event(s); 645bdd6a90aSFam Zheng event_notifier_test_and_clear(n); 646bdd6a90aSFam Zheng nvme_poll_queues(s); 647bdd6a90aSFam Zheng } 648bdd6a90aSFam Zheng 649bdd6a90aSFam Zheng static bool nvme_add_io_queue(BlockDriverState *bs, Error **errp) 650bdd6a90aSFam Zheng { 651bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 6521b539bd6SPhilippe Mathieu-Daudé unsigned n = s->queue_count; 653bdd6a90aSFam Zheng NVMeQueuePair *q; 654bdd6a90aSFam Zheng NvmeCmd cmd; 6551b539bd6SPhilippe Mathieu-Daudé unsigned queue_size = NVME_QUEUE_SIZE; 656bdd6a90aSFam Zheng 65776a24781SPhilippe Mathieu-Daudé assert(n <= UINT16_MAX); 6580a28b02eSPhilippe Mathieu-Daudé q = nvme_create_queue_pair(s, bdrv_get_aio_context(bs), 6590a28b02eSPhilippe Mathieu-Daudé n, queue_size, errp); 660bdd6a90aSFam Zheng if (!q) { 661bdd6a90aSFam Zheng return false; 662bdd6a90aSFam Zheng } 663bdd6a90aSFam Zheng cmd = (NvmeCmd) { 664bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_CREATE_CQ, 665c26f2173SKlaus Jensen .dptr.prp1 = cpu_to_le64(q->cq.iova), 66676a24781SPhilippe Mathieu-Daudé .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n), 66776a24781SPhilippe Mathieu-Daudé .cdw11 = cpu_to_le32(NVME_CQ_IEN | NVME_CQ_PC), 668bdd6a90aSFam Zheng }; 66908d54067SPhilippe Mathieu-Daudé if (nvme_admin_cmd_sync(bs, &cmd)) { 6701b539bd6SPhilippe Mathieu-Daudé error_setg(errp, "Failed to create CQ io queue [%u]", n); 671c8edbfb2SPhilippe Mathieu-Daudé goto out_error; 672bdd6a90aSFam Zheng } 673bdd6a90aSFam Zheng cmd = (NvmeCmd) { 674bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_CREATE_SQ, 675c26f2173SKlaus Jensen .dptr.prp1 = cpu_to_le64(q->sq.iova), 67676a24781SPhilippe Mathieu-Daudé .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n), 67776a24781SPhilippe Mathieu-Daudé .cdw11 = cpu_to_le32(NVME_SQ_PC | (n << 16)), 678bdd6a90aSFam Zheng }; 67908d54067SPhilippe Mathieu-Daudé if (nvme_admin_cmd_sync(bs, &cmd)) { 6801b539bd6SPhilippe Mathieu-Daudé error_setg(errp, "Failed to create SQ io queue [%u]", n); 681c8edbfb2SPhilippe Mathieu-Daudé goto out_error; 682bdd6a90aSFam Zheng } 683bdd6a90aSFam Zheng s->queues = g_renew(NVMeQueuePair *, s->queues, n + 1); 684bdd6a90aSFam Zheng s->queues[n] = q; 6851b539bd6SPhilippe Mathieu-Daudé s->queue_count++; 686bdd6a90aSFam Zheng return true; 687c8edbfb2SPhilippe Mathieu-Daudé out_error: 688c8edbfb2SPhilippe Mathieu-Daudé nvme_free_queue_pair(q); 689c8edbfb2SPhilippe Mathieu-Daudé return false; 690bdd6a90aSFam Zheng } 691bdd6a90aSFam Zheng 692bdd6a90aSFam Zheng static bool nvme_poll_cb(void *opaque) 693bdd6a90aSFam Zheng { 694bdd6a90aSFam Zheng EventNotifier *e = opaque; 695b111b3fcSPhilippe Mathieu-Daudé BDRVNVMeState *s = container_of(e, BDRVNVMeState, 696b111b3fcSPhilippe Mathieu-Daudé irq_notifier[MSIX_SHARED_IRQ_IDX]); 697bdd6a90aSFam Zheng 698b3ac2b94SSimran Singhal return nvme_poll_queues(s); 699bdd6a90aSFam Zheng } 700bdd6a90aSFam Zheng 701bdd6a90aSFam Zheng static int nvme_init(BlockDriverState *bs, const char *device, int namespace, 702bdd6a90aSFam Zheng Error **errp) 703bdd6a90aSFam Zheng { 704bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 70552b75ea8SPhilippe Mathieu-Daudé NVMeQueuePair *q; 7060a28b02eSPhilippe Mathieu-Daudé AioContext *aio_context = bdrv_get_aio_context(bs); 707bdd6a90aSFam Zheng int ret; 708bdd6a90aSFam Zheng uint64_t cap; 709bdd6a90aSFam Zheng uint64_t timeout_ms; 710bdd6a90aSFam Zheng uint64_t deadline, now; 7119406e0d9SPhilippe Mathieu-Daudé volatile NvmeBar *regs = NULL; 712bdd6a90aSFam Zheng 713bdd6a90aSFam Zheng qemu_co_mutex_init(&s->dma_map_lock); 714bdd6a90aSFam Zheng qemu_co_queue_init(&s->dma_flush_queue); 715cc61b074SMax Reitz s->device = g_strdup(device); 716bdd6a90aSFam Zheng s->nsid = namespace; 717bdd6a90aSFam Zheng s->aio_context = bdrv_get_aio_context(bs); 718b111b3fcSPhilippe Mathieu-Daudé ret = event_notifier_init(&s->irq_notifier[MSIX_SHARED_IRQ_IDX], 0); 719bdd6a90aSFam Zheng if (ret) { 720bdd6a90aSFam Zheng error_setg(errp, "Failed to init event notifier"); 721bdd6a90aSFam Zheng return ret; 722bdd6a90aSFam Zheng } 723bdd6a90aSFam Zheng 724bdd6a90aSFam Zheng s->vfio = qemu_vfio_open_pci(device, errp); 725bdd6a90aSFam Zheng if (!s->vfio) { 726bdd6a90aSFam Zheng ret = -EINVAL; 7279582f357SFam Zheng goto out; 728bdd6a90aSFam Zheng } 729bdd6a90aSFam Zheng 73037d7a45aSPhilippe Mathieu-Daudé regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, sizeof(NvmeBar), 731b02c01a5SPhilippe Mathieu-Daudé PROT_READ | PROT_WRITE, errp); 73237d7a45aSPhilippe Mathieu-Daudé if (!regs) { 733bdd6a90aSFam Zheng ret = -EINVAL; 7349582f357SFam Zheng goto out; 735bdd6a90aSFam Zheng } 736bdd6a90aSFam Zheng /* Perform initialize sequence as described in NVMe spec "7.6.1 737bdd6a90aSFam Zheng * Initialization". */ 738bdd6a90aSFam Zheng 7399406e0d9SPhilippe Mathieu-Daudé cap = le64_to_cpu(regs->cap); 74015b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability_raw(cap); 74115b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Maximum Queue Entries Supported", 74215b2260bSPhilippe Mathieu-Daudé 1 + NVME_CAP_MQES(cap)); 74315b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Contiguous Queues Required", 74415b2260bSPhilippe Mathieu-Daudé NVME_CAP_CQR(cap)); 74515b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Doorbell Stride", 74615b2260bSPhilippe Mathieu-Daudé 2 << (2 + NVME_CAP_DSTRD(cap))); 74715b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Subsystem Reset Supported", 74815b2260bSPhilippe Mathieu-Daudé NVME_CAP_NSSRS(cap)); 74915b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Memory Page Size Minimum", 75015b2260bSPhilippe Mathieu-Daudé 1 << (12 + NVME_CAP_MPSMIN(cap))); 75115b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Memory Page Size Maximum", 75215b2260bSPhilippe Mathieu-Daudé 1 << (12 + NVME_CAP_MPSMAX(cap))); 753fad1eb68SPhilippe Mathieu-Daudé if (!NVME_CAP_CSS(cap)) { 754bdd6a90aSFam Zheng error_setg(errp, "Device doesn't support NVMe command set"); 755bdd6a90aSFam Zheng ret = -EINVAL; 7569582f357SFam Zheng goto out; 757bdd6a90aSFam Zheng } 758bdd6a90aSFam Zheng 759a652a3ecSPhilippe Mathieu-Daudé s->page_size = 1u << (12 + NVME_CAP_MPSMIN(cap)); 760fad1eb68SPhilippe Mathieu-Daudé s->doorbell_scale = (4 << NVME_CAP_DSTRD(cap)) / sizeof(uint32_t); 761bdd6a90aSFam Zheng bs->bl.opt_mem_alignment = s->page_size; 762c8228ac3SPhilippe Mathieu-Daudé bs->bl.request_alignment = s->page_size; 763fad1eb68SPhilippe Mathieu-Daudé timeout_ms = MIN(500 * NVME_CAP_TO(cap), 30000); 764bdd6a90aSFam Zheng 765bdd6a90aSFam Zheng /* Reset device to get a clean state. */ 7669406e0d9SPhilippe Mathieu-Daudé regs->cc = cpu_to_le32(le32_to_cpu(regs->cc) & 0xFE); 767bdd6a90aSFam Zheng /* Wait for CSTS.RDY = 0. */ 768e4f310feSPhilippe Mathieu-Daudé deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCALE_MS; 769fad1eb68SPhilippe Mathieu-Daudé while (NVME_CSTS_RDY(le32_to_cpu(regs->csts))) { 770bdd6a90aSFam Zheng if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 771bdd6a90aSFam Zheng error_setg(errp, "Timeout while waiting for device to reset (%" 772bdd6a90aSFam Zheng PRId64 " ms)", 773bdd6a90aSFam Zheng timeout_ms); 774bdd6a90aSFam Zheng ret = -ETIMEDOUT; 7759582f357SFam Zheng goto out; 776bdd6a90aSFam Zheng } 777bdd6a90aSFam Zheng } 778bdd6a90aSFam Zheng 779f6845323SPhilippe Mathieu-Daudé s->doorbells = qemu_vfio_pci_map_bar(s->vfio, 0, sizeof(NvmeBar), 780f6845323SPhilippe Mathieu-Daudé NVME_DOORBELL_SIZE, PROT_WRITE, errp); 781f6845323SPhilippe Mathieu-Daudé if (!s->doorbells) { 782f6845323SPhilippe Mathieu-Daudé ret = -EINVAL; 783f6845323SPhilippe Mathieu-Daudé goto out; 784f6845323SPhilippe Mathieu-Daudé } 785f6845323SPhilippe Mathieu-Daudé 786bdd6a90aSFam Zheng /* Set up admin queue. */ 787bdd6a90aSFam Zheng s->queues = g_new(NVMeQueuePair *, 1); 78852b75ea8SPhilippe Mathieu-Daudé q = nvme_create_queue_pair(s, aio_context, 0, NVME_QUEUE_SIZE, errp); 78952b75ea8SPhilippe Mathieu-Daudé if (!q) { 790bdd6a90aSFam Zheng ret = -EINVAL; 7919582f357SFam Zheng goto out; 792bdd6a90aSFam Zheng } 79352b75ea8SPhilippe Mathieu-Daudé s->queues[INDEX_ADMIN] = q; 7941b539bd6SPhilippe Mathieu-Daudé s->queue_count = 1; 7953c363c07SPhilippe Mathieu-Daudé QEMU_BUILD_BUG_ON((NVME_QUEUE_SIZE - 1) & 0xF000); 7963c363c07SPhilippe Mathieu-Daudé regs->aqa = cpu_to_le32(((NVME_QUEUE_SIZE - 1) << AQA_ACQS_SHIFT) | 7973c363c07SPhilippe Mathieu-Daudé ((NVME_QUEUE_SIZE - 1) << AQA_ASQS_SHIFT)); 79852b75ea8SPhilippe Mathieu-Daudé regs->asq = cpu_to_le64(q->sq.iova); 79952b75ea8SPhilippe Mathieu-Daudé regs->acq = cpu_to_le64(q->cq.iova); 800bdd6a90aSFam Zheng 801bdd6a90aSFam Zheng /* After setting up all control registers we can enable device now. */ 802fad1eb68SPhilippe Mathieu-Daudé regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << CC_IOCQES_SHIFT) | 803fad1eb68SPhilippe Mathieu-Daudé (ctz32(NVME_SQ_ENTRY_BYTES) << CC_IOSQES_SHIFT) | 804fad1eb68SPhilippe Mathieu-Daudé CC_EN_MASK); 805bdd6a90aSFam Zheng /* Wait for CSTS.RDY = 1. */ 806bdd6a90aSFam Zheng now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 807eefffb02SPhilippe Mathieu-Daudé deadline = now + timeout_ms * SCALE_MS; 808fad1eb68SPhilippe Mathieu-Daudé while (!NVME_CSTS_RDY(le32_to_cpu(regs->csts))) { 809bdd6a90aSFam Zheng if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 810bdd6a90aSFam Zheng error_setg(errp, "Timeout while waiting for device to start (%" 811bdd6a90aSFam Zheng PRId64 " ms)", 812bdd6a90aSFam Zheng timeout_ms); 813bdd6a90aSFam Zheng ret = -ETIMEDOUT; 8149582f357SFam Zheng goto out; 815bdd6a90aSFam Zheng } 816bdd6a90aSFam Zheng } 817bdd6a90aSFam Zheng 818b111b3fcSPhilippe Mathieu-Daudé ret = qemu_vfio_pci_init_irq(s->vfio, s->irq_notifier, 819bdd6a90aSFam Zheng VFIO_PCI_MSIX_IRQ_INDEX, errp); 820bdd6a90aSFam Zheng if (ret) { 8219582f357SFam Zheng goto out; 822bdd6a90aSFam Zheng } 823b111b3fcSPhilippe Mathieu-Daudé aio_set_event_notifier(bdrv_get_aio_context(bs), 824b111b3fcSPhilippe Mathieu-Daudé &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 825bdd6a90aSFam Zheng false, nvme_handle_event, nvme_poll_cb); 826bdd6a90aSFam Zheng 8277a5f00ddSPhilippe Mathieu-Daudé if (!nvme_identify(bs, namespace, errp)) { 828bdd6a90aSFam Zheng ret = -EIO; 8299582f357SFam Zheng goto out; 830bdd6a90aSFam Zheng } 831bdd6a90aSFam Zheng 832bdd6a90aSFam Zheng /* Set up command queues. */ 833bdd6a90aSFam Zheng if (!nvme_add_io_queue(bs, errp)) { 834bdd6a90aSFam Zheng ret = -EIO; 835bdd6a90aSFam Zheng } 8369582f357SFam Zheng out: 83737d7a45aSPhilippe Mathieu-Daudé if (regs) { 83837d7a45aSPhilippe Mathieu-Daudé qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)regs, 0, sizeof(NvmeBar)); 83937d7a45aSPhilippe Mathieu-Daudé } 84037d7a45aSPhilippe Mathieu-Daudé 8419582f357SFam Zheng /* Cleaning up is done in nvme_file_open() upon error. */ 842bdd6a90aSFam Zheng return ret; 843bdd6a90aSFam Zheng } 844bdd6a90aSFam Zheng 845bdd6a90aSFam Zheng /* Parse a filename in the format of nvme://XXXX:XX:XX.X/X. Example: 846bdd6a90aSFam Zheng * 847bdd6a90aSFam Zheng * nvme://0000:44:00.0/1 848bdd6a90aSFam Zheng * 849bdd6a90aSFam Zheng * where the "nvme://" is a fixed form of the protocol prefix, the middle part 850bdd6a90aSFam Zheng * is the PCI address, and the last part is the namespace number starting from 851bdd6a90aSFam Zheng * 1 according to the NVMe spec. */ 852bdd6a90aSFam Zheng static void nvme_parse_filename(const char *filename, QDict *options, 853bdd6a90aSFam Zheng Error **errp) 854bdd6a90aSFam Zheng { 855bdd6a90aSFam Zheng int pref = strlen("nvme://"); 856bdd6a90aSFam Zheng 857bdd6a90aSFam Zheng if (strlen(filename) > pref && !strncmp(filename, "nvme://", pref)) { 858bdd6a90aSFam Zheng const char *tmp = filename + pref; 859bdd6a90aSFam Zheng char *device; 860bdd6a90aSFam Zheng const char *namespace; 861bdd6a90aSFam Zheng unsigned long ns; 862bdd6a90aSFam Zheng const char *slash = strchr(tmp, '/'); 863bdd6a90aSFam Zheng if (!slash) { 864625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, tmp); 865bdd6a90aSFam Zheng return; 866bdd6a90aSFam Zheng } 867bdd6a90aSFam Zheng device = g_strndup(tmp, slash - tmp); 868625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, device); 869bdd6a90aSFam Zheng g_free(device); 870bdd6a90aSFam Zheng namespace = slash + 1; 871bdd6a90aSFam Zheng if (*namespace && qemu_strtoul(namespace, NULL, 10, &ns)) { 872bdd6a90aSFam Zheng error_setg(errp, "Invalid namespace '%s', positive number expected", 873bdd6a90aSFam Zheng namespace); 874bdd6a90aSFam Zheng return; 875bdd6a90aSFam Zheng } 876625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_NAMESPACE, 877625eaca9SLaurent Vivier *namespace ? namespace : "1"); 878bdd6a90aSFam Zheng } 879bdd6a90aSFam Zheng } 880bdd6a90aSFam Zheng 881bdd6a90aSFam Zheng static int nvme_enable_disable_write_cache(BlockDriverState *bs, bool enable, 882bdd6a90aSFam Zheng Error **errp) 883bdd6a90aSFam Zheng { 884bdd6a90aSFam Zheng int ret; 885bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 886bdd6a90aSFam Zheng NvmeCmd cmd = { 887bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_SET_FEATURES, 888bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 889bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(0x06), 890bdd6a90aSFam Zheng .cdw11 = cpu_to_le32(enable ? 0x01 : 0x00), 891bdd6a90aSFam Zheng }; 892bdd6a90aSFam Zheng 89308d54067SPhilippe Mathieu-Daudé ret = nvme_admin_cmd_sync(bs, &cmd); 894bdd6a90aSFam Zheng if (ret) { 895bdd6a90aSFam Zheng error_setg(errp, "Failed to configure NVMe write cache"); 896bdd6a90aSFam Zheng } 897bdd6a90aSFam Zheng return ret; 898bdd6a90aSFam Zheng } 899bdd6a90aSFam Zheng 900bdd6a90aSFam Zheng static void nvme_close(BlockDriverState *bs) 901bdd6a90aSFam Zheng { 902bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 903bdd6a90aSFam Zheng 9041b539bd6SPhilippe Mathieu-Daudé for (unsigned i = 0; i < s->queue_count; ++i) { 905b75fd5f5SStefan Hajnoczi nvme_free_queue_pair(s->queues[i]); 906bdd6a90aSFam Zheng } 9079582f357SFam Zheng g_free(s->queues); 908b111b3fcSPhilippe Mathieu-Daudé aio_set_event_notifier(bdrv_get_aio_context(bs), 909b111b3fcSPhilippe Mathieu-Daudé &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 910bdd6a90aSFam Zheng false, NULL, NULL); 911b111b3fcSPhilippe Mathieu-Daudé event_notifier_cleanup(&s->irq_notifier[MSIX_SHARED_IRQ_IDX]); 912f6845323SPhilippe Mathieu-Daudé qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->doorbells, 913f6845323SPhilippe Mathieu-Daudé sizeof(NvmeBar), NVME_DOORBELL_SIZE); 914bdd6a90aSFam Zheng qemu_vfio_close(s->vfio); 915cc61b074SMax Reitz 916cc61b074SMax Reitz g_free(s->device); 917bdd6a90aSFam Zheng } 918bdd6a90aSFam Zheng 919bdd6a90aSFam Zheng static int nvme_file_open(BlockDriverState *bs, QDict *options, int flags, 920bdd6a90aSFam Zheng Error **errp) 921bdd6a90aSFam Zheng { 922bdd6a90aSFam Zheng const char *device; 923bdd6a90aSFam Zheng QemuOpts *opts; 924bdd6a90aSFam Zheng int namespace; 925bdd6a90aSFam Zheng int ret; 926bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 927bdd6a90aSFam Zheng 928e0dd95e3SMaxim Levitsky bs->supported_write_flags = BDRV_REQ_FUA; 929e0dd95e3SMaxim Levitsky 930bdd6a90aSFam Zheng opts = qemu_opts_create(&runtime_opts, NULL, 0, &error_abort); 931bdd6a90aSFam Zheng qemu_opts_absorb_qdict(opts, options, &error_abort); 932bdd6a90aSFam Zheng device = qemu_opt_get(opts, NVME_BLOCK_OPT_DEVICE); 933bdd6a90aSFam Zheng if (!device) { 934bdd6a90aSFam Zheng error_setg(errp, "'" NVME_BLOCK_OPT_DEVICE "' option is required"); 935bdd6a90aSFam Zheng qemu_opts_del(opts); 936bdd6a90aSFam Zheng return -EINVAL; 937bdd6a90aSFam Zheng } 938bdd6a90aSFam Zheng 939bdd6a90aSFam Zheng namespace = qemu_opt_get_number(opts, NVME_BLOCK_OPT_NAMESPACE, 1); 940bdd6a90aSFam Zheng ret = nvme_init(bs, device, namespace, errp); 941bdd6a90aSFam Zheng qemu_opts_del(opts); 942bdd6a90aSFam Zheng if (ret) { 943bdd6a90aSFam Zheng goto fail; 944bdd6a90aSFam Zheng } 945bdd6a90aSFam Zheng if (flags & BDRV_O_NOCACHE) { 946bdd6a90aSFam Zheng if (!s->write_cache_supported) { 947bdd6a90aSFam Zheng error_setg(errp, 948bdd6a90aSFam Zheng "NVMe controller doesn't support write cache configuration"); 949bdd6a90aSFam Zheng ret = -EINVAL; 950bdd6a90aSFam Zheng } else { 951bdd6a90aSFam Zheng ret = nvme_enable_disable_write_cache(bs, !(flags & BDRV_O_NOCACHE), 952bdd6a90aSFam Zheng errp); 953bdd6a90aSFam Zheng } 954bdd6a90aSFam Zheng if (ret) { 955bdd6a90aSFam Zheng goto fail; 956bdd6a90aSFam Zheng } 957bdd6a90aSFam Zheng } 958bdd6a90aSFam Zheng return 0; 959bdd6a90aSFam Zheng fail: 960bdd6a90aSFam Zheng nvme_close(bs); 961bdd6a90aSFam Zheng return ret; 962bdd6a90aSFam Zheng } 963bdd6a90aSFam Zheng 964bdd6a90aSFam Zheng static int64_t nvme_getlength(BlockDriverState *bs) 965bdd6a90aSFam Zheng { 966bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 967118d1b6aSMaxim Levitsky return s->nsze << s->blkshift; 968118d1b6aSMaxim Levitsky } 969bdd6a90aSFam Zheng 9701120407bSMax Reitz static uint32_t nvme_get_blocksize(BlockDriverState *bs) 971118d1b6aSMaxim Levitsky { 972118d1b6aSMaxim Levitsky BDRVNVMeState *s = bs->opaque; 9731120407bSMax Reitz assert(s->blkshift >= BDRV_SECTOR_BITS && s->blkshift <= 12); 9741120407bSMax Reitz return UINT32_C(1) << s->blkshift; 975118d1b6aSMaxim Levitsky } 976118d1b6aSMaxim Levitsky 977118d1b6aSMaxim Levitsky static int nvme_probe_blocksizes(BlockDriverState *bs, BlockSizes *bsz) 978118d1b6aSMaxim Levitsky { 9791120407bSMax Reitz uint32_t blocksize = nvme_get_blocksize(bs); 980118d1b6aSMaxim Levitsky bsz->phys = blocksize; 981118d1b6aSMaxim Levitsky bsz->log = blocksize; 982118d1b6aSMaxim Levitsky return 0; 983bdd6a90aSFam Zheng } 984bdd6a90aSFam Zheng 985bdd6a90aSFam Zheng /* Called with s->dma_map_lock */ 986bdd6a90aSFam Zheng static coroutine_fn int nvme_cmd_unmap_qiov(BlockDriverState *bs, 987bdd6a90aSFam Zheng QEMUIOVector *qiov) 988bdd6a90aSFam Zheng { 989bdd6a90aSFam Zheng int r = 0; 990bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 991bdd6a90aSFam Zheng 992bdd6a90aSFam Zheng s->dma_map_count -= qiov->size; 993bdd6a90aSFam Zheng if (!s->dma_map_count && !qemu_co_queue_empty(&s->dma_flush_queue)) { 994bdd6a90aSFam Zheng r = qemu_vfio_dma_reset_temporary(s->vfio); 995bdd6a90aSFam Zheng if (!r) { 996bdd6a90aSFam Zheng qemu_co_queue_restart_all(&s->dma_flush_queue); 997bdd6a90aSFam Zheng } 998bdd6a90aSFam Zheng } 999bdd6a90aSFam Zheng return r; 1000bdd6a90aSFam Zheng } 1001bdd6a90aSFam Zheng 1002bdd6a90aSFam Zheng /* Called with s->dma_map_lock */ 1003bdd6a90aSFam Zheng static coroutine_fn int nvme_cmd_map_qiov(BlockDriverState *bs, NvmeCmd *cmd, 1004bdd6a90aSFam Zheng NVMeRequest *req, QEMUIOVector *qiov) 1005bdd6a90aSFam Zheng { 1006bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1007bdd6a90aSFam Zheng uint64_t *pagelist = req->prp_list_page; 1008bdd6a90aSFam Zheng int i, j, r; 1009bdd6a90aSFam Zheng int entries = 0; 1010bdd6a90aSFam Zheng 1011bdd6a90aSFam Zheng assert(qiov->size); 1012bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(qiov->size, s->page_size)); 1013bdd6a90aSFam Zheng assert(qiov->size / s->page_size <= s->page_size / sizeof(uint64_t)); 1014bdd6a90aSFam Zheng for (i = 0; i < qiov->niov; ++i) { 1015bdd6a90aSFam Zheng bool retry = true; 1016bdd6a90aSFam Zheng uint64_t iova; 1017bdd6a90aSFam Zheng try_map: 1018bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, 1019bdd6a90aSFam Zheng qiov->iov[i].iov_base, 1020bdd6a90aSFam Zheng qiov->iov[i].iov_len, 1021bdd6a90aSFam Zheng true, &iova); 1022bdd6a90aSFam Zheng if (r == -ENOMEM && retry) { 1023bdd6a90aSFam Zheng retry = false; 1024bdd6a90aSFam Zheng trace_nvme_dma_flush_queue_wait(s); 1025bdd6a90aSFam Zheng if (s->dma_map_count) { 1026bdd6a90aSFam Zheng trace_nvme_dma_map_flush(s); 1027bdd6a90aSFam Zheng qemu_co_queue_wait(&s->dma_flush_queue, &s->dma_map_lock); 1028bdd6a90aSFam Zheng } else { 1029bdd6a90aSFam Zheng r = qemu_vfio_dma_reset_temporary(s->vfio); 1030bdd6a90aSFam Zheng if (r) { 1031bdd6a90aSFam Zheng goto fail; 1032bdd6a90aSFam Zheng } 1033bdd6a90aSFam Zheng } 1034bdd6a90aSFam Zheng goto try_map; 1035bdd6a90aSFam Zheng } 1036bdd6a90aSFam Zheng if (r) { 1037bdd6a90aSFam Zheng goto fail; 1038bdd6a90aSFam Zheng } 1039bdd6a90aSFam Zheng 1040bdd6a90aSFam Zheng for (j = 0; j < qiov->iov[i].iov_len / s->page_size; j++) { 10412916405aSLi Feng pagelist[entries++] = cpu_to_le64(iova + j * s->page_size); 1042bdd6a90aSFam Zheng } 1043bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov_iov(s, i, qiov->iov[i].iov_base, 1044bdd6a90aSFam Zheng qiov->iov[i].iov_len / s->page_size); 1045bdd6a90aSFam Zheng } 1046bdd6a90aSFam Zheng 1047bdd6a90aSFam Zheng s->dma_map_count += qiov->size; 1048bdd6a90aSFam Zheng 1049bdd6a90aSFam Zheng assert(entries <= s->page_size / sizeof(uint64_t)); 1050bdd6a90aSFam Zheng switch (entries) { 1051bdd6a90aSFam Zheng case 0: 1052bdd6a90aSFam Zheng abort(); 1053bdd6a90aSFam Zheng case 1: 1054c26f2173SKlaus Jensen cmd->dptr.prp1 = pagelist[0]; 1055c26f2173SKlaus Jensen cmd->dptr.prp2 = 0; 1056bdd6a90aSFam Zheng break; 1057bdd6a90aSFam Zheng case 2: 1058c26f2173SKlaus Jensen cmd->dptr.prp1 = pagelist[0]; 1059c26f2173SKlaus Jensen cmd->dptr.prp2 = pagelist[1]; 1060bdd6a90aSFam Zheng break; 1061bdd6a90aSFam Zheng default: 1062c26f2173SKlaus Jensen cmd->dptr.prp1 = pagelist[0]; 1063c26f2173SKlaus Jensen cmd->dptr.prp2 = cpu_to_le64(req->prp_list_iova + sizeof(uint64_t)); 1064bdd6a90aSFam Zheng break; 1065bdd6a90aSFam Zheng } 1066bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov(s, cmd, req, qiov, entries); 1067bdd6a90aSFam Zheng for (i = 0; i < entries; ++i) { 1068bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov_pages(s, i, pagelist[i]); 1069bdd6a90aSFam Zheng } 1070bdd6a90aSFam Zheng return 0; 1071bdd6a90aSFam Zheng fail: 1072bdd6a90aSFam Zheng /* No need to unmap [0 - i) iovs even if we've failed, since we don't 1073bdd6a90aSFam Zheng * increment s->dma_map_count. This is okay for fixed mapping memory areas 1074bdd6a90aSFam Zheng * because they are already mapped before calling this function; for 1075bdd6a90aSFam Zheng * temporary mappings, a later nvme_cmd_(un)map_qiov will reclaim by 1076bdd6a90aSFam Zheng * calling qemu_vfio_dma_reset_temporary when necessary. */ 1077bdd6a90aSFam Zheng return r; 1078bdd6a90aSFam Zheng } 1079bdd6a90aSFam Zheng 1080bdd6a90aSFam Zheng typedef struct { 1081bdd6a90aSFam Zheng Coroutine *co; 1082bdd6a90aSFam Zheng int ret; 1083bdd6a90aSFam Zheng AioContext *ctx; 1084bdd6a90aSFam Zheng } NVMeCoData; 1085bdd6a90aSFam Zheng 1086bdd6a90aSFam Zheng static void nvme_rw_cb_bh(void *opaque) 1087bdd6a90aSFam Zheng { 1088bdd6a90aSFam Zheng NVMeCoData *data = opaque; 1089bdd6a90aSFam Zheng qemu_coroutine_enter(data->co); 1090bdd6a90aSFam Zheng } 1091bdd6a90aSFam Zheng 1092bdd6a90aSFam Zheng static void nvme_rw_cb(void *opaque, int ret) 1093bdd6a90aSFam Zheng { 1094bdd6a90aSFam Zheng NVMeCoData *data = opaque; 1095bdd6a90aSFam Zheng data->ret = ret; 1096bdd6a90aSFam Zheng if (!data->co) { 1097bdd6a90aSFam Zheng /* The rw coroutine hasn't yielded, don't try to enter. */ 1098bdd6a90aSFam Zheng return; 1099bdd6a90aSFam Zheng } 1100e4ec5ad4SPavel Dovgalyuk replay_bh_schedule_oneshot_event(data->ctx, nvme_rw_cb_bh, data); 1101bdd6a90aSFam Zheng } 1102bdd6a90aSFam Zheng 1103bdd6a90aSFam Zheng static coroutine_fn int nvme_co_prw_aligned(BlockDriverState *bs, 1104bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 1105bdd6a90aSFam Zheng QEMUIOVector *qiov, 1106bdd6a90aSFam Zheng bool is_write, 1107bdd6a90aSFam Zheng int flags) 1108bdd6a90aSFam Zheng { 1109bdd6a90aSFam Zheng int r; 1110bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 111173159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1112bdd6a90aSFam Zheng NVMeRequest *req; 1113118d1b6aSMaxim Levitsky 1114118d1b6aSMaxim Levitsky uint32_t cdw12 = (((bytes >> s->blkshift) - 1) & 0xFFFF) | 1115bdd6a90aSFam Zheng (flags & BDRV_REQ_FUA ? 1 << 30 : 0); 1116bdd6a90aSFam Zheng NvmeCmd cmd = { 1117bdd6a90aSFam Zheng .opcode = is_write ? NVME_CMD_WRITE : NVME_CMD_READ, 1118bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 1119118d1b6aSMaxim Levitsky .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF), 1120118d1b6aSMaxim Levitsky .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF), 1121bdd6a90aSFam Zheng .cdw12 = cpu_to_le32(cdw12), 1122bdd6a90aSFam Zheng }; 1123bdd6a90aSFam Zheng NVMeCoData data = { 1124bdd6a90aSFam Zheng .ctx = bdrv_get_aio_context(bs), 1125bdd6a90aSFam Zheng .ret = -EINPROGRESS, 1126bdd6a90aSFam Zheng }; 1127bdd6a90aSFam Zheng 1128bdd6a90aSFam Zheng trace_nvme_prw_aligned(s, is_write, offset, bytes, flags, qiov->niov); 11291b539bd6SPhilippe Mathieu-Daudé assert(s->queue_count > 1); 1130bdd6a90aSFam Zheng req = nvme_get_free_req(ioq); 1131bdd6a90aSFam Zheng assert(req); 1132bdd6a90aSFam Zheng 1133bdd6a90aSFam Zheng qemu_co_mutex_lock(&s->dma_map_lock); 1134bdd6a90aSFam Zheng r = nvme_cmd_map_qiov(bs, &cmd, req, qiov); 1135bdd6a90aSFam Zheng qemu_co_mutex_unlock(&s->dma_map_lock); 1136bdd6a90aSFam Zheng if (r) { 1137b75fd5f5SStefan Hajnoczi nvme_put_free_req_and_wake(ioq, req); 1138bdd6a90aSFam Zheng return r; 1139bdd6a90aSFam Zheng } 1140b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1141bdd6a90aSFam Zheng 1142bdd6a90aSFam Zheng data.co = qemu_coroutine_self(); 1143bdd6a90aSFam Zheng while (data.ret == -EINPROGRESS) { 1144bdd6a90aSFam Zheng qemu_coroutine_yield(); 1145bdd6a90aSFam Zheng } 1146bdd6a90aSFam Zheng 1147bdd6a90aSFam Zheng qemu_co_mutex_lock(&s->dma_map_lock); 1148bdd6a90aSFam Zheng r = nvme_cmd_unmap_qiov(bs, qiov); 1149bdd6a90aSFam Zheng qemu_co_mutex_unlock(&s->dma_map_lock); 1150bdd6a90aSFam Zheng if (r) { 1151bdd6a90aSFam Zheng return r; 1152bdd6a90aSFam Zheng } 1153bdd6a90aSFam Zheng 1154bdd6a90aSFam Zheng trace_nvme_rw_done(s, is_write, offset, bytes, data.ret); 1155bdd6a90aSFam Zheng return data.ret; 1156bdd6a90aSFam Zheng } 1157bdd6a90aSFam Zheng 1158bdd6a90aSFam Zheng static inline bool nvme_qiov_aligned(BlockDriverState *bs, 1159bdd6a90aSFam Zheng const QEMUIOVector *qiov) 1160bdd6a90aSFam Zheng { 1161bdd6a90aSFam Zheng int i; 1162bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1163bdd6a90aSFam Zheng 1164bdd6a90aSFam Zheng for (i = 0; i < qiov->niov; ++i) { 1165bdd6a90aSFam Zheng if (!QEMU_PTR_IS_ALIGNED(qiov->iov[i].iov_base, s->page_size) || 1166bdd6a90aSFam Zheng !QEMU_IS_ALIGNED(qiov->iov[i].iov_len, s->page_size)) { 1167bdd6a90aSFam Zheng trace_nvme_qiov_unaligned(qiov, i, qiov->iov[i].iov_base, 1168bdd6a90aSFam Zheng qiov->iov[i].iov_len, s->page_size); 1169bdd6a90aSFam Zheng return false; 1170bdd6a90aSFam Zheng } 1171bdd6a90aSFam Zheng } 1172bdd6a90aSFam Zheng return true; 1173bdd6a90aSFam Zheng } 1174bdd6a90aSFam Zheng 1175bdd6a90aSFam Zheng static int nvme_co_prw(BlockDriverState *bs, uint64_t offset, uint64_t bytes, 1176bdd6a90aSFam Zheng QEMUIOVector *qiov, bool is_write, int flags) 1177bdd6a90aSFam Zheng { 1178bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1179bdd6a90aSFam Zheng int r; 1180bdd6a90aSFam Zheng uint8_t *buf = NULL; 1181bdd6a90aSFam Zheng QEMUIOVector local_qiov; 1182bdd6a90aSFam Zheng 1183bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(offset, s->page_size)); 1184bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(bytes, s->page_size)); 1185bdd6a90aSFam Zheng assert(bytes <= s->max_transfer); 1186bdd6a90aSFam Zheng if (nvme_qiov_aligned(bs, qiov)) { 1187f25e7ab2SPhilippe Mathieu-Daudé s->stats.aligned_accesses++; 1188bdd6a90aSFam Zheng return nvme_co_prw_aligned(bs, offset, bytes, qiov, is_write, flags); 1189bdd6a90aSFam Zheng } 1190f25e7ab2SPhilippe Mathieu-Daudé s->stats.unaligned_accesses++; 1191bdd6a90aSFam Zheng trace_nvme_prw_buffered(s, offset, bytes, qiov->niov, is_write); 119238e1f818SPhilippe Mathieu-Daudé buf = qemu_try_memalign(s->page_size, bytes); 1193bdd6a90aSFam Zheng 1194bdd6a90aSFam Zheng if (!buf) { 1195bdd6a90aSFam Zheng return -ENOMEM; 1196bdd6a90aSFam Zheng } 1197bdd6a90aSFam Zheng qemu_iovec_init(&local_qiov, 1); 1198bdd6a90aSFam Zheng if (is_write) { 1199bdd6a90aSFam Zheng qemu_iovec_to_buf(qiov, 0, buf, bytes); 1200bdd6a90aSFam Zheng } 1201bdd6a90aSFam Zheng qemu_iovec_add(&local_qiov, buf, bytes); 1202bdd6a90aSFam Zheng r = nvme_co_prw_aligned(bs, offset, bytes, &local_qiov, is_write, flags); 1203bdd6a90aSFam Zheng qemu_iovec_destroy(&local_qiov); 1204bdd6a90aSFam Zheng if (!r && !is_write) { 1205bdd6a90aSFam Zheng qemu_iovec_from_buf(qiov, 0, buf, bytes); 1206bdd6a90aSFam Zheng } 1207bdd6a90aSFam Zheng qemu_vfree(buf); 1208bdd6a90aSFam Zheng return r; 1209bdd6a90aSFam Zheng } 1210bdd6a90aSFam Zheng 1211bdd6a90aSFam Zheng static coroutine_fn int nvme_co_preadv(BlockDriverState *bs, 1212bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 1213bdd6a90aSFam Zheng QEMUIOVector *qiov, int flags) 1214bdd6a90aSFam Zheng { 1215bdd6a90aSFam Zheng return nvme_co_prw(bs, offset, bytes, qiov, false, flags); 1216bdd6a90aSFam Zheng } 1217bdd6a90aSFam Zheng 1218bdd6a90aSFam Zheng static coroutine_fn int nvme_co_pwritev(BlockDriverState *bs, 1219bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 1220bdd6a90aSFam Zheng QEMUIOVector *qiov, int flags) 1221bdd6a90aSFam Zheng { 1222bdd6a90aSFam Zheng return nvme_co_prw(bs, offset, bytes, qiov, true, flags); 1223bdd6a90aSFam Zheng } 1224bdd6a90aSFam Zheng 1225bdd6a90aSFam Zheng static coroutine_fn int nvme_co_flush(BlockDriverState *bs) 1226bdd6a90aSFam Zheng { 1227bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 122873159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1229bdd6a90aSFam Zheng NVMeRequest *req; 1230bdd6a90aSFam Zheng NvmeCmd cmd = { 1231bdd6a90aSFam Zheng .opcode = NVME_CMD_FLUSH, 1232bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 1233bdd6a90aSFam Zheng }; 1234bdd6a90aSFam Zheng NVMeCoData data = { 1235bdd6a90aSFam Zheng .ctx = bdrv_get_aio_context(bs), 1236bdd6a90aSFam Zheng .ret = -EINPROGRESS, 1237bdd6a90aSFam Zheng }; 1238bdd6a90aSFam Zheng 12391b539bd6SPhilippe Mathieu-Daudé assert(s->queue_count > 1); 1240bdd6a90aSFam Zheng req = nvme_get_free_req(ioq); 1241bdd6a90aSFam Zheng assert(req); 1242b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1243bdd6a90aSFam Zheng 1244bdd6a90aSFam Zheng data.co = qemu_coroutine_self(); 1245bdd6a90aSFam Zheng if (data.ret == -EINPROGRESS) { 1246bdd6a90aSFam Zheng qemu_coroutine_yield(); 1247bdd6a90aSFam Zheng } 1248bdd6a90aSFam Zheng 1249bdd6a90aSFam Zheng return data.ret; 1250bdd6a90aSFam Zheng } 1251bdd6a90aSFam Zheng 1252bdd6a90aSFam Zheng 1253e0dd95e3SMaxim Levitsky static coroutine_fn int nvme_co_pwrite_zeroes(BlockDriverState *bs, 1254e0dd95e3SMaxim Levitsky int64_t offset, 1255e0dd95e3SMaxim Levitsky int bytes, 1256e0dd95e3SMaxim Levitsky BdrvRequestFlags flags) 1257e0dd95e3SMaxim Levitsky { 1258e0dd95e3SMaxim Levitsky BDRVNVMeState *s = bs->opaque; 125973159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1260e0dd95e3SMaxim Levitsky NVMeRequest *req; 1261e0dd95e3SMaxim Levitsky 1262e0dd95e3SMaxim Levitsky uint32_t cdw12 = ((bytes >> s->blkshift) - 1) & 0xFFFF; 1263e0dd95e3SMaxim Levitsky 1264e0dd95e3SMaxim Levitsky if (!s->supports_write_zeroes) { 1265e0dd95e3SMaxim Levitsky return -ENOTSUP; 1266e0dd95e3SMaxim Levitsky } 1267e0dd95e3SMaxim Levitsky 1268e0dd95e3SMaxim Levitsky NvmeCmd cmd = { 126969265150SKlaus Jensen .opcode = NVME_CMD_WRITE_ZEROES, 1270e0dd95e3SMaxim Levitsky .nsid = cpu_to_le32(s->nsid), 1271e0dd95e3SMaxim Levitsky .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF), 1272e0dd95e3SMaxim Levitsky .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF), 1273e0dd95e3SMaxim Levitsky }; 1274e0dd95e3SMaxim Levitsky 1275e0dd95e3SMaxim Levitsky NVMeCoData data = { 1276e0dd95e3SMaxim Levitsky .ctx = bdrv_get_aio_context(bs), 1277e0dd95e3SMaxim Levitsky .ret = -EINPROGRESS, 1278e0dd95e3SMaxim Levitsky }; 1279e0dd95e3SMaxim Levitsky 1280e0dd95e3SMaxim Levitsky if (flags & BDRV_REQ_MAY_UNMAP) { 1281e0dd95e3SMaxim Levitsky cdw12 |= (1 << 25); 1282e0dd95e3SMaxim Levitsky } 1283e0dd95e3SMaxim Levitsky 1284e0dd95e3SMaxim Levitsky if (flags & BDRV_REQ_FUA) { 1285e0dd95e3SMaxim Levitsky cdw12 |= (1 << 30); 1286e0dd95e3SMaxim Levitsky } 1287e0dd95e3SMaxim Levitsky 1288e0dd95e3SMaxim Levitsky cmd.cdw12 = cpu_to_le32(cdw12); 1289e0dd95e3SMaxim Levitsky 1290e0dd95e3SMaxim Levitsky trace_nvme_write_zeroes(s, offset, bytes, flags); 12911b539bd6SPhilippe Mathieu-Daudé assert(s->queue_count > 1); 1292e0dd95e3SMaxim Levitsky req = nvme_get_free_req(ioq); 1293e0dd95e3SMaxim Levitsky assert(req); 1294e0dd95e3SMaxim Levitsky 1295b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1296e0dd95e3SMaxim Levitsky 1297e0dd95e3SMaxim Levitsky data.co = qemu_coroutine_self(); 1298e0dd95e3SMaxim Levitsky while (data.ret == -EINPROGRESS) { 1299e0dd95e3SMaxim Levitsky qemu_coroutine_yield(); 1300e0dd95e3SMaxim Levitsky } 1301e0dd95e3SMaxim Levitsky 1302e0dd95e3SMaxim Levitsky trace_nvme_rw_done(s, true, offset, bytes, data.ret); 1303e0dd95e3SMaxim Levitsky return data.ret; 1304e0dd95e3SMaxim Levitsky } 1305e0dd95e3SMaxim Levitsky 1306e0dd95e3SMaxim Levitsky 1307e87a09d6SMaxim Levitsky static int coroutine_fn nvme_co_pdiscard(BlockDriverState *bs, 1308e87a09d6SMaxim Levitsky int64_t offset, 1309e87a09d6SMaxim Levitsky int bytes) 1310e87a09d6SMaxim Levitsky { 1311e87a09d6SMaxim Levitsky BDRVNVMeState *s = bs->opaque; 131273159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1313e87a09d6SMaxim Levitsky NVMeRequest *req; 1314e87a09d6SMaxim Levitsky NvmeDsmRange *buf; 1315e87a09d6SMaxim Levitsky QEMUIOVector local_qiov; 1316e87a09d6SMaxim Levitsky int ret; 1317e87a09d6SMaxim Levitsky 1318e87a09d6SMaxim Levitsky NvmeCmd cmd = { 1319e87a09d6SMaxim Levitsky .opcode = NVME_CMD_DSM, 1320e87a09d6SMaxim Levitsky .nsid = cpu_to_le32(s->nsid), 1321e87a09d6SMaxim Levitsky .cdw10 = cpu_to_le32(0), /*number of ranges - 0 based*/ 1322e87a09d6SMaxim Levitsky .cdw11 = cpu_to_le32(1 << 2), /*deallocate bit*/ 1323e87a09d6SMaxim Levitsky }; 1324e87a09d6SMaxim Levitsky 1325e87a09d6SMaxim Levitsky NVMeCoData data = { 1326e87a09d6SMaxim Levitsky .ctx = bdrv_get_aio_context(bs), 1327e87a09d6SMaxim Levitsky .ret = -EINPROGRESS, 1328e87a09d6SMaxim Levitsky }; 1329e87a09d6SMaxim Levitsky 1330e87a09d6SMaxim Levitsky if (!s->supports_discard) { 1331e87a09d6SMaxim Levitsky return -ENOTSUP; 1332e87a09d6SMaxim Levitsky } 1333e87a09d6SMaxim Levitsky 13341b539bd6SPhilippe Mathieu-Daudé assert(s->queue_count > 1); 1335e87a09d6SMaxim Levitsky 133638e1f818SPhilippe Mathieu-Daudé buf = qemu_try_memalign(s->page_size, s->page_size); 1337e87a09d6SMaxim Levitsky if (!buf) { 1338e87a09d6SMaxim Levitsky return -ENOMEM; 1339e87a09d6SMaxim Levitsky } 13402ed84693SPhilippe Mathieu-Daudé memset(buf, 0, s->page_size); 1341e87a09d6SMaxim Levitsky buf->nlb = cpu_to_le32(bytes >> s->blkshift); 1342e87a09d6SMaxim Levitsky buf->slba = cpu_to_le64(offset >> s->blkshift); 1343e87a09d6SMaxim Levitsky buf->cattr = 0; 1344e87a09d6SMaxim Levitsky 1345e87a09d6SMaxim Levitsky qemu_iovec_init(&local_qiov, 1); 1346e87a09d6SMaxim Levitsky qemu_iovec_add(&local_qiov, buf, 4096); 1347e87a09d6SMaxim Levitsky 1348e87a09d6SMaxim Levitsky req = nvme_get_free_req(ioq); 1349e87a09d6SMaxim Levitsky assert(req); 1350e87a09d6SMaxim Levitsky 1351e87a09d6SMaxim Levitsky qemu_co_mutex_lock(&s->dma_map_lock); 1352e87a09d6SMaxim Levitsky ret = nvme_cmd_map_qiov(bs, &cmd, req, &local_qiov); 1353e87a09d6SMaxim Levitsky qemu_co_mutex_unlock(&s->dma_map_lock); 1354e87a09d6SMaxim Levitsky 1355e87a09d6SMaxim Levitsky if (ret) { 1356b75fd5f5SStefan Hajnoczi nvme_put_free_req_and_wake(ioq, req); 1357e87a09d6SMaxim Levitsky goto out; 1358e87a09d6SMaxim Levitsky } 1359e87a09d6SMaxim Levitsky 1360e87a09d6SMaxim Levitsky trace_nvme_dsm(s, offset, bytes); 1361e87a09d6SMaxim Levitsky 1362b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1363e87a09d6SMaxim Levitsky 1364e87a09d6SMaxim Levitsky data.co = qemu_coroutine_self(); 1365e87a09d6SMaxim Levitsky while (data.ret == -EINPROGRESS) { 1366e87a09d6SMaxim Levitsky qemu_coroutine_yield(); 1367e87a09d6SMaxim Levitsky } 1368e87a09d6SMaxim Levitsky 1369e87a09d6SMaxim Levitsky qemu_co_mutex_lock(&s->dma_map_lock); 1370e87a09d6SMaxim Levitsky ret = nvme_cmd_unmap_qiov(bs, &local_qiov); 1371e87a09d6SMaxim Levitsky qemu_co_mutex_unlock(&s->dma_map_lock); 1372e87a09d6SMaxim Levitsky 1373e87a09d6SMaxim Levitsky if (ret) { 1374e87a09d6SMaxim Levitsky goto out; 1375e87a09d6SMaxim Levitsky } 1376e87a09d6SMaxim Levitsky 1377e87a09d6SMaxim Levitsky ret = data.ret; 1378e87a09d6SMaxim Levitsky trace_nvme_dsm_done(s, offset, bytes, ret); 1379e87a09d6SMaxim Levitsky out: 1380e87a09d6SMaxim Levitsky qemu_iovec_destroy(&local_qiov); 1381e87a09d6SMaxim Levitsky qemu_vfree(buf); 1382e87a09d6SMaxim Levitsky return ret; 1383e87a09d6SMaxim Levitsky 1384e87a09d6SMaxim Levitsky } 1385e87a09d6SMaxim Levitsky 1386e87a09d6SMaxim Levitsky 1387bdd6a90aSFam Zheng static int nvme_reopen_prepare(BDRVReopenState *reopen_state, 1388bdd6a90aSFam Zheng BlockReopenQueue *queue, Error **errp) 1389bdd6a90aSFam Zheng { 1390bdd6a90aSFam Zheng return 0; 1391bdd6a90aSFam Zheng } 1392bdd6a90aSFam Zheng 1393998b3a1eSMax Reitz static void nvme_refresh_filename(BlockDriverState *bs) 1394bdd6a90aSFam Zheng { 1395cc61b074SMax Reitz BDRVNVMeState *s = bs->opaque; 1396bdd6a90aSFam Zheng 1397cc61b074SMax Reitz snprintf(bs->exact_filename, sizeof(bs->exact_filename), "nvme://%s/%i", 1398cc61b074SMax Reitz s->device, s->nsid); 1399bdd6a90aSFam Zheng } 1400bdd6a90aSFam Zheng 1401bdd6a90aSFam Zheng static void nvme_refresh_limits(BlockDriverState *bs, Error **errp) 1402bdd6a90aSFam Zheng { 1403bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1404bdd6a90aSFam Zheng 1405bdd6a90aSFam Zheng bs->bl.opt_mem_alignment = s->page_size; 1406bdd6a90aSFam Zheng bs->bl.request_alignment = s->page_size; 1407bdd6a90aSFam Zheng bs->bl.max_transfer = s->max_transfer; 1408bdd6a90aSFam Zheng } 1409bdd6a90aSFam Zheng 1410bdd6a90aSFam Zheng static void nvme_detach_aio_context(BlockDriverState *bs) 1411bdd6a90aSFam Zheng { 1412bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1413bdd6a90aSFam Zheng 14141b539bd6SPhilippe Mathieu-Daudé for (unsigned i = 0; i < s->queue_count; i++) { 14157838c67fSStefan Hajnoczi NVMeQueuePair *q = s->queues[i]; 14167838c67fSStefan Hajnoczi 14177838c67fSStefan Hajnoczi qemu_bh_delete(q->completion_bh); 14187838c67fSStefan Hajnoczi q->completion_bh = NULL; 14197838c67fSStefan Hajnoczi } 14207838c67fSStefan Hajnoczi 1421b111b3fcSPhilippe Mathieu-Daudé aio_set_event_notifier(bdrv_get_aio_context(bs), 1422b111b3fcSPhilippe Mathieu-Daudé &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 1423bdd6a90aSFam Zheng false, NULL, NULL); 1424bdd6a90aSFam Zheng } 1425bdd6a90aSFam Zheng 1426bdd6a90aSFam Zheng static void nvme_attach_aio_context(BlockDriverState *bs, 1427bdd6a90aSFam Zheng AioContext *new_context) 1428bdd6a90aSFam Zheng { 1429bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1430bdd6a90aSFam Zheng 1431bdd6a90aSFam Zheng s->aio_context = new_context; 1432b111b3fcSPhilippe Mathieu-Daudé aio_set_event_notifier(new_context, &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 1433bdd6a90aSFam Zheng false, nvme_handle_event, nvme_poll_cb); 14347838c67fSStefan Hajnoczi 14351b539bd6SPhilippe Mathieu-Daudé for (unsigned i = 0; i < s->queue_count; i++) { 14367838c67fSStefan Hajnoczi NVMeQueuePair *q = s->queues[i]; 14377838c67fSStefan Hajnoczi 14387838c67fSStefan Hajnoczi q->completion_bh = 14397838c67fSStefan Hajnoczi aio_bh_new(new_context, nvme_process_completion_bh, q); 14407838c67fSStefan Hajnoczi } 1441bdd6a90aSFam Zheng } 1442bdd6a90aSFam Zheng 1443bdd6a90aSFam Zheng static void nvme_aio_plug(BlockDriverState *bs) 1444bdd6a90aSFam Zheng { 1445bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 14462f0d8947SPaolo Bonzini assert(!s->plugged); 14472f0d8947SPaolo Bonzini s->plugged = true; 1448bdd6a90aSFam Zheng } 1449bdd6a90aSFam Zheng 1450bdd6a90aSFam Zheng static void nvme_aio_unplug(BlockDriverState *bs) 1451bdd6a90aSFam Zheng { 1452bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1453bdd6a90aSFam Zheng assert(s->plugged); 14542f0d8947SPaolo Bonzini s->plugged = false; 14551b539bd6SPhilippe Mathieu-Daudé for (unsigned i = INDEX_IO(0); i < s->queue_count; i++) { 1456bdd6a90aSFam Zheng NVMeQueuePair *q = s->queues[i]; 1457bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 1458b75fd5f5SStefan Hajnoczi nvme_kick(q); 1459b75fd5f5SStefan Hajnoczi nvme_process_completion(q); 1460bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 1461bdd6a90aSFam Zheng } 1462bdd6a90aSFam Zheng } 1463bdd6a90aSFam Zheng 14649ed61612SFam Zheng static void nvme_register_buf(BlockDriverState *bs, void *host, size_t size) 14659ed61612SFam Zheng { 14669ed61612SFam Zheng int ret; 14679ed61612SFam Zheng BDRVNVMeState *s = bs->opaque; 14689ed61612SFam Zheng 14699ed61612SFam Zheng ret = qemu_vfio_dma_map(s->vfio, host, size, false, NULL); 14709ed61612SFam Zheng if (ret) { 14719ed61612SFam Zheng /* FIXME: we may run out of IOVA addresses after repeated 14729ed61612SFam Zheng * bdrv_register_buf/bdrv_unregister_buf, because nvme_vfio_dma_unmap 14739ed61612SFam Zheng * doesn't reclaim addresses for fixed mappings. */ 14749ed61612SFam Zheng error_report("nvme_register_buf failed: %s", strerror(-ret)); 14759ed61612SFam Zheng } 14769ed61612SFam Zheng } 14779ed61612SFam Zheng 14789ed61612SFam Zheng static void nvme_unregister_buf(BlockDriverState *bs, void *host) 14799ed61612SFam Zheng { 14809ed61612SFam Zheng BDRVNVMeState *s = bs->opaque; 14819ed61612SFam Zheng 14829ed61612SFam Zheng qemu_vfio_dma_unmap(s->vfio, host); 14839ed61612SFam Zheng } 14849ed61612SFam Zheng 1485f25e7ab2SPhilippe Mathieu-Daudé static BlockStatsSpecific *nvme_get_specific_stats(BlockDriverState *bs) 1486f25e7ab2SPhilippe Mathieu-Daudé { 1487f25e7ab2SPhilippe Mathieu-Daudé BlockStatsSpecific *stats = g_new(BlockStatsSpecific, 1); 1488f25e7ab2SPhilippe Mathieu-Daudé BDRVNVMeState *s = bs->opaque; 1489f25e7ab2SPhilippe Mathieu-Daudé 1490f25e7ab2SPhilippe Mathieu-Daudé stats->driver = BLOCKDEV_DRIVER_NVME; 1491f25e7ab2SPhilippe Mathieu-Daudé stats->u.nvme = (BlockStatsSpecificNvme) { 1492f25e7ab2SPhilippe Mathieu-Daudé .completion_errors = s->stats.completion_errors, 1493f25e7ab2SPhilippe Mathieu-Daudé .aligned_accesses = s->stats.aligned_accesses, 1494f25e7ab2SPhilippe Mathieu-Daudé .unaligned_accesses = s->stats.unaligned_accesses, 1495f25e7ab2SPhilippe Mathieu-Daudé }; 1496f25e7ab2SPhilippe Mathieu-Daudé 1497f25e7ab2SPhilippe Mathieu-Daudé return stats; 1498f25e7ab2SPhilippe Mathieu-Daudé } 1499f25e7ab2SPhilippe Mathieu-Daudé 15002654267cSMax Reitz static const char *const nvme_strong_runtime_opts[] = { 15012654267cSMax Reitz NVME_BLOCK_OPT_DEVICE, 15022654267cSMax Reitz NVME_BLOCK_OPT_NAMESPACE, 15032654267cSMax Reitz 15042654267cSMax Reitz NULL 15052654267cSMax Reitz }; 15062654267cSMax Reitz 1507bdd6a90aSFam Zheng static BlockDriver bdrv_nvme = { 1508bdd6a90aSFam Zheng .format_name = "nvme", 1509bdd6a90aSFam Zheng .protocol_name = "nvme", 1510bdd6a90aSFam Zheng .instance_size = sizeof(BDRVNVMeState), 1511bdd6a90aSFam Zheng 15125a5e7f8cSMaxim Levitsky .bdrv_co_create_opts = bdrv_co_create_opts_simple, 15135a5e7f8cSMaxim Levitsky .create_opts = &bdrv_create_opts_simple, 15145a5e7f8cSMaxim Levitsky 1515bdd6a90aSFam Zheng .bdrv_parse_filename = nvme_parse_filename, 1516bdd6a90aSFam Zheng .bdrv_file_open = nvme_file_open, 1517bdd6a90aSFam Zheng .bdrv_close = nvme_close, 1518bdd6a90aSFam Zheng .bdrv_getlength = nvme_getlength, 1519118d1b6aSMaxim Levitsky .bdrv_probe_blocksizes = nvme_probe_blocksizes, 1520bdd6a90aSFam Zheng 1521bdd6a90aSFam Zheng .bdrv_co_preadv = nvme_co_preadv, 1522bdd6a90aSFam Zheng .bdrv_co_pwritev = nvme_co_pwritev, 1523e0dd95e3SMaxim Levitsky 1524e0dd95e3SMaxim Levitsky .bdrv_co_pwrite_zeroes = nvme_co_pwrite_zeroes, 1525e87a09d6SMaxim Levitsky .bdrv_co_pdiscard = nvme_co_pdiscard, 1526e0dd95e3SMaxim Levitsky 1527bdd6a90aSFam Zheng .bdrv_co_flush_to_disk = nvme_co_flush, 1528bdd6a90aSFam Zheng .bdrv_reopen_prepare = nvme_reopen_prepare, 1529bdd6a90aSFam Zheng 1530bdd6a90aSFam Zheng .bdrv_refresh_filename = nvme_refresh_filename, 1531bdd6a90aSFam Zheng .bdrv_refresh_limits = nvme_refresh_limits, 15322654267cSMax Reitz .strong_runtime_opts = nvme_strong_runtime_opts, 1533f25e7ab2SPhilippe Mathieu-Daudé .bdrv_get_specific_stats = nvme_get_specific_stats, 1534bdd6a90aSFam Zheng 1535bdd6a90aSFam Zheng .bdrv_detach_aio_context = nvme_detach_aio_context, 1536bdd6a90aSFam Zheng .bdrv_attach_aio_context = nvme_attach_aio_context, 1537bdd6a90aSFam Zheng 1538bdd6a90aSFam Zheng .bdrv_io_plug = nvme_aio_plug, 1539bdd6a90aSFam Zheng .bdrv_io_unplug = nvme_aio_unplug, 15409ed61612SFam Zheng 15419ed61612SFam Zheng .bdrv_register_buf = nvme_register_buf, 15429ed61612SFam Zheng .bdrv_unregister_buf = nvme_unregister_buf, 1543bdd6a90aSFam Zheng }; 1544bdd6a90aSFam Zheng 1545bdd6a90aSFam Zheng static void bdrv_nvme_init(void) 1546bdd6a90aSFam Zheng { 1547bdd6a90aSFam Zheng bdrv_register(&bdrv_nvme); 1548bdd6a90aSFam Zheng } 1549bdd6a90aSFam Zheng 1550bdd6a90aSFam Zheng block_init(bdrv_nvme_init); 1551