1bdd6a90aSFam Zheng /* 2bdd6a90aSFam Zheng * NVMe block driver based on vfio 3bdd6a90aSFam Zheng * 4bdd6a90aSFam Zheng * Copyright 2016 - 2018 Red Hat, Inc. 5bdd6a90aSFam Zheng * 6bdd6a90aSFam Zheng * Authors: 7bdd6a90aSFam Zheng * Fam Zheng <famz@redhat.com> 8bdd6a90aSFam Zheng * Paolo Bonzini <pbonzini@redhat.com> 9bdd6a90aSFam Zheng * 10bdd6a90aSFam Zheng * This work is licensed under the terms of the GNU GPL, version 2 or later. 11bdd6a90aSFam Zheng * See the COPYING file in the top-level directory. 12bdd6a90aSFam Zheng */ 13bdd6a90aSFam Zheng 14bdd6a90aSFam Zheng #include "qemu/osdep.h" 15bdd6a90aSFam Zheng #include <linux/vfio.h> 16bdd6a90aSFam Zheng #include "qapi/error.h" 17bdd6a90aSFam Zheng #include "qapi/qmp/qdict.h" 18bdd6a90aSFam Zheng #include "qapi/qmp/qstring.h" 19bdd6a90aSFam Zheng #include "qemu/error-report.h" 20db725815SMarkus Armbruster #include "qemu/main-loop.h" 210b8fa32fSMarkus Armbruster #include "qemu/module.h" 22bdd6a90aSFam Zheng #include "qemu/cutils.h" 23922a01a0SMarkus Armbruster #include "qemu/option.h" 24bdd6a90aSFam Zheng #include "qemu/vfio-helpers.h" 25bdd6a90aSFam Zheng #include "block/block_int.h" 26e4ec5ad4SPavel Dovgalyuk #include "sysemu/replay.h" 27bdd6a90aSFam Zheng #include "trace.h" 28bdd6a90aSFam Zheng 29a3d9a352SFam Zheng #include "block/nvme.h" 30bdd6a90aSFam Zheng 31bdd6a90aSFam Zheng #define NVME_SQ_ENTRY_BYTES 64 32bdd6a90aSFam Zheng #define NVME_CQ_ENTRY_BYTES 16 33bdd6a90aSFam Zheng #define NVME_QUEUE_SIZE 128 34f6845323SPhilippe Mathieu-Daudé #define NVME_DOORBELL_SIZE 4096 35bdd6a90aSFam Zheng 361086e95dSStefan Hajnoczi /* 371086e95dSStefan Hajnoczi * We have to leave one slot empty as that is the full queue case where 381086e95dSStefan Hajnoczi * head == tail + 1. 391086e95dSStefan Hajnoczi */ 401086e95dSStefan Hajnoczi #define NVME_NUM_REQS (NVME_QUEUE_SIZE - 1) 411086e95dSStefan Hajnoczi 42b75fd5f5SStefan Hajnoczi typedef struct BDRVNVMeState BDRVNVMeState; 43b75fd5f5SStefan Hajnoczi 443214b0f0SPhilippe Mathieu-Daudé /* Same index is used for queues and IRQs */ 453214b0f0SPhilippe Mathieu-Daudé #define INDEX_ADMIN 0 463214b0f0SPhilippe Mathieu-Daudé #define INDEX_IO(n) (1 + n) 473214b0f0SPhilippe Mathieu-Daudé 483214b0f0SPhilippe Mathieu-Daudé /* This driver shares a single MSIX IRQ for the admin and I/O queues */ 493214b0f0SPhilippe Mathieu-Daudé enum { 503214b0f0SPhilippe Mathieu-Daudé MSIX_SHARED_IRQ_IDX = 0, 513214b0f0SPhilippe Mathieu-Daudé MSIX_IRQ_COUNT = 1 523214b0f0SPhilippe Mathieu-Daudé }; 533214b0f0SPhilippe Mathieu-Daudé 54bdd6a90aSFam Zheng typedef struct { 55bdd6a90aSFam Zheng int32_t head, tail; 56bdd6a90aSFam Zheng uint8_t *queue; 57bdd6a90aSFam Zheng uint64_t iova; 58bdd6a90aSFam Zheng /* Hardware MMIO register */ 59bdd6a90aSFam Zheng volatile uint32_t *doorbell; 60bdd6a90aSFam Zheng } NVMeQueue; 61bdd6a90aSFam Zheng 62bdd6a90aSFam Zheng typedef struct { 63bdd6a90aSFam Zheng BlockCompletionFunc *cb; 64bdd6a90aSFam Zheng void *opaque; 65bdd6a90aSFam Zheng int cid; 66bdd6a90aSFam Zheng void *prp_list_page; 67bdd6a90aSFam Zheng uint64_t prp_list_iova; 681086e95dSStefan Hajnoczi int free_req_next; /* q->reqs[] index of next free req */ 69bdd6a90aSFam Zheng } NVMeRequest; 70bdd6a90aSFam Zheng 71bdd6a90aSFam Zheng typedef struct { 72bdd6a90aSFam Zheng QemuMutex lock; 73bdd6a90aSFam Zheng 74b75fd5f5SStefan Hajnoczi /* Read from I/O code path, initialized under BQL */ 75b75fd5f5SStefan Hajnoczi BDRVNVMeState *s; 76bdd6a90aSFam Zheng int index; 77b75fd5f5SStefan Hajnoczi 78b75fd5f5SStefan Hajnoczi /* Fields protected by BQL */ 79bdd6a90aSFam Zheng uint8_t *prp_list_pages; 80bdd6a90aSFam Zheng 81bdd6a90aSFam Zheng /* Fields protected by @lock */ 82a5db74f3SStefan Hajnoczi CoQueue free_req_queue; 83bdd6a90aSFam Zheng NVMeQueue sq, cq; 84bdd6a90aSFam Zheng int cq_phase; 851086e95dSStefan Hajnoczi int free_req_head; 861086e95dSStefan Hajnoczi NVMeRequest reqs[NVME_NUM_REQS]; 87bdd6a90aSFam Zheng int need_kick; 88bdd6a90aSFam Zheng int inflight; 897838c67fSStefan Hajnoczi 907838c67fSStefan Hajnoczi /* Thread-safe, no lock necessary */ 917838c67fSStefan Hajnoczi QEMUBH *completion_bh; 92bdd6a90aSFam Zheng } NVMeQueuePair; 93bdd6a90aSFam Zheng 94b75fd5f5SStefan Hajnoczi struct BDRVNVMeState { 95bdd6a90aSFam Zheng AioContext *aio_context; 96bdd6a90aSFam Zheng QEMUVFIOState *vfio; 974b19e9b8SPhilippe Mathieu-Daudé void *bar0_wo_map; 98f6845323SPhilippe Mathieu-Daudé /* Memory mapped registers */ 99f6845323SPhilippe Mathieu-Daudé volatile struct { 100f6845323SPhilippe Mathieu-Daudé uint32_t sq_tail; 101f6845323SPhilippe Mathieu-Daudé uint32_t cq_head; 102f6845323SPhilippe Mathieu-Daudé } *doorbells; 103bdd6a90aSFam Zheng /* The submission/completion queue pairs. 104bdd6a90aSFam Zheng * [0]: admin queue. 105bdd6a90aSFam Zheng * [1..]: io queues. 106bdd6a90aSFam Zheng */ 107bdd6a90aSFam Zheng NVMeQueuePair **queues; 1081b539bd6SPhilippe Mathieu-Daudé unsigned queue_count; 109bdd6a90aSFam Zheng size_t page_size; 110bdd6a90aSFam Zheng /* How many uint32_t elements does each doorbell entry take. */ 111bdd6a90aSFam Zheng size_t doorbell_scale; 112bdd6a90aSFam Zheng bool write_cache_supported; 113b111b3fcSPhilippe Mathieu-Daudé EventNotifier irq_notifier[MSIX_IRQ_COUNT]; 114118d1b6aSMaxim Levitsky 115bdd6a90aSFam Zheng uint64_t nsze; /* Namespace size reported by identify command */ 116bdd6a90aSFam Zheng int nsid; /* The namespace id to read/write data. */ 1171120407bSMax Reitz int blkshift; 118118d1b6aSMaxim Levitsky 119bdd6a90aSFam Zheng uint64_t max_transfer; 1202f0d8947SPaolo Bonzini bool plugged; 121bdd6a90aSFam Zheng 122e0dd95e3SMaxim Levitsky bool supports_write_zeroes; 123e87a09d6SMaxim Levitsky bool supports_discard; 124e0dd95e3SMaxim Levitsky 125bdd6a90aSFam Zheng CoMutex dma_map_lock; 126bdd6a90aSFam Zheng CoQueue dma_flush_queue; 127bdd6a90aSFam Zheng 128bdd6a90aSFam Zheng /* Total size of mapped qiov, accessed under dma_map_lock */ 129bdd6a90aSFam Zheng int dma_map_count; 130cc61b074SMax Reitz 131cc61b074SMax Reitz /* PCI address (required for nvme_refresh_filename()) */ 132cc61b074SMax Reitz char *device; 133f25e7ab2SPhilippe Mathieu-Daudé 134f25e7ab2SPhilippe Mathieu-Daudé struct { 135f25e7ab2SPhilippe Mathieu-Daudé uint64_t completion_errors; 136f25e7ab2SPhilippe Mathieu-Daudé uint64_t aligned_accesses; 137f25e7ab2SPhilippe Mathieu-Daudé uint64_t unaligned_accesses; 138f25e7ab2SPhilippe Mathieu-Daudé } stats; 139b75fd5f5SStefan Hajnoczi }; 140bdd6a90aSFam Zheng 141bdd6a90aSFam Zheng #define NVME_BLOCK_OPT_DEVICE "device" 142bdd6a90aSFam Zheng #define NVME_BLOCK_OPT_NAMESPACE "namespace" 143bdd6a90aSFam Zheng 1447838c67fSStefan Hajnoczi static void nvme_process_completion_bh(void *opaque); 1457838c67fSStefan Hajnoczi 146bdd6a90aSFam Zheng static QemuOptsList runtime_opts = { 147bdd6a90aSFam Zheng .name = "nvme", 148bdd6a90aSFam Zheng .head = QTAILQ_HEAD_INITIALIZER(runtime_opts.head), 149bdd6a90aSFam Zheng .desc = { 150bdd6a90aSFam Zheng { 151bdd6a90aSFam Zheng .name = NVME_BLOCK_OPT_DEVICE, 152bdd6a90aSFam Zheng .type = QEMU_OPT_STRING, 153bdd6a90aSFam Zheng .help = "NVMe PCI device address", 154bdd6a90aSFam Zheng }, 155bdd6a90aSFam Zheng { 156bdd6a90aSFam Zheng .name = NVME_BLOCK_OPT_NAMESPACE, 157bdd6a90aSFam Zheng .type = QEMU_OPT_NUMBER, 158bdd6a90aSFam Zheng .help = "NVMe namespace", 159bdd6a90aSFam Zheng }, 160bdd6a90aSFam Zheng { /* end of list */ } 161bdd6a90aSFam Zheng }, 162bdd6a90aSFam Zheng }; 163bdd6a90aSFam Zheng 164dfa9c6c6SPhilippe Mathieu-Daudé /* Returns true on success, false on failure. */ 165dfa9c6c6SPhilippe Mathieu-Daudé static bool nvme_init_queue(BDRVNVMeState *s, NVMeQueue *q, 1661b539bd6SPhilippe Mathieu-Daudé unsigned nentries, size_t entry_bytes, Error **errp) 167bdd6a90aSFam Zheng { 168bdd6a90aSFam Zheng size_t bytes; 169bdd6a90aSFam Zheng int r; 170bdd6a90aSFam Zheng 1712387aaceSEric Auger bytes = ROUND_UP(nentries * entry_bytes, qemu_real_host_page_size); 172bdd6a90aSFam Zheng q->head = q->tail = 0; 1732387aaceSEric Auger q->queue = qemu_try_memalign(qemu_real_host_page_size, bytes); 174bdd6a90aSFam Zheng if (!q->queue) { 175bdd6a90aSFam Zheng error_setg(errp, "Cannot allocate queue"); 176dfa9c6c6SPhilippe Mathieu-Daudé return false; 177bdd6a90aSFam Zheng } 1782ed84693SPhilippe Mathieu-Daudé memset(q->queue, 0, bytes); 179bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, q->queue, bytes, false, &q->iova); 180bdd6a90aSFam Zheng if (r) { 181bdd6a90aSFam Zheng error_setg(errp, "Cannot map queue"); 182dfa9c6c6SPhilippe Mathieu-Daudé return false; 183bdd6a90aSFam Zheng } 184dfa9c6c6SPhilippe Mathieu-Daudé return true; 185bdd6a90aSFam Zheng } 186bdd6a90aSFam Zheng 187b75fd5f5SStefan Hajnoczi static void nvme_free_queue_pair(NVMeQueuePair *q) 188bdd6a90aSFam Zheng { 1896e1e9ff2SPhilippe Mathieu-Daudé trace_nvme_free_queue_pair(q->index, q); 1907838c67fSStefan Hajnoczi if (q->completion_bh) { 1917838c67fSStefan Hajnoczi qemu_bh_delete(q->completion_bh); 1927838c67fSStefan Hajnoczi } 193bdd6a90aSFam Zheng qemu_vfree(q->prp_list_pages); 194bdd6a90aSFam Zheng qemu_vfree(q->sq.queue); 195bdd6a90aSFam Zheng qemu_vfree(q->cq.queue); 196bdd6a90aSFam Zheng qemu_mutex_destroy(&q->lock); 197bdd6a90aSFam Zheng g_free(q); 198bdd6a90aSFam Zheng } 199bdd6a90aSFam Zheng 200bdd6a90aSFam Zheng static void nvme_free_req_queue_cb(void *opaque) 201bdd6a90aSFam Zheng { 202bdd6a90aSFam Zheng NVMeQueuePair *q = opaque; 203bdd6a90aSFam Zheng 204bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 205bdd6a90aSFam Zheng while (qemu_co_enter_next(&q->free_req_queue, &q->lock)) { 206bdd6a90aSFam Zheng /* Retry all pending requests */ 207bdd6a90aSFam Zheng } 208bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 209bdd6a90aSFam Zheng } 210bdd6a90aSFam Zheng 2110a28b02eSPhilippe Mathieu-Daudé static NVMeQueuePair *nvme_create_queue_pair(BDRVNVMeState *s, 2120a28b02eSPhilippe Mathieu-Daudé AioContext *aio_context, 2131b539bd6SPhilippe Mathieu-Daudé unsigned idx, size_t size, 214bdd6a90aSFam Zheng Error **errp) 215bdd6a90aSFam Zheng { 216bdd6a90aSFam Zheng int i, r; 2170ea45f76SPhilippe Mathieu-Daudé NVMeQueuePair *q; 218bdd6a90aSFam Zheng uint64_t prp_list_iova; 219f8fd3ebaSEric Auger size_t bytes; 220bdd6a90aSFam Zheng 2210ea45f76SPhilippe Mathieu-Daudé q = g_try_new0(NVMeQueuePair, 1); 2220ea45f76SPhilippe Mathieu-Daudé if (!q) { 223*526c37c1SPhilippe Mathieu-Daudé error_setg(errp, "Cannot allocate queue pair"); 2240ea45f76SPhilippe Mathieu-Daudé return NULL; 2250ea45f76SPhilippe Mathieu-Daudé } 2266e1e9ff2SPhilippe Mathieu-Daudé trace_nvme_create_queue_pair(idx, q, size, aio_context, 2276e1e9ff2SPhilippe Mathieu-Daudé event_notifier_get_fd(s->irq_notifier)); 228f8fd3ebaSEric Auger bytes = QEMU_ALIGN_UP(s->page_size * NVME_NUM_REQS, 229f8fd3ebaSEric Auger qemu_real_host_page_size); 230f8fd3ebaSEric Auger q->prp_list_pages = qemu_try_memalign(qemu_real_host_page_size, bytes); 2310ea45f76SPhilippe Mathieu-Daudé if (!q->prp_list_pages) { 232*526c37c1SPhilippe Mathieu-Daudé error_setg(errp, "Cannot allocate PRP page list"); 2330ea45f76SPhilippe Mathieu-Daudé goto fail; 2340ea45f76SPhilippe Mathieu-Daudé } 235f8fd3ebaSEric Auger memset(q->prp_list_pages, 0, bytes); 236bdd6a90aSFam Zheng qemu_mutex_init(&q->lock); 237b75fd5f5SStefan Hajnoczi q->s = s; 238bdd6a90aSFam Zheng q->index = idx; 239bdd6a90aSFam Zheng qemu_co_queue_init(&q->free_req_queue); 2400a28b02eSPhilippe Mathieu-Daudé q->completion_bh = aio_bh_new(aio_context, nvme_process_completion_bh, q); 241f8fd3ebaSEric Auger r = qemu_vfio_dma_map(s->vfio, q->prp_list_pages, bytes, 242bdd6a90aSFam Zheng false, &prp_list_iova); 243bdd6a90aSFam Zheng if (r) { 244*526c37c1SPhilippe Mathieu-Daudé error_setg_errno(errp, -r, "Cannot map buffer for DMA"); 245bdd6a90aSFam Zheng goto fail; 246bdd6a90aSFam Zheng } 2471086e95dSStefan Hajnoczi q->free_req_head = -1; 2481086e95dSStefan Hajnoczi for (i = 0; i < NVME_NUM_REQS; i++) { 249bdd6a90aSFam Zheng NVMeRequest *req = &q->reqs[i]; 250bdd6a90aSFam Zheng req->cid = i + 1; 2511086e95dSStefan Hajnoczi req->free_req_next = q->free_req_head; 2521086e95dSStefan Hajnoczi q->free_req_head = i; 253bdd6a90aSFam Zheng req->prp_list_page = q->prp_list_pages + i * s->page_size; 254bdd6a90aSFam Zheng req->prp_list_iova = prp_list_iova + i * s->page_size; 255bdd6a90aSFam Zheng } 2561086e95dSStefan Hajnoczi 257dfa9c6c6SPhilippe Mathieu-Daudé if (!nvme_init_queue(s, &q->sq, size, NVME_SQ_ENTRY_BYTES, errp)) { 258bdd6a90aSFam Zheng goto fail; 259bdd6a90aSFam Zheng } 260f6845323SPhilippe Mathieu-Daudé q->sq.doorbell = &s->doorbells[idx * s->doorbell_scale].sq_tail; 261bdd6a90aSFam Zheng 262dfa9c6c6SPhilippe Mathieu-Daudé if (!nvme_init_queue(s, &q->cq, size, NVME_CQ_ENTRY_BYTES, errp)) { 263bdd6a90aSFam Zheng goto fail; 264bdd6a90aSFam Zheng } 265f6845323SPhilippe Mathieu-Daudé q->cq.doorbell = &s->doorbells[idx * s->doorbell_scale].cq_head; 266bdd6a90aSFam Zheng 267bdd6a90aSFam Zheng return q; 268bdd6a90aSFam Zheng fail: 269b75fd5f5SStefan Hajnoczi nvme_free_queue_pair(q); 270bdd6a90aSFam Zheng return NULL; 271bdd6a90aSFam Zheng } 272bdd6a90aSFam Zheng 273bdd6a90aSFam Zheng /* With q->lock */ 274b75fd5f5SStefan Hajnoczi static void nvme_kick(NVMeQueuePair *q) 275bdd6a90aSFam Zheng { 276b75fd5f5SStefan Hajnoczi BDRVNVMeState *s = q->s; 277b75fd5f5SStefan Hajnoczi 278bdd6a90aSFam Zheng if (s->plugged || !q->need_kick) { 279bdd6a90aSFam Zheng return; 280bdd6a90aSFam Zheng } 281bdd6a90aSFam Zheng trace_nvme_kick(s, q->index); 282bdd6a90aSFam Zheng assert(!(q->sq.tail & 0xFF00)); 283bdd6a90aSFam Zheng /* Fence the write to submission queue entry before notifying the device. */ 284bdd6a90aSFam Zheng smp_wmb(); 285bdd6a90aSFam Zheng *q->sq.doorbell = cpu_to_le32(q->sq.tail); 286bdd6a90aSFam Zheng q->inflight += q->need_kick; 287bdd6a90aSFam Zheng q->need_kick = 0; 288bdd6a90aSFam Zheng } 289bdd6a90aSFam Zheng 290bdd6a90aSFam Zheng /* Find a free request element if any, otherwise: 291bdd6a90aSFam Zheng * a) if in coroutine context, try to wait for one to become available; 292bdd6a90aSFam Zheng * b) if not in coroutine, return NULL; 293bdd6a90aSFam Zheng */ 294bdd6a90aSFam Zheng static NVMeRequest *nvme_get_free_req(NVMeQueuePair *q) 295bdd6a90aSFam Zheng { 2961086e95dSStefan Hajnoczi NVMeRequest *req; 297bdd6a90aSFam Zheng 298bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 2991086e95dSStefan Hajnoczi 3001086e95dSStefan Hajnoczi while (q->free_req_head == -1) { 301bdd6a90aSFam Zheng if (qemu_in_coroutine()) { 30251e98b6dSPhilippe Mathieu-Daudé trace_nvme_free_req_queue_wait(q->s, q->index); 303bdd6a90aSFam Zheng qemu_co_queue_wait(&q->free_req_queue, &q->lock); 304bdd6a90aSFam Zheng } else { 305bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 306bdd6a90aSFam Zheng return NULL; 307bdd6a90aSFam Zheng } 308bdd6a90aSFam Zheng } 3091086e95dSStefan Hajnoczi 3101086e95dSStefan Hajnoczi req = &q->reqs[q->free_req_head]; 3111086e95dSStefan Hajnoczi q->free_req_head = req->free_req_next; 3121086e95dSStefan Hajnoczi req->free_req_next = -1; 3131086e95dSStefan Hajnoczi 314bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 315bdd6a90aSFam Zheng return req; 316bdd6a90aSFam Zheng } 317bdd6a90aSFam Zheng 3181086e95dSStefan Hajnoczi /* With q->lock */ 3191086e95dSStefan Hajnoczi static void nvme_put_free_req_locked(NVMeQueuePair *q, NVMeRequest *req) 3201086e95dSStefan Hajnoczi { 3211086e95dSStefan Hajnoczi req->free_req_next = q->free_req_head; 3221086e95dSStefan Hajnoczi q->free_req_head = req - q->reqs; 3231086e95dSStefan Hajnoczi } 3241086e95dSStefan Hajnoczi 3251086e95dSStefan Hajnoczi /* With q->lock */ 326b75fd5f5SStefan Hajnoczi static void nvme_wake_free_req_locked(NVMeQueuePair *q) 3271086e95dSStefan Hajnoczi { 3281086e95dSStefan Hajnoczi if (!qemu_co_queue_empty(&q->free_req_queue)) { 329b75fd5f5SStefan Hajnoczi replay_bh_schedule_oneshot_event(q->s->aio_context, 3301086e95dSStefan Hajnoczi nvme_free_req_queue_cb, q); 3311086e95dSStefan Hajnoczi } 3321086e95dSStefan Hajnoczi } 3331086e95dSStefan Hajnoczi 3341086e95dSStefan Hajnoczi /* Insert a request in the freelist and wake waiters */ 335b75fd5f5SStefan Hajnoczi static void nvme_put_free_req_and_wake(NVMeQueuePair *q, NVMeRequest *req) 3361086e95dSStefan Hajnoczi { 3371086e95dSStefan Hajnoczi qemu_mutex_lock(&q->lock); 3381086e95dSStefan Hajnoczi nvme_put_free_req_locked(q, req); 339b75fd5f5SStefan Hajnoczi nvme_wake_free_req_locked(q); 3401086e95dSStefan Hajnoczi qemu_mutex_unlock(&q->lock); 3411086e95dSStefan Hajnoczi } 3421086e95dSStefan Hajnoczi 343bdd6a90aSFam Zheng static inline int nvme_translate_error(const NvmeCqe *c) 344bdd6a90aSFam Zheng { 345bdd6a90aSFam Zheng uint16_t status = (le16_to_cpu(c->status) >> 1) & 0xFF; 346bdd6a90aSFam Zheng if (status) { 347bdd6a90aSFam Zheng trace_nvme_error(le32_to_cpu(c->result), 348bdd6a90aSFam Zheng le16_to_cpu(c->sq_head), 349bdd6a90aSFam Zheng le16_to_cpu(c->sq_id), 350bdd6a90aSFam Zheng le16_to_cpu(c->cid), 351bdd6a90aSFam Zheng le16_to_cpu(status)); 352bdd6a90aSFam Zheng } 353bdd6a90aSFam Zheng switch (status) { 354bdd6a90aSFam Zheng case 0: 355bdd6a90aSFam Zheng return 0; 356bdd6a90aSFam Zheng case 1: 357bdd6a90aSFam Zheng return -ENOSYS; 358bdd6a90aSFam Zheng case 2: 359bdd6a90aSFam Zheng return -EINVAL; 360bdd6a90aSFam Zheng default: 361bdd6a90aSFam Zheng return -EIO; 362bdd6a90aSFam Zheng } 363bdd6a90aSFam Zheng } 364bdd6a90aSFam Zheng 365bdd6a90aSFam Zheng /* With q->lock */ 366b75fd5f5SStefan Hajnoczi static bool nvme_process_completion(NVMeQueuePair *q) 367bdd6a90aSFam Zheng { 368b75fd5f5SStefan Hajnoczi BDRVNVMeState *s = q->s; 369bdd6a90aSFam Zheng bool progress = false; 370bdd6a90aSFam Zheng NVMeRequest *preq; 371bdd6a90aSFam Zheng NVMeRequest req; 372bdd6a90aSFam Zheng NvmeCqe *c; 373bdd6a90aSFam Zheng 374bdd6a90aSFam Zheng trace_nvme_process_completion(s, q->index, q->inflight); 3757838c67fSStefan Hajnoczi if (s->plugged) { 3767838c67fSStefan Hajnoczi trace_nvme_process_completion_queue_plugged(s, q->index); 377bdd6a90aSFam Zheng return false; 378bdd6a90aSFam Zheng } 3797838c67fSStefan Hajnoczi 3807838c67fSStefan Hajnoczi /* 3817838c67fSStefan Hajnoczi * Support re-entrancy when a request cb() function invokes aio_poll(). 3827838c67fSStefan Hajnoczi * Pending completions must be visible to aio_poll() so that a cb() 3837838c67fSStefan Hajnoczi * function can wait for the completion of another request. 3847838c67fSStefan Hajnoczi * 3857838c67fSStefan Hajnoczi * The aio_poll() loop will execute our BH and we'll resume completion 3867838c67fSStefan Hajnoczi * processing there. 3877838c67fSStefan Hajnoczi */ 3887838c67fSStefan Hajnoczi qemu_bh_schedule(q->completion_bh); 3897838c67fSStefan Hajnoczi 390bdd6a90aSFam Zheng assert(q->inflight >= 0); 391bdd6a90aSFam Zheng while (q->inflight) { 39204b3fb39SStefan Hajnoczi int ret; 393bdd6a90aSFam Zheng int16_t cid; 39404b3fb39SStefan Hajnoczi 395bdd6a90aSFam Zheng c = (NvmeCqe *)&q->cq.queue[q->cq.head * NVME_CQ_ENTRY_BYTES]; 396258867d1SMaxim Levitsky if ((le16_to_cpu(c->status) & 0x1) == q->cq_phase) { 397bdd6a90aSFam Zheng break; 398bdd6a90aSFam Zheng } 39904b3fb39SStefan Hajnoczi ret = nvme_translate_error(c); 400f25e7ab2SPhilippe Mathieu-Daudé if (ret) { 401f25e7ab2SPhilippe Mathieu-Daudé s->stats.completion_errors++; 402f25e7ab2SPhilippe Mathieu-Daudé } 403bdd6a90aSFam Zheng q->cq.head = (q->cq.head + 1) % NVME_QUEUE_SIZE; 404bdd6a90aSFam Zheng if (!q->cq.head) { 405bdd6a90aSFam Zheng q->cq_phase = !q->cq_phase; 406bdd6a90aSFam Zheng } 407bdd6a90aSFam Zheng cid = le16_to_cpu(c->cid); 408bdd6a90aSFam Zheng if (cid == 0 || cid > NVME_QUEUE_SIZE) { 40958ad6ae0SPhilippe Mathieu-Daudé warn_report("NVMe: Unexpected CID in completion queue: %"PRIu32", " 41058ad6ae0SPhilippe Mathieu-Daudé "queue size: %u", cid, NVME_QUEUE_SIZE); 411bdd6a90aSFam Zheng continue; 412bdd6a90aSFam Zheng } 413bdd6a90aSFam Zheng trace_nvme_complete_command(s, q->index, cid); 414bdd6a90aSFam Zheng preq = &q->reqs[cid - 1]; 415bdd6a90aSFam Zheng req = *preq; 416bdd6a90aSFam Zheng assert(req.cid == cid); 417bdd6a90aSFam Zheng assert(req.cb); 4181086e95dSStefan Hajnoczi nvme_put_free_req_locked(q, preq); 419bdd6a90aSFam Zheng preq->cb = preq->opaque = NULL; 4207838c67fSStefan Hajnoczi q->inflight--; 421bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 42204b3fb39SStefan Hajnoczi req.cb(req.opaque, ret); 423bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 424bdd6a90aSFam Zheng progress = true; 425bdd6a90aSFam Zheng } 426bdd6a90aSFam Zheng if (progress) { 427bdd6a90aSFam Zheng /* Notify the device so it can post more completions. */ 428bdd6a90aSFam Zheng smp_mb_release(); 429bdd6a90aSFam Zheng *q->cq.doorbell = cpu_to_le32(q->cq.head); 430b75fd5f5SStefan Hajnoczi nvme_wake_free_req_locked(q); 431bdd6a90aSFam Zheng } 4327838c67fSStefan Hajnoczi 4337838c67fSStefan Hajnoczi qemu_bh_cancel(q->completion_bh); 4347838c67fSStefan Hajnoczi 435bdd6a90aSFam Zheng return progress; 436bdd6a90aSFam Zheng } 437bdd6a90aSFam Zheng 4387838c67fSStefan Hajnoczi static void nvme_process_completion_bh(void *opaque) 4397838c67fSStefan Hajnoczi { 4407838c67fSStefan Hajnoczi NVMeQueuePair *q = opaque; 4417838c67fSStefan Hajnoczi 4427838c67fSStefan Hajnoczi /* 4437838c67fSStefan Hajnoczi * We're being invoked because a nvme_process_completion() cb() function 4447838c67fSStefan Hajnoczi * called aio_poll(). The callback may be waiting for further completions 4457838c67fSStefan Hajnoczi * so notify the device that it has space to fill in more completions now. 4467838c67fSStefan Hajnoczi */ 4477838c67fSStefan Hajnoczi smp_mb_release(); 4487838c67fSStefan Hajnoczi *q->cq.doorbell = cpu_to_le32(q->cq.head); 4497838c67fSStefan Hajnoczi nvme_wake_free_req_locked(q); 4507838c67fSStefan Hajnoczi 4517838c67fSStefan Hajnoczi nvme_process_completion(q); 4527838c67fSStefan Hajnoczi } 4537838c67fSStefan Hajnoczi 454bdd6a90aSFam Zheng static void nvme_trace_command(const NvmeCmd *cmd) 455bdd6a90aSFam Zheng { 456bdd6a90aSFam Zheng int i; 457bdd6a90aSFam Zheng 458e266f52cSPhilippe Mathieu-Daudé if (!trace_event_get_state_backends(TRACE_NVME_SUBMIT_COMMAND_RAW)) { 459e266f52cSPhilippe Mathieu-Daudé return; 460e266f52cSPhilippe Mathieu-Daudé } 461bdd6a90aSFam Zheng for (i = 0; i < 8; ++i) { 462bdd6a90aSFam Zheng uint8_t *cmdp = (uint8_t *)cmd + i * 8; 463bdd6a90aSFam Zheng trace_nvme_submit_command_raw(cmdp[0], cmdp[1], cmdp[2], cmdp[3], 464bdd6a90aSFam Zheng cmdp[4], cmdp[5], cmdp[6], cmdp[7]); 465bdd6a90aSFam Zheng } 466bdd6a90aSFam Zheng } 467bdd6a90aSFam Zheng 468b75fd5f5SStefan Hajnoczi static void nvme_submit_command(NVMeQueuePair *q, NVMeRequest *req, 469bdd6a90aSFam Zheng NvmeCmd *cmd, BlockCompletionFunc cb, 470bdd6a90aSFam Zheng void *opaque) 471bdd6a90aSFam Zheng { 472bdd6a90aSFam Zheng assert(!req->cb); 473bdd6a90aSFam Zheng req->cb = cb; 474bdd6a90aSFam Zheng req->opaque = opaque; 475a0546a7bSPhilippe Mathieu-Daudé cmd->cid = cpu_to_le16(req->cid); 476bdd6a90aSFam Zheng 477b75fd5f5SStefan Hajnoczi trace_nvme_submit_command(q->s, q->index, req->cid); 478bdd6a90aSFam Zheng nvme_trace_command(cmd); 479bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 480bdd6a90aSFam Zheng memcpy((uint8_t *)q->sq.queue + 481bdd6a90aSFam Zheng q->sq.tail * NVME_SQ_ENTRY_BYTES, cmd, sizeof(*cmd)); 482bdd6a90aSFam Zheng q->sq.tail = (q->sq.tail + 1) % NVME_QUEUE_SIZE; 483bdd6a90aSFam Zheng q->need_kick++; 484b75fd5f5SStefan Hajnoczi nvme_kick(q); 485b75fd5f5SStefan Hajnoczi nvme_process_completion(q); 486bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 487bdd6a90aSFam Zheng } 488bdd6a90aSFam Zheng 48908d54067SPhilippe Mathieu-Daudé static void nvme_admin_cmd_sync_cb(void *opaque, int ret) 490bdd6a90aSFam Zheng { 491bdd6a90aSFam Zheng int *pret = opaque; 492bdd6a90aSFam Zheng *pret = ret; 4934720cbeeSKevin Wolf aio_wait_kick(); 494bdd6a90aSFam Zheng } 495bdd6a90aSFam Zheng 49608d54067SPhilippe Mathieu-Daudé static int nvme_admin_cmd_sync(BlockDriverState *bs, NvmeCmd *cmd) 497bdd6a90aSFam Zheng { 49808d54067SPhilippe Mathieu-Daudé BDRVNVMeState *s = bs->opaque; 49908d54067SPhilippe Mathieu-Daudé NVMeQueuePair *q = s->queues[INDEX_ADMIN]; 500073a0697SPhilippe Mathieu-Daudé AioContext *aio_context = bdrv_get_aio_context(bs); 501bdd6a90aSFam Zheng NVMeRequest *req; 502bdd6a90aSFam Zheng int ret = -EINPROGRESS; 503bdd6a90aSFam Zheng req = nvme_get_free_req(q); 504bdd6a90aSFam Zheng if (!req) { 505bdd6a90aSFam Zheng return -EBUSY; 506bdd6a90aSFam Zheng } 50708d54067SPhilippe Mathieu-Daudé nvme_submit_command(q, req, cmd, nvme_admin_cmd_sync_cb, &ret); 508bdd6a90aSFam Zheng 509073a0697SPhilippe Mathieu-Daudé AIO_WAIT_WHILE(aio_context, ret == -EINPROGRESS); 510bdd6a90aSFam Zheng return ret; 511bdd6a90aSFam Zheng } 512bdd6a90aSFam Zheng 5137a5f00ddSPhilippe Mathieu-Daudé /* Returns true on success, false on failure. */ 5147a5f00ddSPhilippe Mathieu-Daudé static bool nvme_identify(BlockDriverState *bs, int namespace, Error **errp) 515bdd6a90aSFam Zheng { 516bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 5177a5f00ddSPhilippe Mathieu-Daudé bool ret = false; 5187d3b214aSPhilippe Mathieu-Daudé union { 5197d3b214aSPhilippe Mathieu-Daudé NvmeIdCtrl ctrl; 5207d3b214aSPhilippe Mathieu-Daudé NvmeIdNs ns; 5217d3b214aSPhilippe Mathieu-Daudé } *id; 522118d1b6aSMaxim Levitsky NvmeLBAF *lbaf; 523e0dd95e3SMaxim Levitsky uint16_t oncs; 5241120407bSMax Reitz int r; 525bdd6a90aSFam Zheng uint64_t iova; 526bdd6a90aSFam Zheng NvmeCmd cmd = { 527bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_IDENTIFY, 528bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(0x1), 529bdd6a90aSFam Zheng }; 5300aecd060SEric Auger size_t id_size = QEMU_ALIGN_UP(sizeof(*id), qemu_real_host_page_size); 531bdd6a90aSFam Zheng 5320aecd060SEric Auger id = qemu_try_memalign(qemu_real_host_page_size, id_size); 5334d980939SPhilippe Mathieu-Daudé if (!id) { 534bdd6a90aSFam Zheng error_setg(errp, "Cannot allocate buffer for identify response"); 535bdd6a90aSFam Zheng goto out; 536bdd6a90aSFam Zheng } 5370aecd060SEric Auger r = qemu_vfio_dma_map(s->vfio, id, id_size, true, &iova); 538bdd6a90aSFam Zheng if (r) { 539bdd6a90aSFam Zheng error_setg(errp, "Cannot map buffer for DMA"); 540bdd6a90aSFam Zheng goto out; 541bdd6a90aSFam Zheng } 542bdd6a90aSFam Zheng 5430aecd060SEric Auger memset(id, 0, id_size); 5442ed84693SPhilippe Mathieu-Daudé cmd.dptr.prp1 = cpu_to_le64(iova); 54508d54067SPhilippe Mathieu-Daudé if (nvme_admin_cmd_sync(bs, &cmd)) { 546bdd6a90aSFam Zheng error_setg(errp, "Failed to identify controller"); 547bdd6a90aSFam Zheng goto out; 548bdd6a90aSFam Zheng } 549bdd6a90aSFam Zheng 5507d3b214aSPhilippe Mathieu-Daudé if (le32_to_cpu(id->ctrl.nn) < namespace) { 551bdd6a90aSFam Zheng error_setg(errp, "Invalid namespace"); 552bdd6a90aSFam Zheng goto out; 553bdd6a90aSFam Zheng } 5547d3b214aSPhilippe Mathieu-Daudé s->write_cache_supported = le32_to_cpu(id->ctrl.vwc) & 0x1; 5557d3b214aSPhilippe Mathieu-Daudé s->max_transfer = (id->ctrl.mdts ? 1 << id->ctrl.mdts : 0) * s->page_size; 556bdd6a90aSFam Zheng /* For now the page list buffer per command is one page, to hold at most 557bdd6a90aSFam Zheng * s->page_size / sizeof(uint64_t) entries. */ 558bdd6a90aSFam Zheng s->max_transfer = MIN_NON_ZERO(s->max_transfer, 559bdd6a90aSFam Zheng s->page_size / sizeof(uint64_t) * s->page_size); 560bdd6a90aSFam Zheng 5617d3b214aSPhilippe Mathieu-Daudé oncs = le16_to_cpu(id->ctrl.oncs); 56269265150SKlaus Jensen s->supports_write_zeroes = !!(oncs & NVME_ONCS_WRITE_ZEROES); 563e87a09d6SMaxim Levitsky s->supports_discard = !!(oncs & NVME_ONCS_DSM); 564e0dd95e3SMaxim Levitsky 5650aecd060SEric Auger memset(id, 0, id_size); 566bdd6a90aSFam Zheng cmd.cdw10 = 0; 567bdd6a90aSFam Zheng cmd.nsid = cpu_to_le32(namespace); 56808d54067SPhilippe Mathieu-Daudé if (nvme_admin_cmd_sync(bs, &cmd)) { 569bdd6a90aSFam Zheng error_setg(errp, "Failed to identify namespace"); 570bdd6a90aSFam Zheng goto out; 571bdd6a90aSFam Zheng } 572bdd6a90aSFam Zheng 5737d3b214aSPhilippe Mathieu-Daudé s->nsze = le64_to_cpu(id->ns.nsze); 5747d3b214aSPhilippe Mathieu-Daudé lbaf = &id->ns.lbaf[NVME_ID_NS_FLBAS_INDEX(id->ns.flbas)]; 575bdd6a90aSFam Zheng 5767d3b214aSPhilippe Mathieu-Daudé if (NVME_ID_NS_DLFEAT_WRITE_ZEROES(id->ns.dlfeat) && 5777d3b214aSPhilippe Mathieu-Daudé NVME_ID_NS_DLFEAT_READ_BEHAVIOR(id->ns.dlfeat) == 578e0dd95e3SMaxim Levitsky NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES) { 579e0dd95e3SMaxim Levitsky bs->supported_write_flags |= BDRV_REQ_MAY_UNMAP; 580e0dd95e3SMaxim Levitsky } 581e0dd95e3SMaxim Levitsky 582118d1b6aSMaxim Levitsky if (lbaf->ms) { 583118d1b6aSMaxim Levitsky error_setg(errp, "Namespaces with metadata are not yet supported"); 584118d1b6aSMaxim Levitsky goto out; 585118d1b6aSMaxim Levitsky } 586118d1b6aSMaxim Levitsky 5871120407bSMax Reitz if (lbaf->ds < BDRV_SECTOR_BITS || lbaf->ds > 12 || 5881120407bSMax Reitz (1 << lbaf->ds) > s->page_size) 5891120407bSMax Reitz { 5901120407bSMax Reitz error_setg(errp, "Namespace has unsupported block size (2^%d)", 5911120407bSMax Reitz lbaf->ds); 592118d1b6aSMaxim Levitsky goto out; 593118d1b6aSMaxim Levitsky } 594118d1b6aSMaxim Levitsky 5957a5f00ddSPhilippe Mathieu-Daudé ret = true; 596118d1b6aSMaxim Levitsky s->blkshift = lbaf->ds; 597bdd6a90aSFam Zheng out: 5984d980939SPhilippe Mathieu-Daudé qemu_vfio_dma_unmap(s->vfio, id); 5994d980939SPhilippe Mathieu-Daudé qemu_vfree(id); 6007a5f00ddSPhilippe Mathieu-Daudé 6017a5f00ddSPhilippe Mathieu-Daudé return ret; 602bdd6a90aSFam Zheng } 603bdd6a90aSFam Zheng 6047a1fb2efSPhilippe Mathieu-Daudé static bool nvme_poll_queue(NVMeQueuePair *q) 605bdd6a90aSFam Zheng { 606bdd6a90aSFam Zheng bool progress = false; 607bdd6a90aSFam Zheng 6082446e0e2SStefan Hajnoczi const size_t cqe_offset = q->cq.head * NVME_CQ_ENTRY_BYTES; 6092446e0e2SStefan Hajnoczi NvmeCqe *cqe = (NvmeCqe *)&q->cq.queue[cqe_offset]; 6102446e0e2SStefan Hajnoczi 6111c914cd1SPhilippe Mathieu-Daudé trace_nvme_poll_queue(q->s, q->index); 6122446e0e2SStefan Hajnoczi /* 6132446e0e2SStefan Hajnoczi * Do an early check for completions. q->lock isn't needed because 6142446e0e2SStefan Hajnoczi * nvme_process_completion() only runs in the event loop thread and 6152446e0e2SStefan Hajnoczi * cannot race with itself. 6162446e0e2SStefan Hajnoczi */ 6172446e0e2SStefan Hajnoczi if ((le16_to_cpu(cqe->status) & 0x1) == q->cq_phase) { 6187a1fb2efSPhilippe Mathieu-Daudé return false; 6192446e0e2SStefan Hajnoczi } 6202446e0e2SStefan Hajnoczi 621bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 622b75fd5f5SStefan Hajnoczi while (nvme_process_completion(q)) { 623bdd6a90aSFam Zheng /* Keep polling */ 624bdd6a90aSFam Zheng progress = true; 625bdd6a90aSFam Zheng } 626bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 6277a1fb2efSPhilippe Mathieu-Daudé 6287a1fb2efSPhilippe Mathieu-Daudé return progress; 6297a1fb2efSPhilippe Mathieu-Daudé } 6307a1fb2efSPhilippe Mathieu-Daudé 6317a1fb2efSPhilippe Mathieu-Daudé static bool nvme_poll_queues(BDRVNVMeState *s) 6327a1fb2efSPhilippe Mathieu-Daudé { 6337a1fb2efSPhilippe Mathieu-Daudé bool progress = false; 6347a1fb2efSPhilippe Mathieu-Daudé int i; 6357a1fb2efSPhilippe Mathieu-Daudé 6361b539bd6SPhilippe Mathieu-Daudé for (i = 0; i < s->queue_count; i++) { 6377a1fb2efSPhilippe Mathieu-Daudé if (nvme_poll_queue(s->queues[i])) { 6387a1fb2efSPhilippe Mathieu-Daudé progress = true; 6397a1fb2efSPhilippe Mathieu-Daudé } 640bdd6a90aSFam Zheng } 641bdd6a90aSFam Zheng return progress; 642bdd6a90aSFam Zheng } 643bdd6a90aSFam Zheng 644bdd6a90aSFam Zheng static void nvme_handle_event(EventNotifier *n) 645bdd6a90aSFam Zheng { 646b111b3fcSPhilippe Mathieu-Daudé BDRVNVMeState *s = container_of(n, BDRVNVMeState, 647b111b3fcSPhilippe Mathieu-Daudé irq_notifier[MSIX_SHARED_IRQ_IDX]); 648bdd6a90aSFam Zheng 649bdd6a90aSFam Zheng trace_nvme_handle_event(s); 650bdd6a90aSFam Zheng event_notifier_test_and_clear(n); 651bdd6a90aSFam Zheng nvme_poll_queues(s); 652bdd6a90aSFam Zheng } 653bdd6a90aSFam Zheng 654bdd6a90aSFam Zheng static bool nvme_add_io_queue(BlockDriverState *bs, Error **errp) 655bdd6a90aSFam Zheng { 656bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 6571b539bd6SPhilippe Mathieu-Daudé unsigned n = s->queue_count; 658bdd6a90aSFam Zheng NVMeQueuePair *q; 659bdd6a90aSFam Zheng NvmeCmd cmd; 6601b539bd6SPhilippe Mathieu-Daudé unsigned queue_size = NVME_QUEUE_SIZE; 661bdd6a90aSFam Zheng 66276a24781SPhilippe Mathieu-Daudé assert(n <= UINT16_MAX); 6630a28b02eSPhilippe Mathieu-Daudé q = nvme_create_queue_pair(s, bdrv_get_aio_context(bs), 6640a28b02eSPhilippe Mathieu-Daudé n, queue_size, errp); 665bdd6a90aSFam Zheng if (!q) { 666bdd6a90aSFam Zheng return false; 667bdd6a90aSFam Zheng } 668bdd6a90aSFam Zheng cmd = (NvmeCmd) { 669bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_CREATE_CQ, 670c26f2173SKlaus Jensen .dptr.prp1 = cpu_to_le64(q->cq.iova), 67176a24781SPhilippe Mathieu-Daudé .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n), 67276a24781SPhilippe Mathieu-Daudé .cdw11 = cpu_to_le32(NVME_CQ_IEN | NVME_CQ_PC), 673bdd6a90aSFam Zheng }; 67408d54067SPhilippe Mathieu-Daudé if (nvme_admin_cmd_sync(bs, &cmd)) { 6751b539bd6SPhilippe Mathieu-Daudé error_setg(errp, "Failed to create CQ io queue [%u]", n); 676c8edbfb2SPhilippe Mathieu-Daudé goto out_error; 677bdd6a90aSFam Zheng } 678bdd6a90aSFam Zheng cmd = (NvmeCmd) { 679bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_CREATE_SQ, 680c26f2173SKlaus Jensen .dptr.prp1 = cpu_to_le64(q->sq.iova), 68176a24781SPhilippe Mathieu-Daudé .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n), 68276a24781SPhilippe Mathieu-Daudé .cdw11 = cpu_to_le32(NVME_SQ_PC | (n << 16)), 683bdd6a90aSFam Zheng }; 68408d54067SPhilippe Mathieu-Daudé if (nvme_admin_cmd_sync(bs, &cmd)) { 6851b539bd6SPhilippe Mathieu-Daudé error_setg(errp, "Failed to create SQ io queue [%u]", n); 686c8edbfb2SPhilippe Mathieu-Daudé goto out_error; 687bdd6a90aSFam Zheng } 688bdd6a90aSFam Zheng s->queues = g_renew(NVMeQueuePair *, s->queues, n + 1); 689bdd6a90aSFam Zheng s->queues[n] = q; 6901b539bd6SPhilippe Mathieu-Daudé s->queue_count++; 691bdd6a90aSFam Zheng return true; 692c8edbfb2SPhilippe Mathieu-Daudé out_error: 693c8edbfb2SPhilippe Mathieu-Daudé nvme_free_queue_pair(q); 694c8edbfb2SPhilippe Mathieu-Daudé return false; 695bdd6a90aSFam Zheng } 696bdd6a90aSFam Zheng 697bdd6a90aSFam Zheng static bool nvme_poll_cb(void *opaque) 698bdd6a90aSFam Zheng { 699bdd6a90aSFam Zheng EventNotifier *e = opaque; 700b111b3fcSPhilippe Mathieu-Daudé BDRVNVMeState *s = container_of(e, BDRVNVMeState, 701b111b3fcSPhilippe Mathieu-Daudé irq_notifier[MSIX_SHARED_IRQ_IDX]); 702bdd6a90aSFam Zheng 703b3ac2b94SSimran Singhal return nvme_poll_queues(s); 704bdd6a90aSFam Zheng } 705bdd6a90aSFam Zheng 706bdd6a90aSFam Zheng static int nvme_init(BlockDriverState *bs, const char *device, int namespace, 707bdd6a90aSFam Zheng Error **errp) 708bdd6a90aSFam Zheng { 709bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 71052b75ea8SPhilippe Mathieu-Daudé NVMeQueuePair *q; 7110a28b02eSPhilippe Mathieu-Daudé AioContext *aio_context = bdrv_get_aio_context(bs); 712bdd6a90aSFam Zheng int ret; 713bdd6a90aSFam Zheng uint64_t cap; 714fcc8672aSPhilippe Mathieu-Daudé uint32_t ver; 715bdd6a90aSFam Zheng uint64_t timeout_ms; 716bdd6a90aSFam Zheng uint64_t deadline, now; 7179406e0d9SPhilippe Mathieu-Daudé volatile NvmeBar *regs = NULL; 718bdd6a90aSFam Zheng 719bdd6a90aSFam Zheng qemu_co_mutex_init(&s->dma_map_lock); 720bdd6a90aSFam Zheng qemu_co_queue_init(&s->dma_flush_queue); 721cc61b074SMax Reitz s->device = g_strdup(device); 722bdd6a90aSFam Zheng s->nsid = namespace; 723bdd6a90aSFam Zheng s->aio_context = bdrv_get_aio_context(bs); 724b111b3fcSPhilippe Mathieu-Daudé ret = event_notifier_init(&s->irq_notifier[MSIX_SHARED_IRQ_IDX], 0); 725bdd6a90aSFam Zheng if (ret) { 726bdd6a90aSFam Zheng error_setg(errp, "Failed to init event notifier"); 727bdd6a90aSFam Zheng return ret; 728bdd6a90aSFam Zheng } 729bdd6a90aSFam Zheng 730bdd6a90aSFam Zheng s->vfio = qemu_vfio_open_pci(device, errp); 731bdd6a90aSFam Zheng if (!s->vfio) { 732bdd6a90aSFam Zheng ret = -EINVAL; 7339582f357SFam Zheng goto out; 734bdd6a90aSFam Zheng } 735bdd6a90aSFam Zheng 73637d7a45aSPhilippe Mathieu-Daudé regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, sizeof(NvmeBar), 737b02c01a5SPhilippe Mathieu-Daudé PROT_READ | PROT_WRITE, errp); 73837d7a45aSPhilippe Mathieu-Daudé if (!regs) { 739bdd6a90aSFam Zheng ret = -EINVAL; 7409582f357SFam Zheng goto out; 741bdd6a90aSFam Zheng } 742bdd6a90aSFam Zheng /* Perform initialize sequence as described in NVMe spec "7.6.1 743bdd6a90aSFam Zheng * Initialization". */ 744bdd6a90aSFam Zheng 7459406e0d9SPhilippe Mathieu-Daudé cap = le64_to_cpu(regs->cap); 74615b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability_raw(cap); 74715b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Maximum Queue Entries Supported", 74815b2260bSPhilippe Mathieu-Daudé 1 + NVME_CAP_MQES(cap)); 74915b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Contiguous Queues Required", 75015b2260bSPhilippe Mathieu-Daudé NVME_CAP_CQR(cap)); 75115b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Doorbell Stride", 75297b709f3SPhilippe Mathieu-Daudé 1 << (2 + NVME_CAP_DSTRD(cap))); 75315b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Subsystem Reset Supported", 75415b2260bSPhilippe Mathieu-Daudé NVME_CAP_NSSRS(cap)); 75515b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Memory Page Size Minimum", 75615b2260bSPhilippe Mathieu-Daudé 1 << (12 + NVME_CAP_MPSMIN(cap))); 75715b2260bSPhilippe Mathieu-Daudé trace_nvme_controller_capability("Memory Page Size Maximum", 75815b2260bSPhilippe Mathieu-Daudé 1 << (12 + NVME_CAP_MPSMAX(cap))); 759fad1eb68SPhilippe Mathieu-Daudé if (!NVME_CAP_CSS(cap)) { 760bdd6a90aSFam Zheng error_setg(errp, "Device doesn't support NVMe command set"); 761bdd6a90aSFam Zheng ret = -EINVAL; 7629582f357SFam Zheng goto out; 763bdd6a90aSFam Zheng } 764bdd6a90aSFam Zheng 765a652a3ecSPhilippe Mathieu-Daudé s->page_size = 1u << (12 + NVME_CAP_MPSMIN(cap)); 766fad1eb68SPhilippe Mathieu-Daudé s->doorbell_scale = (4 << NVME_CAP_DSTRD(cap)) / sizeof(uint32_t); 767bdd6a90aSFam Zheng bs->bl.opt_mem_alignment = s->page_size; 768c8228ac3SPhilippe Mathieu-Daudé bs->bl.request_alignment = s->page_size; 769fad1eb68SPhilippe Mathieu-Daudé timeout_ms = MIN(500 * NVME_CAP_TO(cap), 30000); 770bdd6a90aSFam Zheng 771fcc8672aSPhilippe Mathieu-Daudé ver = le32_to_cpu(regs->vs); 772fcc8672aSPhilippe Mathieu-Daudé trace_nvme_controller_spec_version(extract32(ver, 16, 16), 773fcc8672aSPhilippe Mathieu-Daudé extract32(ver, 8, 8), 774fcc8672aSPhilippe Mathieu-Daudé extract32(ver, 0, 8)); 775fcc8672aSPhilippe Mathieu-Daudé 776bdd6a90aSFam Zheng /* Reset device to get a clean state. */ 7779406e0d9SPhilippe Mathieu-Daudé regs->cc = cpu_to_le32(le32_to_cpu(regs->cc) & 0xFE); 778bdd6a90aSFam Zheng /* Wait for CSTS.RDY = 0. */ 779e4f310feSPhilippe Mathieu-Daudé deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCALE_MS; 780fad1eb68SPhilippe Mathieu-Daudé while (NVME_CSTS_RDY(le32_to_cpu(regs->csts))) { 781bdd6a90aSFam Zheng if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 782bdd6a90aSFam Zheng error_setg(errp, "Timeout while waiting for device to reset (%" 783bdd6a90aSFam Zheng PRId64 " ms)", 784bdd6a90aSFam Zheng timeout_ms); 785bdd6a90aSFam Zheng ret = -ETIMEDOUT; 7869582f357SFam Zheng goto out; 787bdd6a90aSFam Zheng } 788bdd6a90aSFam Zheng } 789bdd6a90aSFam Zheng 7904b19e9b8SPhilippe Mathieu-Daudé s->bar0_wo_map = qemu_vfio_pci_map_bar(s->vfio, 0, 0, 7914b19e9b8SPhilippe Mathieu-Daudé sizeof(NvmeBar) + NVME_DOORBELL_SIZE, 7924b19e9b8SPhilippe Mathieu-Daudé PROT_WRITE, errp); 7934b19e9b8SPhilippe Mathieu-Daudé s->doorbells = (void *)((uintptr_t)s->bar0_wo_map + sizeof(NvmeBar)); 794f6845323SPhilippe Mathieu-Daudé if (!s->doorbells) { 795f6845323SPhilippe Mathieu-Daudé ret = -EINVAL; 796f6845323SPhilippe Mathieu-Daudé goto out; 797f6845323SPhilippe Mathieu-Daudé } 798f6845323SPhilippe Mathieu-Daudé 799bdd6a90aSFam Zheng /* Set up admin queue. */ 800bdd6a90aSFam Zheng s->queues = g_new(NVMeQueuePair *, 1); 80152b75ea8SPhilippe Mathieu-Daudé q = nvme_create_queue_pair(s, aio_context, 0, NVME_QUEUE_SIZE, errp); 80252b75ea8SPhilippe Mathieu-Daudé if (!q) { 803bdd6a90aSFam Zheng ret = -EINVAL; 8049582f357SFam Zheng goto out; 805bdd6a90aSFam Zheng } 80652b75ea8SPhilippe Mathieu-Daudé s->queues[INDEX_ADMIN] = q; 8071b539bd6SPhilippe Mathieu-Daudé s->queue_count = 1; 8083c363c07SPhilippe Mathieu-Daudé QEMU_BUILD_BUG_ON((NVME_QUEUE_SIZE - 1) & 0xF000); 8093c363c07SPhilippe Mathieu-Daudé regs->aqa = cpu_to_le32(((NVME_QUEUE_SIZE - 1) << AQA_ACQS_SHIFT) | 8103c363c07SPhilippe Mathieu-Daudé ((NVME_QUEUE_SIZE - 1) << AQA_ASQS_SHIFT)); 81152b75ea8SPhilippe Mathieu-Daudé regs->asq = cpu_to_le64(q->sq.iova); 81252b75ea8SPhilippe Mathieu-Daudé regs->acq = cpu_to_le64(q->cq.iova); 813bdd6a90aSFam Zheng 814bdd6a90aSFam Zheng /* After setting up all control registers we can enable device now. */ 815fad1eb68SPhilippe Mathieu-Daudé regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << CC_IOCQES_SHIFT) | 816fad1eb68SPhilippe Mathieu-Daudé (ctz32(NVME_SQ_ENTRY_BYTES) << CC_IOSQES_SHIFT) | 817fad1eb68SPhilippe Mathieu-Daudé CC_EN_MASK); 818bdd6a90aSFam Zheng /* Wait for CSTS.RDY = 1. */ 819bdd6a90aSFam Zheng now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 820eefffb02SPhilippe Mathieu-Daudé deadline = now + timeout_ms * SCALE_MS; 821fad1eb68SPhilippe Mathieu-Daudé while (!NVME_CSTS_RDY(le32_to_cpu(regs->csts))) { 822bdd6a90aSFam Zheng if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 823bdd6a90aSFam Zheng error_setg(errp, "Timeout while waiting for device to start (%" 824bdd6a90aSFam Zheng PRId64 " ms)", 825bdd6a90aSFam Zheng timeout_ms); 826bdd6a90aSFam Zheng ret = -ETIMEDOUT; 8279582f357SFam Zheng goto out; 828bdd6a90aSFam Zheng } 829bdd6a90aSFam Zheng } 830bdd6a90aSFam Zheng 831b111b3fcSPhilippe Mathieu-Daudé ret = qemu_vfio_pci_init_irq(s->vfio, s->irq_notifier, 832bdd6a90aSFam Zheng VFIO_PCI_MSIX_IRQ_INDEX, errp); 833bdd6a90aSFam Zheng if (ret) { 8349582f357SFam Zheng goto out; 835bdd6a90aSFam Zheng } 836b111b3fcSPhilippe Mathieu-Daudé aio_set_event_notifier(bdrv_get_aio_context(bs), 837b111b3fcSPhilippe Mathieu-Daudé &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 838bdd6a90aSFam Zheng false, nvme_handle_event, nvme_poll_cb); 839bdd6a90aSFam Zheng 8407a5f00ddSPhilippe Mathieu-Daudé if (!nvme_identify(bs, namespace, errp)) { 841bdd6a90aSFam Zheng ret = -EIO; 8429582f357SFam Zheng goto out; 843bdd6a90aSFam Zheng } 844bdd6a90aSFam Zheng 845bdd6a90aSFam Zheng /* Set up command queues. */ 846bdd6a90aSFam Zheng if (!nvme_add_io_queue(bs, errp)) { 847bdd6a90aSFam Zheng ret = -EIO; 848bdd6a90aSFam Zheng } 8499582f357SFam Zheng out: 85037d7a45aSPhilippe Mathieu-Daudé if (regs) { 85137d7a45aSPhilippe Mathieu-Daudé qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)regs, 0, sizeof(NvmeBar)); 85237d7a45aSPhilippe Mathieu-Daudé } 85337d7a45aSPhilippe Mathieu-Daudé 8549582f357SFam Zheng /* Cleaning up is done in nvme_file_open() upon error. */ 855bdd6a90aSFam Zheng return ret; 856bdd6a90aSFam Zheng } 857bdd6a90aSFam Zheng 858bdd6a90aSFam Zheng /* Parse a filename in the format of nvme://XXXX:XX:XX.X/X. Example: 859bdd6a90aSFam Zheng * 860bdd6a90aSFam Zheng * nvme://0000:44:00.0/1 861bdd6a90aSFam Zheng * 862bdd6a90aSFam Zheng * where the "nvme://" is a fixed form of the protocol prefix, the middle part 863bdd6a90aSFam Zheng * is the PCI address, and the last part is the namespace number starting from 864bdd6a90aSFam Zheng * 1 according to the NVMe spec. */ 865bdd6a90aSFam Zheng static void nvme_parse_filename(const char *filename, QDict *options, 866bdd6a90aSFam Zheng Error **errp) 867bdd6a90aSFam Zheng { 868bdd6a90aSFam Zheng int pref = strlen("nvme://"); 869bdd6a90aSFam Zheng 870bdd6a90aSFam Zheng if (strlen(filename) > pref && !strncmp(filename, "nvme://", pref)) { 871bdd6a90aSFam Zheng const char *tmp = filename + pref; 872bdd6a90aSFam Zheng char *device; 873bdd6a90aSFam Zheng const char *namespace; 874bdd6a90aSFam Zheng unsigned long ns; 875bdd6a90aSFam Zheng const char *slash = strchr(tmp, '/'); 876bdd6a90aSFam Zheng if (!slash) { 877625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, tmp); 878bdd6a90aSFam Zheng return; 879bdd6a90aSFam Zheng } 880bdd6a90aSFam Zheng device = g_strndup(tmp, slash - tmp); 881625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, device); 882bdd6a90aSFam Zheng g_free(device); 883bdd6a90aSFam Zheng namespace = slash + 1; 884bdd6a90aSFam Zheng if (*namespace && qemu_strtoul(namespace, NULL, 10, &ns)) { 885bdd6a90aSFam Zheng error_setg(errp, "Invalid namespace '%s', positive number expected", 886bdd6a90aSFam Zheng namespace); 887bdd6a90aSFam Zheng return; 888bdd6a90aSFam Zheng } 889625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_NAMESPACE, 890625eaca9SLaurent Vivier *namespace ? namespace : "1"); 891bdd6a90aSFam Zheng } 892bdd6a90aSFam Zheng } 893bdd6a90aSFam Zheng 894bdd6a90aSFam Zheng static int nvme_enable_disable_write_cache(BlockDriverState *bs, bool enable, 895bdd6a90aSFam Zheng Error **errp) 896bdd6a90aSFam Zheng { 897bdd6a90aSFam Zheng int ret; 898bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 899bdd6a90aSFam Zheng NvmeCmd cmd = { 900bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_SET_FEATURES, 901bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 902bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(0x06), 903bdd6a90aSFam Zheng .cdw11 = cpu_to_le32(enable ? 0x01 : 0x00), 904bdd6a90aSFam Zheng }; 905bdd6a90aSFam Zheng 90608d54067SPhilippe Mathieu-Daudé ret = nvme_admin_cmd_sync(bs, &cmd); 907bdd6a90aSFam Zheng if (ret) { 908bdd6a90aSFam Zheng error_setg(errp, "Failed to configure NVMe write cache"); 909bdd6a90aSFam Zheng } 910bdd6a90aSFam Zheng return ret; 911bdd6a90aSFam Zheng } 912bdd6a90aSFam Zheng 913bdd6a90aSFam Zheng static void nvme_close(BlockDriverState *bs) 914bdd6a90aSFam Zheng { 915bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 916bdd6a90aSFam Zheng 9171b539bd6SPhilippe Mathieu-Daudé for (unsigned i = 0; i < s->queue_count; ++i) { 918b75fd5f5SStefan Hajnoczi nvme_free_queue_pair(s->queues[i]); 919bdd6a90aSFam Zheng } 9209582f357SFam Zheng g_free(s->queues); 921b111b3fcSPhilippe Mathieu-Daudé aio_set_event_notifier(bdrv_get_aio_context(bs), 922b111b3fcSPhilippe Mathieu-Daudé &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 923bdd6a90aSFam Zheng false, NULL, NULL); 924b111b3fcSPhilippe Mathieu-Daudé event_notifier_cleanup(&s->irq_notifier[MSIX_SHARED_IRQ_IDX]); 9254b19e9b8SPhilippe Mathieu-Daudé qemu_vfio_pci_unmap_bar(s->vfio, 0, s->bar0_wo_map, 9264b19e9b8SPhilippe Mathieu-Daudé 0, sizeof(NvmeBar) + NVME_DOORBELL_SIZE); 927bdd6a90aSFam Zheng qemu_vfio_close(s->vfio); 928cc61b074SMax Reitz 929cc61b074SMax Reitz g_free(s->device); 930bdd6a90aSFam Zheng } 931bdd6a90aSFam Zheng 932bdd6a90aSFam Zheng static int nvme_file_open(BlockDriverState *bs, QDict *options, int flags, 933bdd6a90aSFam Zheng Error **errp) 934bdd6a90aSFam Zheng { 935bdd6a90aSFam Zheng const char *device; 936bdd6a90aSFam Zheng QemuOpts *opts; 937bdd6a90aSFam Zheng int namespace; 938bdd6a90aSFam Zheng int ret; 939bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 940bdd6a90aSFam Zheng 941e0dd95e3SMaxim Levitsky bs->supported_write_flags = BDRV_REQ_FUA; 942e0dd95e3SMaxim Levitsky 943bdd6a90aSFam Zheng opts = qemu_opts_create(&runtime_opts, NULL, 0, &error_abort); 944bdd6a90aSFam Zheng qemu_opts_absorb_qdict(opts, options, &error_abort); 945bdd6a90aSFam Zheng device = qemu_opt_get(opts, NVME_BLOCK_OPT_DEVICE); 946bdd6a90aSFam Zheng if (!device) { 947bdd6a90aSFam Zheng error_setg(errp, "'" NVME_BLOCK_OPT_DEVICE "' option is required"); 948bdd6a90aSFam Zheng qemu_opts_del(opts); 949bdd6a90aSFam Zheng return -EINVAL; 950bdd6a90aSFam Zheng } 951bdd6a90aSFam Zheng 952bdd6a90aSFam Zheng namespace = qemu_opt_get_number(opts, NVME_BLOCK_OPT_NAMESPACE, 1); 953bdd6a90aSFam Zheng ret = nvme_init(bs, device, namespace, errp); 954bdd6a90aSFam Zheng qemu_opts_del(opts); 955bdd6a90aSFam Zheng if (ret) { 956bdd6a90aSFam Zheng goto fail; 957bdd6a90aSFam Zheng } 958bdd6a90aSFam Zheng if (flags & BDRV_O_NOCACHE) { 959bdd6a90aSFam Zheng if (!s->write_cache_supported) { 960bdd6a90aSFam Zheng error_setg(errp, 961bdd6a90aSFam Zheng "NVMe controller doesn't support write cache configuration"); 962bdd6a90aSFam Zheng ret = -EINVAL; 963bdd6a90aSFam Zheng } else { 964bdd6a90aSFam Zheng ret = nvme_enable_disable_write_cache(bs, !(flags & BDRV_O_NOCACHE), 965bdd6a90aSFam Zheng errp); 966bdd6a90aSFam Zheng } 967bdd6a90aSFam Zheng if (ret) { 968bdd6a90aSFam Zheng goto fail; 969bdd6a90aSFam Zheng } 970bdd6a90aSFam Zheng } 971bdd6a90aSFam Zheng return 0; 972bdd6a90aSFam Zheng fail: 973bdd6a90aSFam Zheng nvme_close(bs); 974bdd6a90aSFam Zheng return ret; 975bdd6a90aSFam Zheng } 976bdd6a90aSFam Zheng 977bdd6a90aSFam Zheng static int64_t nvme_getlength(BlockDriverState *bs) 978bdd6a90aSFam Zheng { 979bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 980118d1b6aSMaxim Levitsky return s->nsze << s->blkshift; 981118d1b6aSMaxim Levitsky } 982bdd6a90aSFam Zheng 9831120407bSMax Reitz static uint32_t nvme_get_blocksize(BlockDriverState *bs) 984118d1b6aSMaxim Levitsky { 985118d1b6aSMaxim Levitsky BDRVNVMeState *s = bs->opaque; 9861120407bSMax Reitz assert(s->blkshift >= BDRV_SECTOR_BITS && s->blkshift <= 12); 9871120407bSMax Reitz return UINT32_C(1) << s->blkshift; 988118d1b6aSMaxim Levitsky } 989118d1b6aSMaxim Levitsky 990118d1b6aSMaxim Levitsky static int nvme_probe_blocksizes(BlockDriverState *bs, BlockSizes *bsz) 991118d1b6aSMaxim Levitsky { 9921120407bSMax Reitz uint32_t blocksize = nvme_get_blocksize(bs); 993118d1b6aSMaxim Levitsky bsz->phys = blocksize; 994118d1b6aSMaxim Levitsky bsz->log = blocksize; 995118d1b6aSMaxim Levitsky return 0; 996bdd6a90aSFam Zheng } 997bdd6a90aSFam Zheng 998bdd6a90aSFam Zheng /* Called with s->dma_map_lock */ 999bdd6a90aSFam Zheng static coroutine_fn int nvme_cmd_unmap_qiov(BlockDriverState *bs, 1000bdd6a90aSFam Zheng QEMUIOVector *qiov) 1001bdd6a90aSFam Zheng { 1002bdd6a90aSFam Zheng int r = 0; 1003bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1004bdd6a90aSFam Zheng 1005bdd6a90aSFam Zheng s->dma_map_count -= qiov->size; 1006bdd6a90aSFam Zheng if (!s->dma_map_count && !qemu_co_queue_empty(&s->dma_flush_queue)) { 1007bdd6a90aSFam Zheng r = qemu_vfio_dma_reset_temporary(s->vfio); 1008bdd6a90aSFam Zheng if (!r) { 1009bdd6a90aSFam Zheng qemu_co_queue_restart_all(&s->dma_flush_queue); 1010bdd6a90aSFam Zheng } 1011bdd6a90aSFam Zheng } 1012bdd6a90aSFam Zheng return r; 1013bdd6a90aSFam Zheng } 1014bdd6a90aSFam Zheng 1015bdd6a90aSFam Zheng /* Called with s->dma_map_lock */ 1016bdd6a90aSFam Zheng static coroutine_fn int nvme_cmd_map_qiov(BlockDriverState *bs, NvmeCmd *cmd, 1017bdd6a90aSFam Zheng NVMeRequest *req, QEMUIOVector *qiov) 1018bdd6a90aSFam Zheng { 1019bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1020bdd6a90aSFam Zheng uint64_t *pagelist = req->prp_list_page; 1021bdd6a90aSFam Zheng int i, j, r; 1022bdd6a90aSFam Zheng int entries = 0; 1023bdd6a90aSFam Zheng 1024bdd6a90aSFam Zheng assert(qiov->size); 1025bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(qiov->size, s->page_size)); 1026bdd6a90aSFam Zheng assert(qiov->size / s->page_size <= s->page_size / sizeof(uint64_t)); 1027bdd6a90aSFam Zheng for (i = 0; i < qiov->niov; ++i) { 1028bdd6a90aSFam Zheng bool retry = true; 1029bdd6a90aSFam Zheng uint64_t iova; 10309e13d598SEric Auger size_t len = QEMU_ALIGN_UP(qiov->iov[i].iov_len, 10319e13d598SEric Auger qemu_real_host_page_size); 1032bdd6a90aSFam Zheng try_map: 1033bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, 1034bdd6a90aSFam Zheng qiov->iov[i].iov_base, 10359e13d598SEric Auger len, true, &iova); 103615a730e7SPhilippe Mathieu-Daudé if (r == -ENOSPC) { 103715a730e7SPhilippe Mathieu-Daudé /* 103815a730e7SPhilippe Mathieu-Daudé * In addition to the -ENOMEM error, the VFIO_IOMMU_MAP_DMA 103915a730e7SPhilippe Mathieu-Daudé * ioctl returns -ENOSPC to signal the user exhausted the DMA 104015a730e7SPhilippe Mathieu-Daudé * mappings available for a container since Linux kernel commit 104115a730e7SPhilippe Mathieu-Daudé * 492855939bdb ("vfio/type1: Limit DMA mappings per container", 104215a730e7SPhilippe Mathieu-Daudé * April 2019, see CVE-2019-3882). 104315a730e7SPhilippe Mathieu-Daudé * 104415a730e7SPhilippe Mathieu-Daudé * This block driver already handles this error path by checking 104515a730e7SPhilippe Mathieu-Daudé * for the -ENOMEM error, so we directly replace -ENOSPC by 104615a730e7SPhilippe Mathieu-Daudé * -ENOMEM. Beside, -ENOSPC has a specific meaning for blockdev 104715a730e7SPhilippe Mathieu-Daudé * coroutines: it triggers BLOCKDEV_ON_ERROR_ENOSPC and 104815a730e7SPhilippe Mathieu-Daudé * BLOCK_ERROR_ACTION_STOP which stops the VM, asking the operator 104915a730e7SPhilippe Mathieu-Daudé * to add more storage to the blockdev. Not something we can do 105015a730e7SPhilippe Mathieu-Daudé * easily with an IOMMU :) 105115a730e7SPhilippe Mathieu-Daudé */ 105215a730e7SPhilippe Mathieu-Daudé r = -ENOMEM; 105315a730e7SPhilippe Mathieu-Daudé } 1054bdd6a90aSFam Zheng if (r == -ENOMEM && retry) { 105515a730e7SPhilippe Mathieu-Daudé /* 105615a730e7SPhilippe Mathieu-Daudé * We exhausted the DMA mappings available for our container: 105715a730e7SPhilippe Mathieu-Daudé * recycle the volatile IOVA mappings. 105815a730e7SPhilippe Mathieu-Daudé */ 1059bdd6a90aSFam Zheng retry = false; 1060bdd6a90aSFam Zheng trace_nvme_dma_flush_queue_wait(s); 1061bdd6a90aSFam Zheng if (s->dma_map_count) { 1062bdd6a90aSFam Zheng trace_nvme_dma_map_flush(s); 1063bdd6a90aSFam Zheng qemu_co_queue_wait(&s->dma_flush_queue, &s->dma_map_lock); 1064bdd6a90aSFam Zheng } else { 1065bdd6a90aSFam Zheng r = qemu_vfio_dma_reset_temporary(s->vfio); 1066bdd6a90aSFam Zheng if (r) { 1067bdd6a90aSFam Zheng goto fail; 1068bdd6a90aSFam Zheng } 1069bdd6a90aSFam Zheng } 1070bdd6a90aSFam Zheng goto try_map; 1071bdd6a90aSFam Zheng } 1072bdd6a90aSFam Zheng if (r) { 1073bdd6a90aSFam Zheng goto fail; 1074bdd6a90aSFam Zheng } 1075bdd6a90aSFam Zheng 1076bdd6a90aSFam Zheng for (j = 0; j < qiov->iov[i].iov_len / s->page_size; j++) { 10772916405aSLi Feng pagelist[entries++] = cpu_to_le64(iova + j * s->page_size); 1078bdd6a90aSFam Zheng } 1079bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov_iov(s, i, qiov->iov[i].iov_base, 1080bdd6a90aSFam Zheng qiov->iov[i].iov_len / s->page_size); 1081bdd6a90aSFam Zheng } 1082bdd6a90aSFam Zheng 1083bdd6a90aSFam Zheng s->dma_map_count += qiov->size; 1084bdd6a90aSFam Zheng 1085bdd6a90aSFam Zheng assert(entries <= s->page_size / sizeof(uint64_t)); 1086bdd6a90aSFam Zheng switch (entries) { 1087bdd6a90aSFam Zheng case 0: 1088bdd6a90aSFam Zheng abort(); 1089bdd6a90aSFam Zheng case 1: 1090c26f2173SKlaus Jensen cmd->dptr.prp1 = pagelist[0]; 1091c26f2173SKlaus Jensen cmd->dptr.prp2 = 0; 1092bdd6a90aSFam Zheng break; 1093bdd6a90aSFam Zheng case 2: 1094c26f2173SKlaus Jensen cmd->dptr.prp1 = pagelist[0]; 1095c26f2173SKlaus Jensen cmd->dptr.prp2 = pagelist[1]; 1096bdd6a90aSFam Zheng break; 1097bdd6a90aSFam Zheng default: 1098c26f2173SKlaus Jensen cmd->dptr.prp1 = pagelist[0]; 1099c26f2173SKlaus Jensen cmd->dptr.prp2 = cpu_to_le64(req->prp_list_iova + sizeof(uint64_t)); 1100bdd6a90aSFam Zheng break; 1101bdd6a90aSFam Zheng } 1102bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov(s, cmd, req, qiov, entries); 1103bdd6a90aSFam Zheng for (i = 0; i < entries; ++i) { 1104bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov_pages(s, i, pagelist[i]); 1105bdd6a90aSFam Zheng } 1106bdd6a90aSFam Zheng return 0; 1107bdd6a90aSFam Zheng fail: 1108bdd6a90aSFam Zheng /* No need to unmap [0 - i) iovs even if we've failed, since we don't 1109bdd6a90aSFam Zheng * increment s->dma_map_count. This is okay for fixed mapping memory areas 1110bdd6a90aSFam Zheng * because they are already mapped before calling this function; for 1111bdd6a90aSFam Zheng * temporary mappings, a later nvme_cmd_(un)map_qiov will reclaim by 1112bdd6a90aSFam Zheng * calling qemu_vfio_dma_reset_temporary when necessary. */ 1113bdd6a90aSFam Zheng return r; 1114bdd6a90aSFam Zheng } 1115bdd6a90aSFam Zheng 1116bdd6a90aSFam Zheng typedef struct { 1117bdd6a90aSFam Zheng Coroutine *co; 1118bdd6a90aSFam Zheng int ret; 1119bdd6a90aSFam Zheng AioContext *ctx; 1120bdd6a90aSFam Zheng } NVMeCoData; 1121bdd6a90aSFam Zheng 1122bdd6a90aSFam Zheng static void nvme_rw_cb_bh(void *opaque) 1123bdd6a90aSFam Zheng { 1124bdd6a90aSFam Zheng NVMeCoData *data = opaque; 1125bdd6a90aSFam Zheng qemu_coroutine_enter(data->co); 1126bdd6a90aSFam Zheng } 1127bdd6a90aSFam Zheng 1128bdd6a90aSFam Zheng static void nvme_rw_cb(void *opaque, int ret) 1129bdd6a90aSFam Zheng { 1130bdd6a90aSFam Zheng NVMeCoData *data = opaque; 1131bdd6a90aSFam Zheng data->ret = ret; 1132bdd6a90aSFam Zheng if (!data->co) { 1133bdd6a90aSFam Zheng /* The rw coroutine hasn't yielded, don't try to enter. */ 1134bdd6a90aSFam Zheng return; 1135bdd6a90aSFam Zheng } 1136e4ec5ad4SPavel Dovgalyuk replay_bh_schedule_oneshot_event(data->ctx, nvme_rw_cb_bh, data); 1137bdd6a90aSFam Zheng } 1138bdd6a90aSFam Zheng 1139bdd6a90aSFam Zheng static coroutine_fn int nvme_co_prw_aligned(BlockDriverState *bs, 1140bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 1141bdd6a90aSFam Zheng QEMUIOVector *qiov, 1142bdd6a90aSFam Zheng bool is_write, 1143bdd6a90aSFam Zheng int flags) 1144bdd6a90aSFam Zheng { 1145bdd6a90aSFam Zheng int r; 1146bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 114773159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1148bdd6a90aSFam Zheng NVMeRequest *req; 1149118d1b6aSMaxim Levitsky 1150118d1b6aSMaxim Levitsky uint32_t cdw12 = (((bytes >> s->blkshift) - 1) & 0xFFFF) | 1151bdd6a90aSFam Zheng (flags & BDRV_REQ_FUA ? 1 << 30 : 0); 1152bdd6a90aSFam Zheng NvmeCmd cmd = { 1153bdd6a90aSFam Zheng .opcode = is_write ? NVME_CMD_WRITE : NVME_CMD_READ, 1154bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 1155118d1b6aSMaxim Levitsky .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF), 1156118d1b6aSMaxim Levitsky .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF), 1157bdd6a90aSFam Zheng .cdw12 = cpu_to_le32(cdw12), 1158bdd6a90aSFam Zheng }; 1159bdd6a90aSFam Zheng NVMeCoData data = { 1160bdd6a90aSFam Zheng .ctx = bdrv_get_aio_context(bs), 1161bdd6a90aSFam Zheng .ret = -EINPROGRESS, 1162bdd6a90aSFam Zheng }; 1163bdd6a90aSFam Zheng 1164bdd6a90aSFam Zheng trace_nvme_prw_aligned(s, is_write, offset, bytes, flags, qiov->niov); 11651b539bd6SPhilippe Mathieu-Daudé assert(s->queue_count > 1); 1166bdd6a90aSFam Zheng req = nvme_get_free_req(ioq); 1167bdd6a90aSFam Zheng assert(req); 1168bdd6a90aSFam Zheng 1169bdd6a90aSFam Zheng qemu_co_mutex_lock(&s->dma_map_lock); 1170bdd6a90aSFam Zheng r = nvme_cmd_map_qiov(bs, &cmd, req, qiov); 1171bdd6a90aSFam Zheng qemu_co_mutex_unlock(&s->dma_map_lock); 1172bdd6a90aSFam Zheng if (r) { 1173b75fd5f5SStefan Hajnoczi nvme_put_free_req_and_wake(ioq, req); 1174bdd6a90aSFam Zheng return r; 1175bdd6a90aSFam Zheng } 1176b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1177bdd6a90aSFam Zheng 1178bdd6a90aSFam Zheng data.co = qemu_coroutine_self(); 1179bdd6a90aSFam Zheng while (data.ret == -EINPROGRESS) { 1180bdd6a90aSFam Zheng qemu_coroutine_yield(); 1181bdd6a90aSFam Zheng } 1182bdd6a90aSFam Zheng 1183bdd6a90aSFam Zheng qemu_co_mutex_lock(&s->dma_map_lock); 1184bdd6a90aSFam Zheng r = nvme_cmd_unmap_qiov(bs, qiov); 1185bdd6a90aSFam Zheng qemu_co_mutex_unlock(&s->dma_map_lock); 1186bdd6a90aSFam Zheng if (r) { 1187bdd6a90aSFam Zheng return r; 1188bdd6a90aSFam Zheng } 1189bdd6a90aSFam Zheng 1190bdd6a90aSFam Zheng trace_nvme_rw_done(s, is_write, offset, bytes, data.ret); 1191bdd6a90aSFam Zheng return data.ret; 1192bdd6a90aSFam Zheng } 1193bdd6a90aSFam Zheng 1194bdd6a90aSFam Zheng static inline bool nvme_qiov_aligned(BlockDriverState *bs, 1195bdd6a90aSFam Zheng const QEMUIOVector *qiov) 1196bdd6a90aSFam Zheng { 1197bdd6a90aSFam Zheng int i; 1198bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1199bdd6a90aSFam Zheng 1200bdd6a90aSFam Zheng for (i = 0; i < qiov->niov; ++i) { 12019e13d598SEric Auger if (!QEMU_PTR_IS_ALIGNED(qiov->iov[i].iov_base, 12029e13d598SEric Auger qemu_real_host_page_size) || 12039e13d598SEric Auger !QEMU_IS_ALIGNED(qiov->iov[i].iov_len, qemu_real_host_page_size)) { 1204bdd6a90aSFam Zheng trace_nvme_qiov_unaligned(qiov, i, qiov->iov[i].iov_base, 1205bdd6a90aSFam Zheng qiov->iov[i].iov_len, s->page_size); 1206bdd6a90aSFam Zheng return false; 1207bdd6a90aSFam Zheng } 1208bdd6a90aSFam Zheng } 1209bdd6a90aSFam Zheng return true; 1210bdd6a90aSFam Zheng } 1211bdd6a90aSFam Zheng 1212bdd6a90aSFam Zheng static int nvme_co_prw(BlockDriverState *bs, uint64_t offset, uint64_t bytes, 1213bdd6a90aSFam Zheng QEMUIOVector *qiov, bool is_write, int flags) 1214bdd6a90aSFam Zheng { 1215bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1216bdd6a90aSFam Zheng int r; 1217bdd6a90aSFam Zheng uint8_t *buf = NULL; 1218bdd6a90aSFam Zheng QEMUIOVector local_qiov; 12199e13d598SEric Auger size_t len = QEMU_ALIGN_UP(bytes, qemu_real_host_page_size); 1220bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(offset, s->page_size)); 1221bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(bytes, s->page_size)); 1222bdd6a90aSFam Zheng assert(bytes <= s->max_transfer); 1223bdd6a90aSFam Zheng if (nvme_qiov_aligned(bs, qiov)) { 1224f25e7ab2SPhilippe Mathieu-Daudé s->stats.aligned_accesses++; 1225bdd6a90aSFam Zheng return nvme_co_prw_aligned(bs, offset, bytes, qiov, is_write, flags); 1226bdd6a90aSFam Zheng } 1227f25e7ab2SPhilippe Mathieu-Daudé s->stats.unaligned_accesses++; 1228bdd6a90aSFam Zheng trace_nvme_prw_buffered(s, offset, bytes, qiov->niov, is_write); 12299e13d598SEric Auger buf = qemu_try_memalign(qemu_real_host_page_size, len); 1230bdd6a90aSFam Zheng 1231bdd6a90aSFam Zheng if (!buf) { 1232bdd6a90aSFam Zheng return -ENOMEM; 1233bdd6a90aSFam Zheng } 1234bdd6a90aSFam Zheng qemu_iovec_init(&local_qiov, 1); 1235bdd6a90aSFam Zheng if (is_write) { 1236bdd6a90aSFam Zheng qemu_iovec_to_buf(qiov, 0, buf, bytes); 1237bdd6a90aSFam Zheng } 1238bdd6a90aSFam Zheng qemu_iovec_add(&local_qiov, buf, bytes); 1239bdd6a90aSFam Zheng r = nvme_co_prw_aligned(bs, offset, bytes, &local_qiov, is_write, flags); 1240bdd6a90aSFam Zheng qemu_iovec_destroy(&local_qiov); 1241bdd6a90aSFam Zheng if (!r && !is_write) { 1242bdd6a90aSFam Zheng qemu_iovec_from_buf(qiov, 0, buf, bytes); 1243bdd6a90aSFam Zheng } 1244bdd6a90aSFam Zheng qemu_vfree(buf); 1245bdd6a90aSFam Zheng return r; 1246bdd6a90aSFam Zheng } 1247bdd6a90aSFam Zheng 1248bdd6a90aSFam Zheng static coroutine_fn int nvme_co_preadv(BlockDriverState *bs, 1249bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 1250bdd6a90aSFam Zheng QEMUIOVector *qiov, int flags) 1251bdd6a90aSFam Zheng { 1252bdd6a90aSFam Zheng return nvme_co_prw(bs, offset, bytes, qiov, false, flags); 1253bdd6a90aSFam Zheng } 1254bdd6a90aSFam Zheng 1255bdd6a90aSFam Zheng static coroutine_fn int nvme_co_pwritev(BlockDriverState *bs, 1256bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 1257bdd6a90aSFam Zheng QEMUIOVector *qiov, int flags) 1258bdd6a90aSFam Zheng { 1259bdd6a90aSFam Zheng return nvme_co_prw(bs, offset, bytes, qiov, true, flags); 1260bdd6a90aSFam Zheng } 1261bdd6a90aSFam Zheng 1262bdd6a90aSFam Zheng static coroutine_fn int nvme_co_flush(BlockDriverState *bs) 1263bdd6a90aSFam Zheng { 1264bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 126573159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1266bdd6a90aSFam Zheng NVMeRequest *req; 1267bdd6a90aSFam Zheng NvmeCmd cmd = { 1268bdd6a90aSFam Zheng .opcode = NVME_CMD_FLUSH, 1269bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 1270bdd6a90aSFam Zheng }; 1271bdd6a90aSFam Zheng NVMeCoData data = { 1272bdd6a90aSFam Zheng .ctx = bdrv_get_aio_context(bs), 1273bdd6a90aSFam Zheng .ret = -EINPROGRESS, 1274bdd6a90aSFam Zheng }; 1275bdd6a90aSFam Zheng 12761b539bd6SPhilippe Mathieu-Daudé assert(s->queue_count > 1); 1277bdd6a90aSFam Zheng req = nvme_get_free_req(ioq); 1278bdd6a90aSFam Zheng assert(req); 1279b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1280bdd6a90aSFam Zheng 1281bdd6a90aSFam Zheng data.co = qemu_coroutine_self(); 1282bdd6a90aSFam Zheng if (data.ret == -EINPROGRESS) { 1283bdd6a90aSFam Zheng qemu_coroutine_yield(); 1284bdd6a90aSFam Zheng } 1285bdd6a90aSFam Zheng 1286bdd6a90aSFam Zheng return data.ret; 1287bdd6a90aSFam Zheng } 1288bdd6a90aSFam Zheng 1289bdd6a90aSFam Zheng 1290e0dd95e3SMaxim Levitsky static coroutine_fn int nvme_co_pwrite_zeroes(BlockDriverState *bs, 1291e0dd95e3SMaxim Levitsky int64_t offset, 1292e0dd95e3SMaxim Levitsky int bytes, 1293e0dd95e3SMaxim Levitsky BdrvRequestFlags flags) 1294e0dd95e3SMaxim Levitsky { 1295e0dd95e3SMaxim Levitsky BDRVNVMeState *s = bs->opaque; 129673159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1297e0dd95e3SMaxim Levitsky NVMeRequest *req; 1298e0dd95e3SMaxim Levitsky 1299e0dd95e3SMaxim Levitsky uint32_t cdw12 = ((bytes >> s->blkshift) - 1) & 0xFFFF; 1300e0dd95e3SMaxim Levitsky 1301e0dd95e3SMaxim Levitsky if (!s->supports_write_zeroes) { 1302e0dd95e3SMaxim Levitsky return -ENOTSUP; 1303e0dd95e3SMaxim Levitsky } 1304e0dd95e3SMaxim Levitsky 1305e0dd95e3SMaxim Levitsky NvmeCmd cmd = { 130669265150SKlaus Jensen .opcode = NVME_CMD_WRITE_ZEROES, 1307e0dd95e3SMaxim Levitsky .nsid = cpu_to_le32(s->nsid), 1308e0dd95e3SMaxim Levitsky .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF), 1309e0dd95e3SMaxim Levitsky .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF), 1310e0dd95e3SMaxim Levitsky }; 1311e0dd95e3SMaxim Levitsky 1312e0dd95e3SMaxim Levitsky NVMeCoData data = { 1313e0dd95e3SMaxim Levitsky .ctx = bdrv_get_aio_context(bs), 1314e0dd95e3SMaxim Levitsky .ret = -EINPROGRESS, 1315e0dd95e3SMaxim Levitsky }; 1316e0dd95e3SMaxim Levitsky 1317e0dd95e3SMaxim Levitsky if (flags & BDRV_REQ_MAY_UNMAP) { 1318e0dd95e3SMaxim Levitsky cdw12 |= (1 << 25); 1319e0dd95e3SMaxim Levitsky } 1320e0dd95e3SMaxim Levitsky 1321e0dd95e3SMaxim Levitsky if (flags & BDRV_REQ_FUA) { 1322e0dd95e3SMaxim Levitsky cdw12 |= (1 << 30); 1323e0dd95e3SMaxim Levitsky } 1324e0dd95e3SMaxim Levitsky 1325e0dd95e3SMaxim Levitsky cmd.cdw12 = cpu_to_le32(cdw12); 1326e0dd95e3SMaxim Levitsky 1327e0dd95e3SMaxim Levitsky trace_nvme_write_zeroes(s, offset, bytes, flags); 13281b539bd6SPhilippe Mathieu-Daudé assert(s->queue_count > 1); 1329e0dd95e3SMaxim Levitsky req = nvme_get_free_req(ioq); 1330e0dd95e3SMaxim Levitsky assert(req); 1331e0dd95e3SMaxim Levitsky 1332b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1333e0dd95e3SMaxim Levitsky 1334e0dd95e3SMaxim Levitsky data.co = qemu_coroutine_self(); 1335e0dd95e3SMaxim Levitsky while (data.ret == -EINPROGRESS) { 1336e0dd95e3SMaxim Levitsky qemu_coroutine_yield(); 1337e0dd95e3SMaxim Levitsky } 1338e0dd95e3SMaxim Levitsky 1339e0dd95e3SMaxim Levitsky trace_nvme_rw_done(s, true, offset, bytes, data.ret); 1340e0dd95e3SMaxim Levitsky return data.ret; 1341e0dd95e3SMaxim Levitsky } 1342e0dd95e3SMaxim Levitsky 1343e0dd95e3SMaxim Levitsky 1344e87a09d6SMaxim Levitsky static int coroutine_fn nvme_co_pdiscard(BlockDriverState *bs, 1345e87a09d6SMaxim Levitsky int64_t offset, 1346e87a09d6SMaxim Levitsky int bytes) 1347e87a09d6SMaxim Levitsky { 1348e87a09d6SMaxim Levitsky BDRVNVMeState *s = bs->opaque; 134973159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1350e87a09d6SMaxim Levitsky NVMeRequest *req; 1351e87a09d6SMaxim Levitsky NvmeDsmRange *buf; 1352e87a09d6SMaxim Levitsky QEMUIOVector local_qiov; 1353e87a09d6SMaxim Levitsky int ret; 1354e87a09d6SMaxim Levitsky 1355e87a09d6SMaxim Levitsky NvmeCmd cmd = { 1356e87a09d6SMaxim Levitsky .opcode = NVME_CMD_DSM, 1357e87a09d6SMaxim Levitsky .nsid = cpu_to_le32(s->nsid), 1358e87a09d6SMaxim Levitsky .cdw10 = cpu_to_le32(0), /*number of ranges - 0 based*/ 1359e87a09d6SMaxim Levitsky .cdw11 = cpu_to_le32(1 << 2), /*deallocate bit*/ 1360e87a09d6SMaxim Levitsky }; 1361e87a09d6SMaxim Levitsky 1362e87a09d6SMaxim Levitsky NVMeCoData data = { 1363e87a09d6SMaxim Levitsky .ctx = bdrv_get_aio_context(bs), 1364e87a09d6SMaxim Levitsky .ret = -EINPROGRESS, 1365e87a09d6SMaxim Levitsky }; 1366e87a09d6SMaxim Levitsky 1367e87a09d6SMaxim Levitsky if (!s->supports_discard) { 1368e87a09d6SMaxim Levitsky return -ENOTSUP; 1369e87a09d6SMaxim Levitsky } 1370e87a09d6SMaxim Levitsky 13711b539bd6SPhilippe Mathieu-Daudé assert(s->queue_count > 1); 1372e87a09d6SMaxim Levitsky 137338e1f818SPhilippe Mathieu-Daudé buf = qemu_try_memalign(s->page_size, s->page_size); 1374e87a09d6SMaxim Levitsky if (!buf) { 1375e87a09d6SMaxim Levitsky return -ENOMEM; 1376e87a09d6SMaxim Levitsky } 13772ed84693SPhilippe Mathieu-Daudé memset(buf, 0, s->page_size); 1378e87a09d6SMaxim Levitsky buf->nlb = cpu_to_le32(bytes >> s->blkshift); 1379e87a09d6SMaxim Levitsky buf->slba = cpu_to_le64(offset >> s->blkshift); 1380e87a09d6SMaxim Levitsky buf->cattr = 0; 1381e87a09d6SMaxim Levitsky 1382e87a09d6SMaxim Levitsky qemu_iovec_init(&local_qiov, 1); 1383e87a09d6SMaxim Levitsky qemu_iovec_add(&local_qiov, buf, 4096); 1384e87a09d6SMaxim Levitsky 1385e87a09d6SMaxim Levitsky req = nvme_get_free_req(ioq); 1386e87a09d6SMaxim Levitsky assert(req); 1387e87a09d6SMaxim Levitsky 1388e87a09d6SMaxim Levitsky qemu_co_mutex_lock(&s->dma_map_lock); 1389e87a09d6SMaxim Levitsky ret = nvme_cmd_map_qiov(bs, &cmd, req, &local_qiov); 1390e87a09d6SMaxim Levitsky qemu_co_mutex_unlock(&s->dma_map_lock); 1391e87a09d6SMaxim Levitsky 1392e87a09d6SMaxim Levitsky if (ret) { 1393b75fd5f5SStefan Hajnoczi nvme_put_free_req_and_wake(ioq, req); 1394e87a09d6SMaxim Levitsky goto out; 1395e87a09d6SMaxim Levitsky } 1396e87a09d6SMaxim Levitsky 1397e87a09d6SMaxim Levitsky trace_nvme_dsm(s, offset, bytes); 1398e87a09d6SMaxim Levitsky 1399b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1400e87a09d6SMaxim Levitsky 1401e87a09d6SMaxim Levitsky data.co = qemu_coroutine_self(); 1402e87a09d6SMaxim Levitsky while (data.ret == -EINPROGRESS) { 1403e87a09d6SMaxim Levitsky qemu_coroutine_yield(); 1404e87a09d6SMaxim Levitsky } 1405e87a09d6SMaxim Levitsky 1406e87a09d6SMaxim Levitsky qemu_co_mutex_lock(&s->dma_map_lock); 1407e87a09d6SMaxim Levitsky ret = nvme_cmd_unmap_qiov(bs, &local_qiov); 1408e87a09d6SMaxim Levitsky qemu_co_mutex_unlock(&s->dma_map_lock); 1409e87a09d6SMaxim Levitsky 1410e87a09d6SMaxim Levitsky if (ret) { 1411e87a09d6SMaxim Levitsky goto out; 1412e87a09d6SMaxim Levitsky } 1413e87a09d6SMaxim Levitsky 1414e87a09d6SMaxim Levitsky ret = data.ret; 1415e87a09d6SMaxim Levitsky trace_nvme_dsm_done(s, offset, bytes, ret); 1416e87a09d6SMaxim Levitsky out: 1417e87a09d6SMaxim Levitsky qemu_iovec_destroy(&local_qiov); 1418e87a09d6SMaxim Levitsky qemu_vfree(buf); 1419e87a09d6SMaxim Levitsky return ret; 1420e87a09d6SMaxim Levitsky 1421e87a09d6SMaxim Levitsky } 1422e87a09d6SMaxim Levitsky 1423c8807c5eSPhilippe Mathieu-Daudé static int coroutine_fn nvme_co_truncate(BlockDriverState *bs, int64_t offset, 1424c8807c5eSPhilippe Mathieu-Daudé bool exact, PreallocMode prealloc, 1425c8807c5eSPhilippe Mathieu-Daudé BdrvRequestFlags flags, Error **errp) 1426c8807c5eSPhilippe Mathieu-Daudé { 1427c8807c5eSPhilippe Mathieu-Daudé int64_t cur_length; 1428c8807c5eSPhilippe Mathieu-Daudé 1429c8807c5eSPhilippe Mathieu-Daudé if (prealloc != PREALLOC_MODE_OFF) { 1430c8807c5eSPhilippe Mathieu-Daudé error_setg(errp, "Unsupported preallocation mode '%s'", 1431c8807c5eSPhilippe Mathieu-Daudé PreallocMode_str(prealloc)); 1432c8807c5eSPhilippe Mathieu-Daudé return -ENOTSUP; 1433c8807c5eSPhilippe Mathieu-Daudé } 1434c8807c5eSPhilippe Mathieu-Daudé 1435c8807c5eSPhilippe Mathieu-Daudé cur_length = nvme_getlength(bs); 1436c8807c5eSPhilippe Mathieu-Daudé if (offset != cur_length && exact) { 1437c8807c5eSPhilippe Mathieu-Daudé error_setg(errp, "Cannot resize NVMe devices"); 1438c8807c5eSPhilippe Mathieu-Daudé return -ENOTSUP; 1439c8807c5eSPhilippe Mathieu-Daudé } else if (offset > cur_length) { 1440c8807c5eSPhilippe Mathieu-Daudé error_setg(errp, "Cannot grow NVMe devices"); 1441c8807c5eSPhilippe Mathieu-Daudé return -EINVAL; 1442c8807c5eSPhilippe Mathieu-Daudé } 1443c8807c5eSPhilippe Mathieu-Daudé 1444c8807c5eSPhilippe Mathieu-Daudé return 0; 1445c8807c5eSPhilippe Mathieu-Daudé } 1446e87a09d6SMaxim Levitsky 1447bdd6a90aSFam Zheng static int nvme_reopen_prepare(BDRVReopenState *reopen_state, 1448bdd6a90aSFam Zheng BlockReopenQueue *queue, Error **errp) 1449bdd6a90aSFam Zheng { 1450bdd6a90aSFam Zheng return 0; 1451bdd6a90aSFam Zheng } 1452bdd6a90aSFam Zheng 1453998b3a1eSMax Reitz static void nvme_refresh_filename(BlockDriverState *bs) 1454bdd6a90aSFam Zheng { 1455cc61b074SMax Reitz BDRVNVMeState *s = bs->opaque; 1456bdd6a90aSFam Zheng 1457cc61b074SMax Reitz snprintf(bs->exact_filename, sizeof(bs->exact_filename), "nvme://%s/%i", 1458cc61b074SMax Reitz s->device, s->nsid); 1459bdd6a90aSFam Zheng } 1460bdd6a90aSFam Zheng 1461bdd6a90aSFam Zheng static void nvme_refresh_limits(BlockDriverState *bs, Error **errp) 1462bdd6a90aSFam Zheng { 1463bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1464bdd6a90aSFam Zheng 1465bdd6a90aSFam Zheng bs->bl.opt_mem_alignment = s->page_size; 1466bdd6a90aSFam Zheng bs->bl.request_alignment = s->page_size; 1467bdd6a90aSFam Zheng bs->bl.max_transfer = s->max_transfer; 1468bdd6a90aSFam Zheng } 1469bdd6a90aSFam Zheng 1470bdd6a90aSFam Zheng static void nvme_detach_aio_context(BlockDriverState *bs) 1471bdd6a90aSFam Zheng { 1472bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1473bdd6a90aSFam Zheng 14741b539bd6SPhilippe Mathieu-Daudé for (unsigned i = 0; i < s->queue_count; i++) { 14757838c67fSStefan Hajnoczi NVMeQueuePair *q = s->queues[i]; 14767838c67fSStefan Hajnoczi 14777838c67fSStefan Hajnoczi qemu_bh_delete(q->completion_bh); 14787838c67fSStefan Hajnoczi q->completion_bh = NULL; 14797838c67fSStefan Hajnoczi } 14807838c67fSStefan Hajnoczi 1481b111b3fcSPhilippe Mathieu-Daudé aio_set_event_notifier(bdrv_get_aio_context(bs), 1482b111b3fcSPhilippe Mathieu-Daudé &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 1483bdd6a90aSFam Zheng false, NULL, NULL); 1484bdd6a90aSFam Zheng } 1485bdd6a90aSFam Zheng 1486bdd6a90aSFam Zheng static void nvme_attach_aio_context(BlockDriverState *bs, 1487bdd6a90aSFam Zheng AioContext *new_context) 1488bdd6a90aSFam Zheng { 1489bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1490bdd6a90aSFam Zheng 1491bdd6a90aSFam Zheng s->aio_context = new_context; 1492b111b3fcSPhilippe Mathieu-Daudé aio_set_event_notifier(new_context, &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 1493bdd6a90aSFam Zheng false, nvme_handle_event, nvme_poll_cb); 14947838c67fSStefan Hajnoczi 14951b539bd6SPhilippe Mathieu-Daudé for (unsigned i = 0; i < s->queue_count; i++) { 14967838c67fSStefan Hajnoczi NVMeQueuePair *q = s->queues[i]; 14977838c67fSStefan Hajnoczi 14987838c67fSStefan Hajnoczi q->completion_bh = 14997838c67fSStefan Hajnoczi aio_bh_new(new_context, nvme_process_completion_bh, q); 15007838c67fSStefan Hajnoczi } 1501bdd6a90aSFam Zheng } 1502bdd6a90aSFam Zheng 1503bdd6a90aSFam Zheng static void nvme_aio_plug(BlockDriverState *bs) 1504bdd6a90aSFam Zheng { 1505bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 15062f0d8947SPaolo Bonzini assert(!s->plugged); 15072f0d8947SPaolo Bonzini s->plugged = true; 1508bdd6a90aSFam Zheng } 1509bdd6a90aSFam Zheng 1510bdd6a90aSFam Zheng static void nvme_aio_unplug(BlockDriverState *bs) 1511bdd6a90aSFam Zheng { 1512bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1513bdd6a90aSFam Zheng assert(s->plugged); 15142f0d8947SPaolo Bonzini s->plugged = false; 15151b539bd6SPhilippe Mathieu-Daudé for (unsigned i = INDEX_IO(0); i < s->queue_count; i++) { 1516bdd6a90aSFam Zheng NVMeQueuePair *q = s->queues[i]; 1517bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 1518b75fd5f5SStefan Hajnoczi nvme_kick(q); 1519b75fd5f5SStefan Hajnoczi nvme_process_completion(q); 1520bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 1521bdd6a90aSFam Zheng } 1522bdd6a90aSFam Zheng } 1523bdd6a90aSFam Zheng 15249ed61612SFam Zheng static void nvme_register_buf(BlockDriverState *bs, void *host, size_t size) 15259ed61612SFam Zheng { 15269ed61612SFam Zheng int ret; 15279ed61612SFam Zheng BDRVNVMeState *s = bs->opaque; 15289ed61612SFam Zheng 15299ed61612SFam Zheng ret = qemu_vfio_dma_map(s->vfio, host, size, false, NULL); 15309ed61612SFam Zheng if (ret) { 15319ed61612SFam Zheng /* FIXME: we may run out of IOVA addresses after repeated 15329ed61612SFam Zheng * bdrv_register_buf/bdrv_unregister_buf, because nvme_vfio_dma_unmap 15339ed61612SFam Zheng * doesn't reclaim addresses for fixed mappings. */ 15349ed61612SFam Zheng error_report("nvme_register_buf failed: %s", strerror(-ret)); 15359ed61612SFam Zheng } 15369ed61612SFam Zheng } 15379ed61612SFam Zheng 15389ed61612SFam Zheng static void nvme_unregister_buf(BlockDriverState *bs, void *host) 15399ed61612SFam Zheng { 15409ed61612SFam Zheng BDRVNVMeState *s = bs->opaque; 15419ed61612SFam Zheng 15429ed61612SFam Zheng qemu_vfio_dma_unmap(s->vfio, host); 15439ed61612SFam Zheng } 15449ed61612SFam Zheng 1545f25e7ab2SPhilippe Mathieu-Daudé static BlockStatsSpecific *nvme_get_specific_stats(BlockDriverState *bs) 1546f25e7ab2SPhilippe Mathieu-Daudé { 1547f25e7ab2SPhilippe Mathieu-Daudé BlockStatsSpecific *stats = g_new(BlockStatsSpecific, 1); 1548f25e7ab2SPhilippe Mathieu-Daudé BDRVNVMeState *s = bs->opaque; 1549f25e7ab2SPhilippe Mathieu-Daudé 1550f25e7ab2SPhilippe Mathieu-Daudé stats->driver = BLOCKDEV_DRIVER_NVME; 1551f25e7ab2SPhilippe Mathieu-Daudé stats->u.nvme = (BlockStatsSpecificNvme) { 1552f25e7ab2SPhilippe Mathieu-Daudé .completion_errors = s->stats.completion_errors, 1553f25e7ab2SPhilippe Mathieu-Daudé .aligned_accesses = s->stats.aligned_accesses, 1554f25e7ab2SPhilippe Mathieu-Daudé .unaligned_accesses = s->stats.unaligned_accesses, 1555f25e7ab2SPhilippe Mathieu-Daudé }; 1556f25e7ab2SPhilippe Mathieu-Daudé 1557f25e7ab2SPhilippe Mathieu-Daudé return stats; 1558f25e7ab2SPhilippe Mathieu-Daudé } 1559f25e7ab2SPhilippe Mathieu-Daudé 15602654267cSMax Reitz static const char *const nvme_strong_runtime_opts[] = { 15612654267cSMax Reitz NVME_BLOCK_OPT_DEVICE, 15622654267cSMax Reitz NVME_BLOCK_OPT_NAMESPACE, 15632654267cSMax Reitz 15642654267cSMax Reitz NULL 15652654267cSMax Reitz }; 15662654267cSMax Reitz 1567bdd6a90aSFam Zheng static BlockDriver bdrv_nvme = { 1568bdd6a90aSFam Zheng .format_name = "nvme", 1569bdd6a90aSFam Zheng .protocol_name = "nvme", 1570bdd6a90aSFam Zheng .instance_size = sizeof(BDRVNVMeState), 1571bdd6a90aSFam Zheng 15725a5e7f8cSMaxim Levitsky .bdrv_co_create_opts = bdrv_co_create_opts_simple, 15735a5e7f8cSMaxim Levitsky .create_opts = &bdrv_create_opts_simple, 15745a5e7f8cSMaxim Levitsky 1575bdd6a90aSFam Zheng .bdrv_parse_filename = nvme_parse_filename, 1576bdd6a90aSFam Zheng .bdrv_file_open = nvme_file_open, 1577bdd6a90aSFam Zheng .bdrv_close = nvme_close, 1578bdd6a90aSFam Zheng .bdrv_getlength = nvme_getlength, 1579118d1b6aSMaxim Levitsky .bdrv_probe_blocksizes = nvme_probe_blocksizes, 1580c8807c5eSPhilippe Mathieu-Daudé .bdrv_co_truncate = nvme_co_truncate, 1581bdd6a90aSFam Zheng 1582bdd6a90aSFam Zheng .bdrv_co_preadv = nvme_co_preadv, 1583bdd6a90aSFam Zheng .bdrv_co_pwritev = nvme_co_pwritev, 1584e0dd95e3SMaxim Levitsky 1585e0dd95e3SMaxim Levitsky .bdrv_co_pwrite_zeroes = nvme_co_pwrite_zeroes, 1586e87a09d6SMaxim Levitsky .bdrv_co_pdiscard = nvme_co_pdiscard, 1587e0dd95e3SMaxim Levitsky 1588bdd6a90aSFam Zheng .bdrv_co_flush_to_disk = nvme_co_flush, 1589bdd6a90aSFam Zheng .bdrv_reopen_prepare = nvme_reopen_prepare, 1590bdd6a90aSFam Zheng 1591bdd6a90aSFam Zheng .bdrv_refresh_filename = nvme_refresh_filename, 1592bdd6a90aSFam Zheng .bdrv_refresh_limits = nvme_refresh_limits, 15932654267cSMax Reitz .strong_runtime_opts = nvme_strong_runtime_opts, 1594f25e7ab2SPhilippe Mathieu-Daudé .bdrv_get_specific_stats = nvme_get_specific_stats, 1595bdd6a90aSFam Zheng 1596bdd6a90aSFam Zheng .bdrv_detach_aio_context = nvme_detach_aio_context, 1597bdd6a90aSFam Zheng .bdrv_attach_aio_context = nvme_attach_aio_context, 1598bdd6a90aSFam Zheng 1599bdd6a90aSFam Zheng .bdrv_io_plug = nvme_aio_plug, 1600bdd6a90aSFam Zheng .bdrv_io_unplug = nvme_aio_unplug, 16019ed61612SFam Zheng 16029ed61612SFam Zheng .bdrv_register_buf = nvme_register_buf, 16039ed61612SFam Zheng .bdrv_unregister_buf = nvme_unregister_buf, 1604bdd6a90aSFam Zheng }; 1605bdd6a90aSFam Zheng 1606bdd6a90aSFam Zheng static void bdrv_nvme_init(void) 1607bdd6a90aSFam Zheng { 1608bdd6a90aSFam Zheng bdrv_register(&bdrv_nvme); 1609bdd6a90aSFam Zheng } 1610bdd6a90aSFam Zheng 1611bdd6a90aSFam Zheng block_init(bdrv_nvme_init); 1612