1bdd6a90aSFam Zheng /* 2bdd6a90aSFam Zheng * NVMe block driver based on vfio 3bdd6a90aSFam Zheng * 4bdd6a90aSFam Zheng * Copyright 2016 - 2018 Red Hat, Inc. 5bdd6a90aSFam Zheng * 6bdd6a90aSFam Zheng * Authors: 7bdd6a90aSFam Zheng * Fam Zheng <famz@redhat.com> 8bdd6a90aSFam Zheng * Paolo Bonzini <pbonzini@redhat.com> 9bdd6a90aSFam Zheng * 10bdd6a90aSFam Zheng * This work is licensed under the terms of the GNU GPL, version 2 or later. 11bdd6a90aSFam Zheng * See the COPYING file in the top-level directory. 12bdd6a90aSFam Zheng */ 13bdd6a90aSFam Zheng 14bdd6a90aSFam Zheng #include "qemu/osdep.h" 15bdd6a90aSFam Zheng #include <linux/vfio.h> 16bdd6a90aSFam Zheng #include "qapi/error.h" 17bdd6a90aSFam Zheng #include "qapi/qmp/qdict.h" 18bdd6a90aSFam Zheng #include "qapi/qmp/qstring.h" 19bdd6a90aSFam Zheng #include "qemu/error-report.h" 200b8fa32fSMarkus Armbruster #include "qemu/module.h" 21bdd6a90aSFam Zheng #include "qemu/cutils.h" 22922a01a0SMarkus Armbruster #include "qemu/option.h" 23bdd6a90aSFam Zheng #include "qemu/vfio-helpers.h" 24bdd6a90aSFam Zheng #include "block/block_int.h" 25bdd6a90aSFam Zheng #include "trace.h" 26bdd6a90aSFam Zheng 27a3d9a352SFam Zheng #include "block/nvme.h" 28bdd6a90aSFam Zheng 29bdd6a90aSFam Zheng #define NVME_SQ_ENTRY_BYTES 64 30bdd6a90aSFam Zheng #define NVME_CQ_ENTRY_BYTES 16 31bdd6a90aSFam Zheng #define NVME_QUEUE_SIZE 128 32bdd6a90aSFam Zheng #define NVME_BAR_SIZE 8192 33bdd6a90aSFam Zheng 34bdd6a90aSFam Zheng typedef struct { 35bdd6a90aSFam Zheng int32_t head, tail; 36bdd6a90aSFam Zheng uint8_t *queue; 37bdd6a90aSFam Zheng uint64_t iova; 38bdd6a90aSFam Zheng /* Hardware MMIO register */ 39bdd6a90aSFam Zheng volatile uint32_t *doorbell; 40bdd6a90aSFam Zheng } NVMeQueue; 41bdd6a90aSFam Zheng 42bdd6a90aSFam Zheng typedef struct { 43bdd6a90aSFam Zheng BlockCompletionFunc *cb; 44bdd6a90aSFam Zheng void *opaque; 45bdd6a90aSFam Zheng int cid; 46bdd6a90aSFam Zheng void *prp_list_page; 47bdd6a90aSFam Zheng uint64_t prp_list_iova; 48bdd6a90aSFam Zheng bool busy; 49bdd6a90aSFam Zheng } NVMeRequest; 50bdd6a90aSFam Zheng 51bdd6a90aSFam Zheng typedef struct { 52bdd6a90aSFam Zheng CoQueue free_req_queue; 53bdd6a90aSFam Zheng QemuMutex lock; 54bdd6a90aSFam Zheng 55bdd6a90aSFam Zheng /* Fields protected by BQL */ 56bdd6a90aSFam Zheng int index; 57bdd6a90aSFam Zheng uint8_t *prp_list_pages; 58bdd6a90aSFam Zheng 59bdd6a90aSFam Zheng /* Fields protected by @lock */ 60bdd6a90aSFam Zheng NVMeQueue sq, cq; 61bdd6a90aSFam Zheng int cq_phase; 62bdd6a90aSFam Zheng NVMeRequest reqs[NVME_QUEUE_SIZE]; 63bdd6a90aSFam Zheng bool busy; 64bdd6a90aSFam Zheng int need_kick; 65bdd6a90aSFam Zheng int inflight; 66bdd6a90aSFam Zheng } NVMeQueuePair; 67bdd6a90aSFam Zheng 68bdd6a90aSFam Zheng /* Memory mapped registers */ 69bdd6a90aSFam Zheng typedef volatile struct { 70bdd6a90aSFam Zheng uint64_t cap; 71bdd6a90aSFam Zheng uint32_t vs; 72bdd6a90aSFam Zheng uint32_t intms; 73bdd6a90aSFam Zheng uint32_t intmc; 74bdd6a90aSFam Zheng uint32_t cc; 75bdd6a90aSFam Zheng uint32_t reserved0; 76bdd6a90aSFam Zheng uint32_t csts; 77bdd6a90aSFam Zheng uint32_t nssr; 78bdd6a90aSFam Zheng uint32_t aqa; 79bdd6a90aSFam Zheng uint64_t asq; 80bdd6a90aSFam Zheng uint64_t acq; 81bdd6a90aSFam Zheng uint32_t cmbloc; 82bdd6a90aSFam Zheng uint32_t cmbsz; 83bdd6a90aSFam Zheng uint8_t reserved1[0xec0]; 84bdd6a90aSFam Zheng uint8_t cmd_set_specfic[0x100]; 85bdd6a90aSFam Zheng uint32_t doorbells[]; 8683c68e14SThomas Huth } NVMeRegs; 87bdd6a90aSFam Zheng 88bdd6a90aSFam Zheng QEMU_BUILD_BUG_ON(offsetof(NVMeRegs, doorbells) != 0x1000); 89bdd6a90aSFam Zheng 90bdd6a90aSFam Zheng typedef struct { 91bdd6a90aSFam Zheng AioContext *aio_context; 92bdd6a90aSFam Zheng QEMUVFIOState *vfio; 93bdd6a90aSFam Zheng NVMeRegs *regs; 94bdd6a90aSFam Zheng /* The submission/completion queue pairs. 95bdd6a90aSFam Zheng * [0]: admin queue. 96bdd6a90aSFam Zheng * [1..]: io queues. 97bdd6a90aSFam Zheng */ 98bdd6a90aSFam Zheng NVMeQueuePair **queues; 99bdd6a90aSFam Zheng int nr_queues; 100bdd6a90aSFam Zheng size_t page_size; 101bdd6a90aSFam Zheng /* How many uint32_t elements does each doorbell entry take. */ 102bdd6a90aSFam Zheng size_t doorbell_scale; 103bdd6a90aSFam Zheng bool write_cache_supported; 104bdd6a90aSFam Zheng EventNotifier irq_notifier; 105bdd6a90aSFam Zheng uint64_t nsze; /* Namespace size reported by identify command */ 106bdd6a90aSFam Zheng int nsid; /* The namespace id to read/write data. */ 107bdd6a90aSFam Zheng uint64_t max_transfer; 1082f0d8947SPaolo Bonzini bool plugged; 109bdd6a90aSFam Zheng 110bdd6a90aSFam Zheng CoMutex dma_map_lock; 111bdd6a90aSFam Zheng CoQueue dma_flush_queue; 112bdd6a90aSFam Zheng 113bdd6a90aSFam Zheng /* Total size of mapped qiov, accessed under dma_map_lock */ 114bdd6a90aSFam Zheng int dma_map_count; 115cc61b074SMax Reitz 116cc61b074SMax Reitz /* PCI address (required for nvme_refresh_filename()) */ 117cc61b074SMax Reitz char *device; 118bdd6a90aSFam Zheng } BDRVNVMeState; 119bdd6a90aSFam Zheng 120bdd6a90aSFam Zheng #define NVME_BLOCK_OPT_DEVICE "device" 121bdd6a90aSFam Zheng #define NVME_BLOCK_OPT_NAMESPACE "namespace" 122bdd6a90aSFam Zheng 123bdd6a90aSFam Zheng static QemuOptsList runtime_opts = { 124bdd6a90aSFam Zheng .name = "nvme", 125bdd6a90aSFam Zheng .head = QTAILQ_HEAD_INITIALIZER(runtime_opts.head), 126bdd6a90aSFam Zheng .desc = { 127bdd6a90aSFam Zheng { 128bdd6a90aSFam Zheng .name = NVME_BLOCK_OPT_DEVICE, 129bdd6a90aSFam Zheng .type = QEMU_OPT_STRING, 130bdd6a90aSFam Zheng .help = "NVMe PCI device address", 131bdd6a90aSFam Zheng }, 132bdd6a90aSFam Zheng { 133bdd6a90aSFam Zheng .name = NVME_BLOCK_OPT_NAMESPACE, 134bdd6a90aSFam Zheng .type = QEMU_OPT_NUMBER, 135bdd6a90aSFam Zheng .help = "NVMe namespace", 136bdd6a90aSFam Zheng }, 137bdd6a90aSFam Zheng { /* end of list */ } 138bdd6a90aSFam Zheng }, 139bdd6a90aSFam Zheng }; 140bdd6a90aSFam Zheng 141bdd6a90aSFam Zheng static void nvme_init_queue(BlockDriverState *bs, NVMeQueue *q, 142bdd6a90aSFam Zheng int nentries, int entry_bytes, Error **errp) 143bdd6a90aSFam Zheng { 144bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 145bdd6a90aSFam Zheng size_t bytes; 146bdd6a90aSFam Zheng int r; 147bdd6a90aSFam Zheng 148bdd6a90aSFam Zheng bytes = ROUND_UP(nentries * entry_bytes, s->page_size); 149bdd6a90aSFam Zheng q->head = q->tail = 0; 150bdd6a90aSFam Zheng q->queue = qemu_try_blockalign0(bs, bytes); 151bdd6a90aSFam Zheng 152bdd6a90aSFam Zheng if (!q->queue) { 153bdd6a90aSFam Zheng error_setg(errp, "Cannot allocate queue"); 154bdd6a90aSFam Zheng return; 155bdd6a90aSFam Zheng } 156bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, q->queue, bytes, false, &q->iova); 157bdd6a90aSFam Zheng if (r) { 158bdd6a90aSFam Zheng error_setg(errp, "Cannot map queue"); 159bdd6a90aSFam Zheng } 160bdd6a90aSFam Zheng } 161bdd6a90aSFam Zheng 162bdd6a90aSFam Zheng static void nvme_free_queue_pair(BlockDriverState *bs, NVMeQueuePair *q) 163bdd6a90aSFam Zheng { 164bdd6a90aSFam Zheng qemu_vfree(q->prp_list_pages); 165bdd6a90aSFam Zheng qemu_vfree(q->sq.queue); 166bdd6a90aSFam Zheng qemu_vfree(q->cq.queue); 167bdd6a90aSFam Zheng qemu_mutex_destroy(&q->lock); 168bdd6a90aSFam Zheng g_free(q); 169bdd6a90aSFam Zheng } 170bdd6a90aSFam Zheng 171bdd6a90aSFam Zheng static void nvme_free_req_queue_cb(void *opaque) 172bdd6a90aSFam Zheng { 173bdd6a90aSFam Zheng NVMeQueuePair *q = opaque; 174bdd6a90aSFam Zheng 175bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 176bdd6a90aSFam Zheng while (qemu_co_enter_next(&q->free_req_queue, &q->lock)) { 177bdd6a90aSFam Zheng /* Retry all pending requests */ 178bdd6a90aSFam Zheng } 179bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 180bdd6a90aSFam Zheng } 181bdd6a90aSFam Zheng 182bdd6a90aSFam Zheng static NVMeQueuePair *nvme_create_queue_pair(BlockDriverState *bs, 183bdd6a90aSFam Zheng int idx, int size, 184bdd6a90aSFam Zheng Error **errp) 185bdd6a90aSFam Zheng { 186bdd6a90aSFam Zheng int i, r; 187bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 188bdd6a90aSFam Zheng Error *local_err = NULL; 189bdd6a90aSFam Zheng NVMeQueuePair *q = g_new0(NVMeQueuePair, 1); 190bdd6a90aSFam Zheng uint64_t prp_list_iova; 191bdd6a90aSFam Zheng 192bdd6a90aSFam Zheng qemu_mutex_init(&q->lock); 193bdd6a90aSFam Zheng q->index = idx; 194bdd6a90aSFam Zheng qemu_co_queue_init(&q->free_req_queue); 195bdd6a90aSFam Zheng q->prp_list_pages = qemu_blockalign0(bs, s->page_size * NVME_QUEUE_SIZE); 196bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, q->prp_list_pages, 197bdd6a90aSFam Zheng s->page_size * NVME_QUEUE_SIZE, 198bdd6a90aSFam Zheng false, &prp_list_iova); 199bdd6a90aSFam Zheng if (r) { 200bdd6a90aSFam Zheng goto fail; 201bdd6a90aSFam Zheng } 202bdd6a90aSFam Zheng for (i = 0; i < NVME_QUEUE_SIZE; i++) { 203bdd6a90aSFam Zheng NVMeRequest *req = &q->reqs[i]; 204bdd6a90aSFam Zheng req->cid = i + 1; 205bdd6a90aSFam Zheng req->prp_list_page = q->prp_list_pages + i * s->page_size; 206bdd6a90aSFam Zheng req->prp_list_iova = prp_list_iova + i * s->page_size; 207bdd6a90aSFam Zheng } 208bdd6a90aSFam Zheng nvme_init_queue(bs, &q->sq, size, NVME_SQ_ENTRY_BYTES, &local_err); 209bdd6a90aSFam Zheng if (local_err) { 210bdd6a90aSFam Zheng error_propagate(errp, local_err); 211bdd6a90aSFam Zheng goto fail; 212bdd6a90aSFam Zheng } 213bdd6a90aSFam Zheng q->sq.doorbell = &s->regs->doorbells[idx * 2 * s->doorbell_scale]; 214bdd6a90aSFam Zheng 215bdd6a90aSFam Zheng nvme_init_queue(bs, &q->cq, size, NVME_CQ_ENTRY_BYTES, &local_err); 216bdd6a90aSFam Zheng if (local_err) { 217bdd6a90aSFam Zheng error_propagate(errp, local_err); 218bdd6a90aSFam Zheng goto fail; 219bdd6a90aSFam Zheng } 220bdd6a90aSFam Zheng q->cq.doorbell = &s->regs->doorbells[idx * 2 * s->doorbell_scale + 1]; 221bdd6a90aSFam Zheng 222bdd6a90aSFam Zheng return q; 223bdd6a90aSFam Zheng fail: 224bdd6a90aSFam Zheng nvme_free_queue_pair(bs, q); 225bdd6a90aSFam Zheng return NULL; 226bdd6a90aSFam Zheng } 227bdd6a90aSFam Zheng 228bdd6a90aSFam Zheng /* With q->lock */ 229bdd6a90aSFam Zheng static void nvme_kick(BDRVNVMeState *s, NVMeQueuePair *q) 230bdd6a90aSFam Zheng { 231bdd6a90aSFam Zheng if (s->plugged || !q->need_kick) { 232bdd6a90aSFam Zheng return; 233bdd6a90aSFam Zheng } 234bdd6a90aSFam Zheng trace_nvme_kick(s, q->index); 235bdd6a90aSFam Zheng assert(!(q->sq.tail & 0xFF00)); 236bdd6a90aSFam Zheng /* Fence the write to submission queue entry before notifying the device. */ 237bdd6a90aSFam Zheng smp_wmb(); 238bdd6a90aSFam Zheng *q->sq.doorbell = cpu_to_le32(q->sq.tail); 239bdd6a90aSFam Zheng q->inflight += q->need_kick; 240bdd6a90aSFam Zheng q->need_kick = 0; 241bdd6a90aSFam Zheng } 242bdd6a90aSFam Zheng 243bdd6a90aSFam Zheng /* Find a free request element if any, otherwise: 244bdd6a90aSFam Zheng * a) if in coroutine context, try to wait for one to become available; 245bdd6a90aSFam Zheng * b) if not in coroutine, return NULL; 246bdd6a90aSFam Zheng */ 247bdd6a90aSFam Zheng static NVMeRequest *nvme_get_free_req(NVMeQueuePair *q) 248bdd6a90aSFam Zheng { 249bdd6a90aSFam Zheng int i; 250bdd6a90aSFam Zheng NVMeRequest *req = NULL; 251bdd6a90aSFam Zheng 252bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 253bdd6a90aSFam Zheng while (q->inflight + q->need_kick > NVME_QUEUE_SIZE - 2) { 254bdd6a90aSFam Zheng /* We have to leave one slot empty as that is the full queue case (head 255bdd6a90aSFam Zheng * == tail + 1). */ 256bdd6a90aSFam Zheng if (qemu_in_coroutine()) { 257bdd6a90aSFam Zheng trace_nvme_free_req_queue_wait(q); 258bdd6a90aSFam Zheng qemu_co_queue_wait(&q->free_req_queue, &q->lock); 259bdd6a90aSFam Zheng } else { 260bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 261bdd6a90aSFam Zheng return NULL; 262bdd6a90aSFam Zheng } 263bdd6a90aSFam Zheng } 264bdd6a90aSFam Zheng for (i = 0; i < NVME_QUEUE_SIZE; i++) { 265bdd6a90aSFam Zheng if (!q->reqs[i].busy) { 266bdd6a90aSFam Zheng q->reqs[i].busy = true; 267bdd6a90aSFam Zheng req = &q->reqs[i]; 268bdd6a90aSFam Zheng break; 269bdd6a90aSFam Zheng } 270bdd6a90aSFam Zheng } 271bdd6a90aSFam Zheng /* We have checked inflight and need_kick while holding q->lock, so one 272bdd6a90aSFam Zheng * free req must be available. */ 273bdd6a90aSFam Zheng assert(req); 274bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 275bdd6a90aSFam Zheng return req; 276bdd6a90aSFam Zheng } 277bdd6a90aSFam Zheng 278bdd6a90aSFam Zheng static inline int nvme_translate_error(const NvmeCqe *c) 279bdd6a90aSFam Zheng { 280bdd6a90aSFam Zheng uint16_t status = (le16_to_cpu(c->status) >> 1) & 0xFF; 281bdd6a90aSFam Zheng if (status) { 282bdd6a90aSFam Zheng trace_nvme_error(le32_to_cpu(c->result), 283bdd6a90aSFam Zheng le16_to_cpu(c->sq_head), 284bdd6a90aSFam Zheng le16_to_cpu(c->sq_id), 285bdd6a90aSFam Zheng le16_to_cpu(c->cid), 286bdd6a90aSFam Zheng le16_to_cpu(status)); 287bdd6a90aSFam Zheng } 288bdd6a90aSFam Zheng switch (status) { 289bdd6a90aSFam Zheng case 0: 290bdd6a90aSFam Zheng return 0; 291bdd6a90aSFam Zheng case 1: 292bdd6a90aSFam Zheng return -ENOSYS; 293bdd6a90aSFam Zheng case 2: 294bdd6a90aSFam Zheng return -EINVAL; 295bdd6a90aSFam Zheng default: 296bdd6a90aSFam Zheng return -EIO; 297bdd6a90aSFam Zheng } 298bdd6a90aSFam Zheng } 299bdd6a90aSFam Zheng 300bdd6a90aSFam Zheng /* With q->lock */ 301bdd6a90aSFam Zheng static bool nvme_process_completion(BDRVNVMeState *s, NVMeQueuePair *q) 302bdd6a90aSFam Zheng { 303bdd6a90aSFam Zheng bool progress = false; 304bdd6a90aSFam Zheng NVMeRequest *preq; 305bdd6a90aSFam Zheng NVMeRequest req; 306bdd6a90aSFam Zheng NvmeCqe *c; 307bdd6a90aSFam Zheng 308bdd6a90aSFam Zheng trace_nvme_process_completion(s, q->index, q->inflight); 309bdd6a90aSFam Zheng if (q->busy || s->plugged) { 310bdd6a90aSFam Zheng trace_nvme_process_completion_queue_busy(s, q->index); 311bdd6a90aSFam Zheng return false; 312bdd6a90aSFam Zheng } 313bdd6a90aSFam Zheng q->busy = true; 314bdd6a90aSFam Zheng assert(q->inflight >= 0); 315bdd6a90aSFam Zheng while (q->inflight) { 316bdd6a90aSFam Zheng int16_t cid; 317bdd6a90aSFam Zheng c = (NvmeCqe *)&q->cq.queue[q->cq.head * NVME_CQ_ENTRY_BYTES]; 318bdd6a90aSFam Zheng if (!c->cid || (le16_to_cpu(c->status) & 0x1) == q->cq_phase) { 319bdd6a90aSFam Zheng break; 320bdd6a90aSFam Zheng } 321bdd6a90aSFam Zheng q->cq.head = (q->cq.head + 1) % NVME_QUEUE_SIZE; 322bdd6a90aSFam Zheng if (!q->cq.head) { 323bdd6a90aSFam Zheng q->cq_phase = !q->cq_phase; 324bdd6a90aSFam Zheng } 325bdd6a90aSFam Zheng cid = le16_to_cpu(c->cid); 326bdd6a90aSFam Zheng if (cid == 0 || cid > NVME_QUEUE_SIZE) { 327bdd6a90aSFam Zheng fprintf(stderr, "Unexpected CID in completion queue: %" PRIu32 "\n", 328bdd6a90aSFam Zheng cid); 329bdd6a90aSFam Zheng continue; 330bdd6a90aSFam Zheng } 331bdd6a90aSFam Zheng assert(cid <= NVME_QUEUE_SIZE); 332bdd6a90aSFam Zheng trace_nvme_complete_command(s, q->index, cid); 333bdd6a90aSFam Zheng preq = &q->reqs[cid - 1]; 334bdd6a90aSFam Zheng req = *preq; 335bdd6a90aSFam Zheng assert(req.cid == cid); 336bdd6a90aSFam Zheng assert(req.cb); 337bdd6a90aSFam Zheng preq->busy = false; 338bdd6a90aSFam Zheng preq->cb = preq->opaque = NULL; 339bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 340bdd6a90aSFam Zheng req.cb(req.opaque, nvme_translate_error(c)); 341bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 342bdd6a90aSFam Zheng c->cid = cpu_to_le16(0); 343bdd6a90aSFam Zheng q->inflight--; 344bdd6a90aSFam Zheng /* Flip Phase Tag bit. */ 345bdd6a90aSFam Zheng c->status = cpu_to_le16(le16_to_cpu(c->status) ^ 0x1); 346bdd6a90aSFam Zheng progress = true; 347bdd6a90aSFam Zheng } 348bdd6a90aSFam Zheng if (progress) { 349bdd6a90aSFam Zheng /* Notify the device so it can post more completions. */ 350bdd6a90aSFam Zheng smp_mb_release(); 351bdd6a90aSFam Zheng *q->cq.doorbell = cpu_to_le32(q->cq.head); 352bdd6a90aSFam Zheng if (!qemu_co_queue_empty(&q->free_req_queue)) { 353bdd6a90aSFam Zheng aio_bh_schedule_oneshot(s->aio_context, nvme_free_req_queue_cb, q); 354bdd6a90aSFam Zheng } 355bdd6a90aSFam Zheng } 356bdd6a90aSFam Zheng q->busy = false; 357bdd6a90aSFam Zheng return progress; 358bdd6a90aSFam Zheng } 359bdd6a90aSFam Zheng 360bdd6a90aSFam Zheng static void nvme_trace_command(const NvmeCmd *cmd) 361bdd6a90aSFam Zheng { 362bdd6a90aSFam Zheng int i; 363bdd6a90aSFam Zheng 364bdd6a90aSFam Zheng for (i = 0; i < 8; ++i) { 365bdd6a90aSFam Zheng uint8_t *cmdp = (uint8_t *)cmd + i * 8; 366bdd6a90aSFam Zheng trace_nvme_submit_command_raw(cmdp[0], cmdp[1], cmdp[2], cmdp[3], 367bdd6a90aSFam Zheng cmdp[4], cmdp[5], cmdp[6], cmdp[7]); 368bdd6a90aSFam Zheng } 369bdd6a90aSFam Zheng } 370bdd6a90aSFam Zheng 371bdd6a90aSFam Zheng static void nvme_submit_command(BDRVNVMeState *s, NVMeQueuePair *q, 372bdd6a90aSFam Zheng NVMeRequest *req, 373bdd6a90aSFam Zheng NvmeCmd *cmd, BlockCompletionFunc cb, 374bdd6a90aSFam Zheng void *opaque) 375bdd6a90aSFam Zheng { 376bdd6a90aSFam Zheng assert(!req->cb); 377bdd6a90aSFam Zheng req->cb = cb; 378bdd6a90aSFam Zheng req->opaque = opaque; 379bdd6a90aSFam Zheng cmd->cid = cpu_to_le32(req->cid); 380bdd6a90aSFam Zheng 381bdd6a90aSFam Zheng trace_nvme_submit_command(s, q->index, req->cid); 382bdd6a90aSFam Zheng nvme_trace_command(cmd); 383bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 384bdd6a90aSFam Zheng memcpy((uint8_t *)q->sq.queue + 385bdd6a90aSFam Zheng q->sq.tail * NVME_SQ_ENTRY_BYTES, cmd, sizeof(*cmd)); 386bdd6a90aSFam Zheng q->sq.tail = (q->sq.tail + 1) % NVME_QUEUE_SIZE; 387bdd6a90aSFam Zheng q->need_kick++; 388bdd6a90aSFam Zheng nvme_kick(s, q); 389bdd6a90aSFam Zheng nvme_process_completion(s, q); 390bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 391bdd6a90aSFam Zheng } 392bdd6a90aSFam Zheng 393bdd6a90aSFam Zheng static void nvme_cmd_sync_cb(void *opaque, int ret) 394bdd6a90aSFam Zheng { 395bdd6a90aSFam Zheng int *pret = opaque; 396bdd6a90aSFam Zheng *pret = ret; 3974720cbeeSKevin Wolf aio_wait_kick(); 398bdd6a90aSFam Zheng } 399bdd6a90aSFam Zheng 400bdd6a90aSFam Zheng static int nvme_cmd_sync(BlockDriverState *bs, NVMeQueuePair *q, 401bdd6a90aSFam Zheng NvmeCmd *cmd) 402bdd6a90aSFam Zheng { 403bdd6a90aSFam Zheng NVMeRequest *req; 404bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 405bdd6a90aSFam Zheng int ret = -EINPROGRESS; 406bdd6a90aSFam Zheng req = nvme_get_free_req(q); 407bdd6a90aSFam Zheng if (!req) { 408bdd6a90aSFam Zheng return -EBUSY; 409bdd6a90aSFam Zheng } 410bdd6a90aSFam Zheng nvme_submit_command(s, q, req, cmd, nvme_cmd_sync_cb, &ret); 411bdd6a90aSFam Zheng 412bdd6a90aSFam Zheng BDRV_POLL_WHILE(bs, ret == -EINPROGRESS); 413bdd6a90aSFam Zheng return ret; 414bdd6a90aSFam Zheng } 415bdd6a90aSFam Zheng 416bdd6a90aSFam Zheng static void nvme_identify(BlockDriverState *bs, int namespace, Error **errp) 417bdd6a90aSFam Zheng { 418bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 419bdd6a90aSFam Zheng NvmeIdCtrl *idctrl; 420bdd6a90aSFam Zheng NvmeIdNs *idns; 421bdd6a90aSFam Zheng uint8_t *resp; 422bdd6a90aSFam Zheng int r; 423bdd6a90aSFam Zheng uint64_t iova; 424bdd6a90aSFam Zheng NvmeCmd cmd = { 425bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_IDENTIFY, 426bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(0x1), 427bdd6a90aSFam Zheng }; 428bdd6a90aSFam Zheng 429bdd6a90aSFam Zheng resp = qemu_try_blockalign0(bs, sizeof(NvmeIdCtrl)); 430bdd6a90aSFam Zheng if (!resp) { 431bdd6a90aSFam Zheng error_setg(errp, "Cannot allocate buffer for identify response"); 432bdd6a90aSFam Zheng goto out; 433bdd6a90aSFam Zheng } 434bdd6a90aSFam Zheng idctrl = (NvmeIdCtrl *)resp; 435bdd6a90aSFam Zheng idns = (NvmeIdNs *)resp; 436bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, resp, sizeof(NvmeIdCtrl), true, &iova); 437bdd6a90aSFam Zheng if (r) { 438bdd6a90aSFam Zheng error_setg(errp, "Cannot map buffer for DMA"); 439bdd6a90aSFam Zheng goto out; 440bdd6a90aSFam Zheng } 441bdd6a90aSFam Zheng cmd.prp1 = cpu_to_le64(iova); 442bdd6a90aSFam Zheng 443bdd6a90aSFam Zheng if (nvme_cmd_sync(bs, s->queues[0], &cmd)) { 444bdd6a90aSFam Zheng error_setg(errp, "Failed to identify controller"); 445bdd6a90aSFam Zheng goto out; 446bdd6a90aSFam Zheng } 447bdd6a90aSFam Zheng 448bdd6a90aSFam Zheng if (le32_to_cpu(idctrl->nn) < namespace) { 449bdd6a90aSFam Zheng error_setg(errp, "Invalid namespace"); 450bdd6a90aSFam Zheng goto out; 451bdd6a90aSFam Zheng } 452bdd6a90aSFam Zheng s->write_cache_supported = le32_to_cpu(idctrl->vwc) & 0x1; 453bdd6a90aSFam Zheng s->max_transfer = (idctrl->mdts ? 1 << idctrl->mdts : 0) * s->page_size; 454bdd6a90aSFam Zheng /* For now the page list buffer per command is one page, to hold at most 455bdd6a90aSFam Zheng * s->page_size / sizeof(uint64_t) entries. */ 456bdd6a90aSFam Zheng s->max_transfer = MIN_NON_ZERO(s->max_transfer, 457bdd6a90aSFam Zheng s->page_size / sizeof(uint64_t) * s->page_size); 458bdd6a90aSFam Zheng 459bdd6a90aSFam Zheng memset(resp, 0, 4096); 460bdd6a90aSFam Zheng 461bdd6a90aSFam Zheng cmd.cdw10 = 0; 462bdd6a90aSFam Zheng cmd.nsid = cpu_to_le32(namespace); 463bdd6a90aSFam Zheng if (nvme_cmd_sync(bs, s->queues[0], &cmd)) { 464bdd6a90aSFam Zheng error_setg(errp, "Failed to identify namespace"); 465bdd6a90aSFam Zheng goto out; 466bdd6a90aSFam Zheng } 467bdd6a90aSFam Zheng 468bdd6a90aSFam Zheng s->nsze = le64_to_cpu(idns->nsze); 469bdd6a90aSFam Zheng 470bdd6a90aSFam Zheng out: 471bdd6a90aSFam Zheng qemu_vfio_dma_unmap(s->vfio, resp); 472bdd6a90aSFam Zheng qemu_vfree(resp); 473bdd6a90aSFam Zheng } 474bdd6a90aSFam Zheng 475bdd6a90aSFam Zheng static bool nvme_poll_queues(BDRVNVMeState *s) 476bdd6a90aSFam Zheng { 477bdd6a90aSFam Zheng bool progress = false; 478bdd6a90aSFam Zheng int i; 479bdd6a90aSFam Zheng 480bdd6a90aSFam Zheng for (i = 0; i < s->nr_queues; i++) { 481bdd6a90aSFam Zheng NVMeQueuePair *q = s->queues[i]; 482bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 483bdd6a90aSFam Zheng while (nvme_process_completion(s, q)) { 484bdd6a90aSFam Zheng /* Keep polling */ 485bdd6a90aSFam Zheng progress = true; 486bdd6a90aSFam Zheng } 487bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 488bdd6a90aSFam Zheng } 489bdd6a90aSFam Zheng return progress; 490bdd6a90aSFam Zheng } 491bdd6a90aSFam Zheng 492bdd6a90aSFam Zheng static void nvme_handle_event(EventNotifier *n) 493bdd6a90aSFam Zheng { 494bdd6a90aSFam Zheng BDRVNVMeState *s = container_of(n, BDRVNVMeState, irq_notifier); 495bdd6a90aSFam Zheng 496bdd6a90aSFam Zheng trace_nvme_handle_event(s); 497bdd6a90aSFam Zheng event_notifier_test_and_clear(n); 498bdd6a90aSFam Zheng nvme_poll_queues(s); 499bdd6a90aSFam Zheng } 500bdd6a90aSFam Zheng 501bdd6a90aSFam Zheng static bool nvme_add_io_queue(BlockDriverState *bs, Error **errp) 502bdd6a90aSFam Zheng { 503bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 504bdd6a90aSFam Zheng int n = s->nr_queues; 505bdd6a90aSFam Zheng NVMeQueuePair *q; 506bdd6a90aSFam Zheng NvmeCmd cmd; 507bdd6a90aSFam Zheng int queue_size = NVME_QUEUE_SIZE; 508bdd6a90aSFam Zheng 509bdd6a90aSFam Zheng q = nvme_create_queue_pair(bs, n, queue_size, errp); 510bdd6a90aSFam Zheng if (!q) { 511bdd6a90aSFam Zheng return false; 512bdd6a90aSFam Zheng } 513bdd6a90aSFam Zheng cmd = (NvmeCmd) { 514bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_CREATE_CQ, 515bdd6a90aSFam Zheng .prp1 = cpu_to_le64(q->cq.iova), 516bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | (n & 0xFFFF)), 517bdd6a90aSFam Zheng .cdw11 = cpu_to_le32(0x3), 518bdd6a90aSFam Zheng }; 519bdd6a90aSFam Zheng if (nvme_cmd_sync(bs, s->queues[0], &cmd)) { 520bdd6a90aSFam Zheng error_setg(errp, "Failed to create io queue [%d]", n); 521bdd6a90aSFam Zheng nvme_free_queue_pair(bs, q); 522bdd6a90aSFam Zheng return false; 523bdd6a90aSFam Zheng } 524bdd6a90aSFam Zheng cmd = (NvmeCmd) { 525bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_CREATE_SQ, 526bdd6a90aSFam Zheng .prp1 = cpu_to_le64(q->sq.iova), 527bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | (n & 0xFFFF)), 528bdd6a90aSFam Zheng .cdw11 = cpu_to_le32(0x1 | (n << 16)), 529bdd6a90aSFam Zheng }; 530bdd6a90aSFam Zheng if (nvme_cmd_sync(bs, s->queues[0], &cmd)) { 531bdd6a90aSFam Zheng error_setg(errp, "Failed to create io queue [%d]", n); 532bdd6a90aSFam Zheng nvme_free_queue_pair(bs, q); 533bdd6a90aSFam Zheng return false; 534bdd6a90aSFam Zheng } 535bdd6a90aSFam Zheng s->queues = g_renew(NVMeQueuePair *, s->queues, n + 1); 536bdd6a90aSFam Zheng s->queues[n] = q; 537bdd6a90aSFam Zheng s->nr_queues++; 538bdd6a90aSFam Zheng return true; 539bdd6a90aSFam Zheng } 540bdd6a90aSFam Zheng 541bdd6a90aSFam Zheng static bool nvme_poll_cb(void *opaque) 542bdd6a90aSFam Zheng { 543bdd6a90aSFam Zheng EventNotifier *e = opaque; 544bdd6a90aSFam Zheng BDRVNVMeState *s = container_of(e, BDRVNVMeState, irq_notifier); 545bdd6a90aSFam Zheng bool progress = false; 546bdd6a90aSFam Zheng 547bdd6a90aSFam Zheng trace_nvme_poll_cb(s); 548bdd6a90aSFam Zheng progress = nvme_poll_queues(s); 549bdd6a90aSFam Zheng return progress; 550bdd6a90aSFam Zheng } 551bdd6a90aSFam Zheng 552bdd6a90aSFam Zheng static int nvme_init(BlockDriverState *bs, const char *device, int namespace, 553bdd6a90aSFam Zheng Error **errp) 554bdd6a90aSFam Zheng { 555bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 556bdd6a90aSFam Zheng int ret; 557bdd6a90aSFam Zheng uint64_t cap; 558bdd6a90aSFam Zheng uint64_t timeout_ms; 559bdd6a90aSFam Zheng uint64_t deadline, now; 560bdd6a90aSFam Zheng Error *local_err = NULL; 561bdd6a90aSFam Zheng 562bdd6a90aSFam Zheng qemu_co_mutex_init(&s->dma_map_lock); 563bdd6a90aSFam Zheng qemu_co_queue_init(&s->dma_flush_queue); 564cc61b074SMax Reitz s->device = g_strdup(device); 565bdd6a90aSFam Zheng s->nsid = namespace; 566bdd6a90aSFam Zheng s->aio_context = bdrv_get_aio_context(bs); 567bdd6a90aSFam Zheng ret = event_notifier_init(&s->irq_notifier, 0); 568bdd6a90aSFam Zheng if (ret) { 569bdd6a90aSFam Zheng error_setg(errp, "Failed to init event notifier"); 570bdd6a90aSFam Zheng return ret; 571bdd6a90aSFam Zheng } 572bdd6a90aSFam Zheng 573bdd6a90aSFam Zheng s->vfio = qemu_vfio_open_pci(device, errp); 574bdd6a90aSFam Zheng if (!s->vfio) { 575bdd6a90aSFam Zheng ret = -EINVAL; 5769582f357SFam Zheng goto out; 577bdd6a90aSFam Zheng } 578bdd6a90aSFam Zheng 579bdd6a90aSFam Zheng s->regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, NVME_BAR_SIZE, errp); 580bdd6a90aSFam Zheng if (!s->regs) { 581bdd6a90aSFam Zheng ret = -EINVAL; 5829582f357SFam Zheng goto out; 583bdd6a90aSFam Zheng } 584bdd6a90aSFam Zheng 585bdd6a90aSFam Zheng /* Perform initialize sequence as described in NVMe spec "7.6.1 586bdd6a90aSFam Zheng * Initialization". */ 587bdd6a90aSFam Zheng 588bdd6a90aSFam Zheng cap = le64_to_cpu(s->regs->cap); 589bdd6a90aSFam Zheng if (!(cap & (1ULL << 37))) { 590bdd6a90aSFam Zheng error_setg(errp, "Device doesn't support NVMe command set"); 591bdd6a90aSFam Zheng ret = -EINVAL; 5929582f357SFam Zheng goto out; 593bdd6a90aSFam Zheng } 594bdd6a90aSFam Zheng 595bdd6a90aSFam Zheng s->page_size = MAX(4096, 1 << (12 + ((cap >> 48) & 0xF))); 596bdd6a90aSFam Zheng s->doorbell_scale = (4 << (((cap >> 32) & 0xF))) / sizeof(uint32_t); 597bdd6a90aSFam Zheng bs->bl.opt_mem_alignment = s->page_size; 598bdd6a90aSFam Zheng timeout_ms = MIN(500 * ((cap >> 24) & 0xFF), 30000); 599bdd6a90aSFam Zheng 600bdd6a90aSFam Zheng /* Reset device to get a clean state. */ 601bdd6a90aSFam Zheng s->regs->cc = cpu_to_le32(le32_to_cpu(s->regs->cc) & 0xFE); 602bdd6a90aSFam Zheng /* Wait for CSTS.RDY = 0. */ 603bdd6a90aSFam Zheng deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * 1000000ULL; 604bdd6a90aSFam Zheng while (le32_to_cpu(s->regs->csts) & 0x1) { 605bdd6a90aSFam Zheng if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 606bdd6a90aSFam Zheng error_setg(errp, "Timeout while waiting for device to reset (%" 607bdd6a90aSFam Zheng PRId64 " ms)", 608bdd6a90aSFam Zheng timeout_ms); 609bdd6a90aSFam Zheng ret = -ETIMEDOUT; 6109582f357SFam Zheng goto out; 611bdd6a90aSFam Zheng } 612bdd6a90aSFam Zheng } 613bdd6a90aSFam Zheng 614bdd6a90aSFam Zheng /* Set up admin queue. */ 615bdd6a90aSFam Zheng s->queues = g_new(NVMeQueuePair *, 1); 616bdd6a90aSFam Zheng s->queues[0] = nvme_create_queue_pair(bs, 0, NVME_QUEUE_SIZE, errp); 617bdd6a90aSFam Zheng if (!s->queues[0]) { 618bdd6a90aSFam Zheng ret = -EINVAL; 6199582f357SFam Zheng goto out; 620bdd6a90aSFam Zheng } 621*95667c3bSMichal Privoznik s->nr_queues = 1; 622bdd6a90aSFam Zheng QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000); 623bdd6a90aSFam Zheng s->regs->aqa = cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE); 624bdd6a90aSFam Zheng s->regs->asq = cpu_to_le64(s->queues[0]->sq.iova); 625bdd6a90aSFam Zheng s->regs->acq = cpu_to_le64(s->queues[0]->cq.iova); 626bdd6a90aSFam Zheng 627bdd6a90aSFam Zheng /* After setting up all control registers we can enable device now. */ 628bdd6a90aSFam Zheng s->regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | 629bdd6a90aSFam Zheng (ctz32(NVME_SQ_ENTRY_BYTES) << 16) | 630bdd6a90aSFam Zheng 0x1); 631bdd6a90aSFam Zheng /* Wait for CSTS.RDY = 1. */ 632bdd6a90aSFam Zheng now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 633bdd6a90aSFam Zheng deadline = now + timeout_ms * 1000000; 634bdd6a90aSFam Zheng while (!(le32_to_cpu(s->regs->csts) & 0x1)) { 635bdd6a90aSFam Zheng if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 636bdd6a90aSFam Zheng error_setg(errp, "Timeout while waiting for device to start (%" 637bdd6a90aSFam Zheng PRId64 " ms)", 638bdd6a90aSFam Zheng timeout_ms); 639bdd6a90aSFam Zheng ret = -ETIMEDOUT; 6409582f357SFam Zheng goto out; 641bdd6a90aSFam Zheng } 642bdd6a90aSFam Zheng } 643bdd6a90aSFam Zheng 644bdd6a90aSFam Zheng ret = qemu_vfio_pci_init_irq(s->vfio, &s->irq_notifier, 645bdd6a90aSFam Zheng VFIO_PCI_MSIX_IRQ_INDEX, errp); 646bdd6a90aSFam Zheng if (ret) { 6479582f357SFam Zheng goto out; 648bdd6a90aSFam Zheng } 649bdd6a90aSFam Zheng aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier, 650bdd6a90aSFam Zheng false, nvme_handle_event, nvme_poll_cb); 651bdd6a90aSFam Zheng 65278d8c99eSPaolo Bonzini nvme_identify(bs, namespace, &local_err); 653bdd6a90aSFam Zheng if (local_err) { 654bdd6a90aSFam Zheng error_propagate(errp, local_err); 655bdd6a90aSFam Zheng ret = -EIO; 6569582f357SFam Zheng goto out; 657bdd6a90aSFam Zheng } 658bdd6a90aSFam Zheng 659bdd6a90aSFam Zheng /* Set up command queues. */ 660bdd6a90aSFam Zheng if (!nvme_add_io_queue(bs, errp)) { 661bdd6a90aSFam Zheng ret = -EIO; 662bdd6a90aSFam Zheng } 6639582f357SFam Zheng out: 6649582f357SFam Zheng /* Cleaning up is done in nvme_file_open() upon error. */ 665bdd6a90aSFam Zheng return ret; 666bdd6a90aSFam Zheng } 667bdd6a90aSFam Zheng 668bdd6a90aSFam Zheng /* Parse a filename in the format of nvme://XXXX:XX:XX.X/X. Example: 669bdd6a90aSFam Zheng * 670bdd6a90aSFam Zheng * nvme://0000:44:00.0/1 671bdd6a90aSFam Zheng * 672bdd6a90aSFam Zheng * where the "nvme://" is a fixed form of the protocol prefix, the middle part 673bdd6a90aSFam Zheng * is the PCI address, and the last part is the namespace number starting from 674bdd6a90aSFam Zheng * 1 according to the NVMe spec. */ 675bdd6a90aSFam Zheng static void nvme_parse_filename(const char *filename, QDict *options, 676bdd6a90aSFam Zheng Error **errp) 677bdd6a90aSFam Zheng { 678bdd6a90aSFam Zheng int pref = strlen("nvme://"); 679bdd6a90aSFam Zheng 680bdd6a90aSFam Zheng if (strlen(filename) > pref && !strncmp(filename, "nvme://", pref)) { 681bdd6a90aSFam Zheng const char *tmp = filename + pref; 682bdd6a90aSFam Zheng char *device; 683bdd6a90aSFam Zheng const char *namespace; 684bdd6a90aSFam Zheng unsigned long ns; 685bdd6a90aSFam Zheng const char *slash = strchr(tmp, '/'); 686bdd6a90aSFam Zheng if (!slash) { 687625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, tmp); 688bdd6a90aSFam Zheng return; 689bdd6a90aSFam Zheng } 690bdd6a90aSFam Zheng device = g_strndup(tmp, slash - tmp); 691625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, device); 692bdd6a90aSFam Zheng g_free(device); 693bdd6a90aSFam Zheng namespace = slash + 1; 694bdd6a90aSFam Zheng if (*namespace && qemu_strtoul(namespace, NULL, 10, &ns)) { 695bdd6a90aSFam Zheng error_setg(errp, "Invalid namespace '%s', positive number expected", 696bdd6a90aSFam Zheng namespace); 697bdd6a90aSFam Zheng return; 698bdd6a90aSFam Zheng } 699625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_NAMESPACE, 700625eaca9SLaurent Vivier *namespace ? namespace : "1"); 701bdd6a90aSFam Zheng } 702bdd6a90aSFam Zheng } 703bdd6a90aSFam Zheng 704bdd6a90aSFam Zheng static int nvme_enable_disable_write_cache(BlockDriverState *bs, bool enable, 705bdd6a90aSFam Zheng Error **errp) 706bdd6a90aSFam Zheng { 707bdd6a90aSFam Zheng int ret; 708bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 709bdd6a90aSFam Zheng NvmeCmd cmd = { 710bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_SET_FEATURES, 711bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 712bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(0x06), 713bdd6a90aSFam Zheng .cdw11 = cpu_to_le32(enable ? 0x01 : 0x00), 714bdd6a90aSFam Zheng }; 715bdd6a90aSFam Zheng 716bdd6a90aSFam Zheng ret = nvme_cmd_sync(bs, s->queues[0], &cmd); 717bdd6a90aSFam Zheng if (ret) { 718bdd6a90aSFam Zheng error_setg(errp, "Failed to configure NVMe write cache"); 719bdd6a90aSFam Zheng } 720bdd6a90aSFam Zheng return ret; 721bdd6a90aSFam Zheng } 722bdd6a90aSFam Zheng 723bdd6a90aSFam Zheng static void nvme_close(BlockDriverState *bs) 724bdd6a90aSFam Zheng { 725bdd6a90aSFam Zheng int i; 726bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 727bdd6a90aSFam Zheng 728bdd6a90aSFam Zheng for (i = 0; i < s->nr_queues; ++i) { 729bdd6a90aSFam Zheng nvme_free_queue_pair(bs, s->queues[i]); 730bdd6a90aSFam Zheng } 7319582f357SFam Zheng g_free(s->queues); 732bdd6a90aSFam Zheng aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier, 733bdd6a90aSFam Zheng false, NULL, NULL); 7349582f357SFam Zheng event_notifier_cleanup(&s->irq_notifier); 735bdd6a90aSFam Zheng qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->regs, 0, NVME_BAR_SIZE); 736bdd6a90aSFam Zheng qemu_vfio_close(s->vfio); 737cc61b074SMax Reitz 738cc61b074SMax Reitz g_free(s->device); 739bdd6a90aSFam Zheng } 740bdd6a90aSFam Zheng 741bdd6a90aSFam Zheng static int nvme_file_open(BlockDriverState *bs, QDict *options, int flags, 742bdd6a90aSFam Zheng Error **errp) 743bdd6a90aSFam Zheng { 744bdd6a90aSFam Zheng const char *device; 745bdd6a90aSFam Zheng QemuOpts *opts; 746bdd6a90aSFam Zheng int namespace; 747bdd6a90aSFam Zheng int ret; 748bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 749bdd6a90aSFam Zheng 750bdd6a90aSFam Zheng opts = qemu_opts_create(&runtime_opts, NULL, 0, &error_abort); 751bdd6a90aSFam Zheng qemu_opts_absorb_qdict(opts, options, &error_abort); 752bdd6a90aSFam Zheng device = qemu_opt_get(opts, NVME_BLOCK_OPT_DEVICE); 753bdd6a90aSFam Zheng if (!device) { 754bdd6a90aSFam Zheng error_setg(errp, "'" NVME_BLOCK_OPT_DEVICE "' option is required"); 755bdd6a90aSFam Zheng qemu_opts_del(opts); 756bdd6a90aSFam Zheng return -EINVAL; 757bdd6a90aSFam Zheng } 758bdd6a90aSFam Zheng 759bdd6a90aSFam Zheng namespace = qemu_opt_get_number(opts, NVME_BLOCK_OPT_NAMESPACE, 1); 760bdd6a90aSFam Zheng ret = nvme_init(bs, device, namespace, errp); 761bdd6a90aSFam Zheng qemu_opts_del(opts); 762bdd6a90aSFam Zheng if (ret) { 763bdd6a90aSFam Zheng goto fail; 764bdd6a90aSFam Zheng } 765bdd6a90aSFam Zheng if (flags & BDRV_O_NOCACHE) { 766bdd6a90aSFam Zheng if (!s->write_cache_supported) { 767bdd6a90aSFam Zheng error_setg(errp, 768bdd6a90aSFam Zheng "NVMe controller doesn't support write cache configuration"); 769bdd6a90aSFam Zheng ret = -EINVAL; 770bdd6a90aSFam Zheng } else { 771bdd6a90aSFam Zheng ret = nvme_enable_disable_write_cache(bs, !(flags & BDRV_O_NOCACHE), 772bdd6a90aSFam Zheng errp); 773bdd6a90aSFam Zheng } 774bdd6a90aSFam Zheng if (ret) { 775bdd6a90aSFam Zheng goto fail; 776bdd6a90aSFam Zheng } 777bdd6a90aSFam Zheng } 778bdd6a90aSFam Zheng bs->supported_write_flags = BDRV_REQ_FUA; 779bdd6a90aSFam Zheng return 0; 780bdd6a90aSFam Zheng fail: 781bdd6a90aSFam Zheng nvme_close(bs); 782bdd6a90aSFam Zheng return ret; 783bdd6a90aSFam Zheng } 784bdd6a90aSFam Zheng 785bdd6a90aSFam Zheng static int64_t nvme_getlength(BlockDriverState *bs) 786bdd6a90aSFam Zheng { 787bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 788bdd6a90aSFam Zheng 789bdd6a90aSFam Zheng return s->nsze << BDRV_SECTOR_BITS; 790bdd6a90aSFam Zheng } 791bdd6a90aSFam Zheng 792bdd6a90aSFam Zheng /* Called with s->dma_map_lock */ 793bdd6a90aSFam Zheng static coroutine_fn int nvme_cmd_unmap_qiov(BlockDriverState *bs, 794bdd6a90aSFam Zheng QEMUIOVector *qiov) 795bdd6a90aSFam Zheng { 796bdd6a90aSFam Zheng int r = 0; 797bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 798bdd6a90aSFam Zheng 799bdd6a90aSFam Zheng s->dma_map_count -= qiov->size; 800bdd6a90aSFam Zheng if (!s->dma_map_count && !qemu_co_queue_empty(&s->dma_flush_queue)) { 801bdd6a90aSFam Zheng r = qemu_vfio_dma_reset_temporary(s->vfio); 802bdd6a90aSFam Zheng if (!r) { 803bdd6a90aSFam Zheng qemu_co_queue_restart_all(&s->dma_flush_queue); 804bdd6a90aSFam Zheng } 805bdd6a90aSFam Zheng } 806bdd6a90aSFam Zheng return r; 807bdd6a90aSFam Zheng } 808bdd6a90aSFam Zheng 809bdd6a90aSFam Zheng /* Called with s->dma_map_lock */ 810bdd6a90aSFam Zheng static coroutine_fn int nvme_cmd_map_qiov(BlockDriverState *bs, NvmeCmd *cmd, 811bdd6a90aSFam Zheng NVMeRequest *req, QEMUIOVector *qiov) 812bdd6a90aSFam Zheng { 813bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 814bdd6a90aSFam Zheng uint64_t *pagelist = req->prp_list_page; 815bdd6a90aSFam Zheng int i, j, r; 816bdd6a90aSFam Zheng int entries = 0; 817bdd6a90aSFam Zheng 818bdd6a90aSFam Zheng assert(qiov->size); 819bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(qiov->size, s->page_size)); 820bdd6a90aSFam Zheng assert(qiov->size / s->page_size <= s->page_size / sizeof(uint64_t)); 821bdd6a90aSFam Zheng for (i = 0; i < qiov->niov; ++i) { 822bdd6a90aSFam Zheng bool retry = true; 823bdd6a90aSFam Zheng uint64_t iova; 824bdd6a90aSFam Zheng try_map: 825bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, 826bdd6a90aSFam Zheng qiov->iov[i].iov_base, 827bdd6a90aSFam Zheng qiov->iov[i].iov_len, 828bdd6a90aSFam Zheng true, &iova); 829bdd6a90aSFam Zheng if (r == -ENOMEM && retry) { 830bdd6a90aSFam Zheng retry = false; 831bdd6a90aSFam Zheng trace_nvme_dma_flush_queue_wait(s); 832bdd6a90aSFam Zheng if (s->dma_map_count) { 833bdd6a90aSFam Zheng trace_nvme_dma_map_flush(s); 834bdd6a90aSFam Zheng qemu_co_queue_wait(&s->dma_flush_queue, &s->dma_map_lock); 835bdd6a90aSFam Zheng } else { 836bdd6a90aSFam Zheng r = qemu_vfio_dma_reset_temporary(s->vfio); 837bdd6a90aSFam Zheng if (r) { 838bdd6a90aSFam Zheng goto fail; 839bdd6a90aSFam Zheng } 840bdd6a90aSFam Zheng } 841bdd6a90aSFam Zheng goto try_map; 842bdd6a90aSFam Zheng } 843bdd6a90aSFam Zheng if (r) { 844bdd6a90aSFam Zheng goto fail; 845bdd6a90aSFam Zheng } 846bdd6a90aSFam Zheng 847bdd6a90aSFam Zheng for (j = 0; j < qiov->iov[i].iov_len / s->page_size; j++) { 8482916405aSLi Feng pagelist[entries++] = cpu_to_le64(iova + j * s->page_size); 849bdd6a90aSFam Zheng } 850bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov_iov(s, i, qiov->iov[i].iov_base, 851bdd6a90aSFam Zheng qiov->iov[i].iov_len / s->page_size); 852bdd6a90aSFam Zheng } 853bdd6a90aSFam Zheng 854bdd6a90aSFam Zheng s->dma_map_count += qiov->size; 855bdd6a90aSFam Zheng 856bdd6a90aSFam Zheng assert(entries <= s->page_size / sizeof(uint64_t)); 857bdd6a90aSFam Zheng switch (entries) { 858bdd6a90aSFam Zheng case 0: 859bdd6a90aSFam Zheng abort(); 860bdd6a90aSFam Zheng case 1: 8612916405aSLi Feng cmd->prp1 = pagelist[0]; 862bdd6a90aSFam Zheng cmd->prp2 = 0; 863bdd6a90aSFam Zheng break; 864bdd6a90aSFam Zheng case 2: 8652916405aSLi Feng cmd->prp1 = pagelist[0]; 8662916405aSLi Feng cmd->prp2 = pagelist[1]; 867bdd6a90aSFam Zheng break; 868bdd6a90aSFam Zheng default: 8692916405aSLi Feng cmd->prp1 = pagelist[0]; 8702916405aSLi Feng cmd->prp2 = cpu_to_le64(req->prp_list_iova + sizeof(uint64_t)); 871bdd6a90aSFam Zheng break; 872bdd6a90aSFam Zheng } 873bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov(s, cmd, req, qiov, entries); 874bdd6a90aSFam Zheng for (i = 0; i < entries; ++i) { 875bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov_pages(s, i, pagelist[i]); 876bdd6a90aSFam Zheng } 877bdd6a90aSFam Zheng return 0; 878bdd6a90aSFam Zheng fail: 879bdd6a90aSFam Zheng /* No need to unmap [0 - i) iovs even if we've failed, since we don't 880bdd6a90aSFam Zheng * increment s->dma_map_count. This is okay for fixed mapping memory areas 881bdd6a90aSFam Zheng * because they are already mapped before calling this function; for 882bdd6a90aSFam Zheng * temporary mappings, a later nvme_cmd_(un)map_qiov will reclaim by 883bdd6a90aSFam Zheng * calling qemu_vfio_dma_reset_temporary when necessary. */ 884bdd6a90aSFam Zheng return r; 885bdd6a90aSFam Zheng } 886bdd6a90aSFam Zheng 887bdd6a90aSFam Zheng typedef struct { 888bdd6a90aSFam Zheng Coroutine *co; 889bdd6a90aSFam Zheng int ret; 890bdd6a90aSFam Zheng AioContext *ctx; 891bdd6a90aSFam Zheng } NVMeCoData; 892bdd6a90aSFam Zheng 893bdd6a90aSFam Zheng static void nvme_rw_cb_bh(void *opaque) 894bdd6a90aSFam Zheng { 895bdd6a90aSFam Zheng NVMeCoData *data = opaque; 896bdd6a90aSFam Zheng qemu_coroutine_enter(data->co); 897bdd6a90aSFam Zheng } 898bdd6a90aSFam Zheng 899bdd6a90aSFam Zheng static void nvme_rw_cb(void *opaque, int ret) 900bdd6a90aSFam Zheng { 901bdd6a90aSFam Zheng NVMeCoData *data = opaque; 902bdd6a90aSFam Zheng data->ret = ret; 903bdd6a90aSFam Zheng if (!data->co) { 904bdd6a90aSFam Zheng /* The rw coroutine hasn't yielded, don't try to enter. */ 905bdd6a90aSFam Zheng return; 906bdd6a90aSFam Zheng } 907bdd6a90aSFam Zheng aio_bh_schedule_oneshot(data->ctx, nvme_rw_cb_bh, data); 908bdd6a90aSFam Zheng } 909bdd6a90aSFam Zheng 910bdd6a90aSFam Zheng static coroutine_fn int nvme_co_prw_aligned(BlockDriverState *bs, 911bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 912bdd6a90aSFam Zheng QEMUIOVector *qiov, 913bdd6a90aSFam Zheng bool is_write, 914bdd6a90aSFam Zheng int flags) 915bdd6a90aSFam Zheng { 916bdd6a90aSFam Zheng int r; 917bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 918bdd6a90aSFam Zheng NVMeQueuePair *ioq = s->queues[1]; 919bdd6a90aSFam Zheng NVMeRequest *req; 920bdd6a90aSFam Zheng uint32_t cdw12 = (((bytes >> BDRV_SECTOR_BITS) - 1) & 0xFFFF) | 921bdd6a90aSFam Zheng (flags & BDRV_REQ_FUA ? 1 << 30 : 0); 922bdd6a90aSFam Zheng NvmeCmd cmd = { 923bdd6a90aSFam Zheng .opcode = is_write ? NVME_CMD_WRITE : NVME_CMD_READ, 924bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 925bdd6a90aSFam Zheng .cdw10 = cpu_to_le32((offset >> BDRV_SECTOR_BITS) & 0xFFFFFFFF), 926bdd6a90aSFam Zheng .cdw11 = cpu_to_le32(((offset >> BDRV_SECTOR_BITS) >> 32) & 0xFFFFFFFF), 927bdd6a90aSFam Zheng .cdw12 = cpu_to_le32(cdw12), 928bdd6a90aSFam Zheng }; 929bdd6a90aSFam Zheng NVMeCoData data = { 930bdd6a90aSFam Zheng .ctx = bdrv_get_aio_context(bs), 931bdd6a90aSFam Zheng .ret = -EINPROGRESS, 932bdd6a90aSFam Zheng }; 933bdd6a90aSFam Zheng 934bdd6a90aSFam Zheng trace_nvme_prw_aligned(s, is_write, offset, bytes, flags, qiov->niov); 935bdd6a90aSFam Zheng assert(s->nr_queues > 1); 936bdd6a90aSFam Zheng req = nvme_get_free_req(ioq); 937bdd6a90aSFam Zheng assert(req); 938bdd6a90aSFam Zheng 939bdd6a90aSFam Zheng qemu_co_mutex_lock(&s->dma_map_lock); 940bdd6a90aSFam Zheng r = nvme_cmd_map_qiov(bs, &cmd, req, qiov); 941bdd6a90aSFam Zheng qemu_co_mutex_unlock(&s->dma_map_lock); 942bdd6a90aSFam Zheng if (r) { 943bdd6a90aSFam Zheng req->busy = false; 944bdd6a90aSFam Zheng return r; 945bdd6a90aSFam Zheng } 946bdd6a90aSFam Zheng nvme_submit_command(s, ioq, req, &cmd, nvme_rw_cb, &data); 947bdd6a90aSFam Zheng 948bdd6a90aSFam Zheng data.co = qemu_coroutine_self(); 949bdd6a90aSFam Zheng while (data.ret == -EINPROGRESS) { 950bdd6a90aSFam Zheng qemu_coroutine_yield(); 951bdd6a90aSFam Zheng } 952bdd6a90aSFam Zheng 953bdd6a90aSFam Zheng qemu_co_mutex_lock(&s->dma_map_lock); 954bdd6a90aSFam Zheng r = nvme_cmd_unmap_qiov(bs, qiov); 955bdd6a90aSFam Zheng qemu_co_mutex_unlock(&s->dma_map_lock); 956bdd6a90aSFam Zheng if (r) { 957bdd6a90aSFam Zheng return r; 958bdd6a90aSFam Zheng } 959bdd6a90aSFam Zheng 960bdd6a90aSFam Zheng trace_nvme_rw_done(s, is_write, offset, bytes, data.ret); 961bdd6a90aSFam Zheng return data.ret; 962bdd6a90aSFam Zheng } 963bdd6a90aSFam Zheng 964bdd6a90aSFam Zheng static inline bool nvme_qiov_aligned(BlockDriverState *bs, 965bdd6a90aSFam Zheng const QEMUIOVector *qiov) 966bdd6a90aSFam Zheng { 967bdd6a90aSFam Zheng int i; 968bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 969bdd6a90aSFam Zheng 970bdd6a90aSFam Zheng for (i = 0; i < qiov->niov; ++i) { 971bdd6a90aSFam Zheng if (!QEMU_PTR_IS_ALIGNED(qiov->iov[i].iov_base, s->page_size) || 972bdd6a90aSFam Zheng !QEMU_IS_ALIGNED(qiov->iov[i].iov_len, s->page_size)) { 973bdd6a90aSFam Zheng trace_nvme_qiov_unaligned(qiov, i, qiov->iov[i].iov_base, 974bdd6a90aSFam Zheng qiov->iov[i].iov_len, s->page_size); 975bdd6a90aSFam Zheng return false; 976bdd6a90aSFam Zheng } 977bdd6a90aSFam Zheng } 978bdd6a90aSFam Zheng return true; 979bdd6a90aSFam Zheng } 980bdd6a90aSFam Zheng 981bdd6a90aSFam Zheng static int nvme_co_prw(BlockDriverState *bs, uint64_t offset, uint64_t bytes, 982bdd6a90aSFam Zheng QEMUIOVector *qiov, bool is_write, int flags) 983bdd6a90aSFam Zheng { 984bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 985bdd6a90aSFam Zheng int r; 986bdd6a90aSFam Zheng uint8_t *buf = NULL; 987bdd6a90aSFam Zheng QEMUIOVector local_qiov; 988bdd6a90aSFam Zheng 989bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(offset, s->page_size)); 990bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(bytes, s->page_size)); 991bdd6a90aSFam Zheng assert(bytes <= s->max_transfer); 992bdd6a90aSFam Zheng if (nvme_qiov_aligned(bs, qiov)) { 993bdd6a90aSFam Zheng return nvme_co_prw_aligned(bs, offset, bytes, qiov, is_write, flags); 994bdd6a90aSFam Zheng } 995bdd6a90aSFam Zheng trace_nvme_prw_buffered(s, offset, bytes, qiov->niov, is_write); 996bdd6a90aSFam Zheng buf = qemu_try_blockalign(bs, bytes); 997bdd6a90aSFam Zheng 998bdd6a90aSFam Zheng if (!buf) { 999bdd6a90aSFam Zheng return -ENOMEM; 1000bdd6a90aSFam Zheng } 1001bdd6a90aSFam Zheng qemu_iovec_init(&local_qiov, 1); 1002bdd6a90aSFam Zheng if (is_write) { 1003bdd6a90aSFam Zheng qemu_iovec_to_buf(qiov, 0, buf, bytes); 1004bdd6a90aSFam Zheng } 1005bdd6a90aSFam Zheng qemu_iovec_add(&local_qiov, buf, bytes); 1006bdd6a90aSFam Zheng r = nvme_co_prw_aligned(bs, offset, bytes, &local_qiov, is_write, flags); 1007bdd6a90aSFam Zheng qemu_iovec_destroy(&local_qiov); 1008bdd6a90aSFam Zheng if (!r && !is_write) { 1009bdd6a90aSFam Zheng qemu_iovec_from_buf(qiov, 0, buf, bytes); 1010bdd6a90aSFam Zheng } 1011bdd6a90aSFam Zheng qemu_vfree(buf); 1012bdd6a90aSFam Zheng return r; 1013bdd6a90aSFam Zheng } 1014bdd6a90aSFam Zheng 1015bdd6a90aSFam Zheng static coroutine_fn int nvme_co_preadv(BlockDriverState *bs, 1016bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 1017bdd6a90aSFam Zheng QEMUIOVector *qiov, int flags) 1018bdd6a90aSFam Zheng { 1019bdd6a90aSFam Zheng return nvme_co_prw(bs, offset, bytes, qiov, false, flags); 1020bdd6a90aSFam Zheng } 1021bdd6a90aSFam Zheng 1022bdd6a90aSFam Zheng static coroutine_fn int nvme_co_pwritev(BlockDriverState *bs, 1023bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 1024bdd6a90aSFam Zheng QEMUIOVector *qiov, int flags) 1025bdd6a90aSFam Zheng { 1026bdd6a90aSFam Zheng return nvme_co_prw(bs, offset, bytes, qiov, true, flags); 1027bdd6a90aSFam Zheng } 1028bdd6a90aSFam Zheng 1029bdd6a90aSFam Zheng static coroutine_fn int nvme_co_flush(BlockDriverState *bs) 1030bdd6a90aSFam Zheng { 1031bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1032bdd6a90aSFam Zheng NVMeQueuePair *ioq = s->queues[1]; 1033bdd6a90aSFam Zheng NVMeRequest *req; 1034bdd6a90aSFam Zheng NvmeCmd cmd = { 1035bdd6a90aSFam Zheng .opcode = NVME_CMD_FLUSH, 1036bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 1037bdd6a90aSFam Zheng }; 1038bdd6a90aSFam Zheng NVMeCoData data = { 1039bdd6a90aSFam Zheng .ctx = bdrv_get_aio_context(bs), 1040bdd6a90aSFam Zheng .ret = -EINPROGRESS, 1041bdd6a90aSFam Zheng }; 1042bdd6a90aSFam Zheng 1043bdd6a90aSFam Zheng assert(s->nr_queues > 1); 1044bdd6a90aSFam Zheng req = nvme_get_free_req(ioq); 1045bdd6a90aSFam Zheng assert(req); 1046bdd6a90aSFam Zheng nvme_submit_command(s, ioq, req, &cmd, nvme_rw_cb, &data); 1047bdd6a90aSFam Zheng 1048bdd6a90aSFam Zheng data.co = qemu_coroutine_self(); 1049bdd6a90aSFam Zheng if (data.ret == -EINPROGRESS) { 1050bdd6a90aSFam Zheng qemu_coroutine_yield(); 1051bdd6a90aSFam Zheng } 1052bdd6a90aSFam Zheng 1053bdd6a90aSFam Zheng return data.ret; 1054bdd6a90aSFam Zheng } 1055bdd6a90aSFam Zheng 1056bdd6a90aSFam Zheng 1057bdd6a90aSFam Zheng static int nvme_reopen_prepare(BDRVReopenState *reopen_state, 1058bdd6a90aSFam Zheng BlockReopenQueue *queue, Error **errp) 1059bdd6a90aSFam Zheng { 1060bdd6a90aSFam Zheng return 0; 1061bdd6a90aSFam Zheng } 1062bdd6a90aSFam Zheng 1063998b3a1eSMax Reitz static void nvme_refresh_filename(BlockDriverState *bs) 1064bdd6a90aSFam Zheng { 1065cc61b074SMax Reitz BDRVNVMeState *s = bs->opaque; 1066bdd6a90aSFam Zheng 1067cc61b074SMax Reitz snprintf(bs->exact_filename, sizeof(bs->exact_filename), "nvme://%s/%i", 1068cc61b074SMax Reitz s->device, s->nsid); 1069bdd6a90aSFam Zheng } 1070bdd6a90aSFam Zheng 1071bdd6a90aSFam Zheng static void nvme_refresh_limits(BlockDriverState *bs, Error **errp) 1072bdd6a90aSFam Zheng { 1073bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1074bdd6a90aSFam Zheng 1075bdd6a90aSFam Zheng bs->bl.opt_mem_alignment = s->page_size; 1076bdd6a90aSFam Zheng bs->bl.request_alignment = s->page_size; 1077bdd6a90aSFam Zheng bs->bl.max_transfer = s->max_transfer; 1078bdd6a90aSFam Zheng } 1079bdd6a90aSFam Zheng 1080bdd6a90aSFam Zheng static void nvme_detach_aio_context(BlockDriverState *bs) 1081bdd6a90aSFam Zheng { 1082bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1083bdd6a90aSFam Zheng 1084bdd6a90aSFam Zheng aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier, 1085bdd6a90aSFam Zheng false, NULL, NULL); 1086bdd6a90aSFam Zheng } 1087bdd6a90aSFam Zheng 1088bdd6a90aSFam Zheng static void nvme_attach_aio_context(BlockDriverState *bs, 1089bdd6a90aSFam Zheng AioContext *new_context) 1090bdd6a90aSFam Zheng { 1091bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1092bdd6a90aSFam Zheng 1093bdd6a90aSFam Zheng s->aio_context = new_context; 1094bdd6a90aSFam Zheng aio_set_event_notifier(new_context, &s->irq_notifier, 1095bdd6a90aSFam Zheng false, nvme_handle_event, nvme_poll_cb); 1096bdd6a90aSFam Zheng } 1097bdd6a90aSFam Zheng 1098bdd6a90aSFam Zheng static void nvme_aio_plug(BlockDriverState *bs) 1099bdd6a90aSFam Zheng { 1100bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 11012f0d8947SPaolo Bonzini assert(!s->plugged); 11022f0d8947SPaolo Bonzini s->plugged = true; 1103bdd6a90aSFam Zheng } 1104bdd6a90aSFam Zheng 1105bdd6a90aSFam Zheng static void nvme_aio_unplug(BlockDriverState *bs) 1106bdd6a90aSFam Zheng { 1107bdd6a90aSFam Zheng int i; 1108bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1109bdd6a90aSFam Zheng assert(s->plugged); 11102f0d8947SPaolo Bonzini s->plugged = false; 1111bdd6a90aSFam Zheng for (i = 1; i < s->nr_queues; i++) { 1112bdd6a90aSFam Zheng NVMeQueuePair *q = s->queues[i]; 1113bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 1114bdd6a90aSFam Zheng nvme_kick(s, q); 1115bdd6a90aSFam Zheng nvme_process_completion(s, q); 1116bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 1117bdd6a90aSFam Zheng } 1118bdd6a90aSFam Zheng } 1119bdd6a90aSFam Zheng 11209ed61612SFam Zheng static void nvme_register_buf(BlockDriverState *bs, void *host, size_t size) 11219ed61612SFam Zheng { 11229ed61612SFam Zheng int ret; 11239ed61612SFam Zheng BDRVNVMeState *s = bs->opaque; 11249ed61612SFam Zheng 11259ed61612SFam Zheng ret = qemu_vfio_dma_map(s->vfio, host, size, false, NULL); 11269ed61612SFam Zheng if (ret) { 11279ed61612SFam Zheng /* FIXME: we may run out of IOVA addresses after repeated 11289ed61612SFam Zheng * bdrv_register_buf/bdrv_unregister_buf, because nvme_vfio_dma_unmap 11299ed61612SFam Zheng * doesn't reclaim addresses for fixed mappings. */ 11309ed61612SFam Zheng error_report("nvme_register_buf failed: %s", strerror(-ret)); 11319ed61612SFam Zheng } 11329ed61612SFam Zheng } 11339ed61612SFam Zheng 11349ed61612SFam Zheng static void nvme_unregister_buf(BlockDriverState *bs, void *host) 11359ed61612SFam Zheng { 11369ed61612SFam Zheng BDRVNVMeState *s = bs->opaque; 11379ed61612SFam Zheng 11389ed61612SFam Zheng qemu_vfio_dma_unmap(s->vfio, host); 11399ed61612SFam Zheng } 11409ed61612SFam Zheng 11412654267cSMax Reitz static const char *const nvme_strong_runtime_opts[] = { 11422654267cSMax Reitz NVME_BLOCK_OPT_DEVICE, 11432654267cSMax Reitz NVME_BLOCK_OPT_NAMESPACE, 11442654267cSMax Reitz 11452654267cSMax Reitz NULL 11462654267cSMax Reitz }; 11472654267cSMax Reitz 1148bdd6a90aSFam Zheng static BlockDriver bdrv_nvme = { 1149bdd6a90aSFam Zheng .format_name = "nvme", 1150bdd6a90aSFam Zheng .protocol_name = "nvme", 1151bdd6a90aSFam Zheng .instance_size = sizeof(BDRVNVMeState), 1152bdd6a90aSFam Zheng 1153bdd6a90aSFam Zheng .bdrv_parse_filename = nvme_parse_filename, 1154bdd6a90aSFam Zheng .bdrv_file_open = nvme_file_open, 1155bdd6a90aSFam Zheng .bdrv_close = nvme_close, 1156bdd6a90aSFam Zheng .bdrv_getlength = nvme_getlength, 1157bdd6a90aSFam Zheng 1158bdd6a90aSFam Zheng .bdrv_co_preadv = nvme_co_preadv, 1159bdd6a90aSFam Zheng .bdrv_co_pwritev = nvme_co_pwritev, 1160bdd6a90aSFam Zheng .bdrv_co_flush_to_disk = nvme_co_flush, 1161bdd6a90aSFam Zheng .bdrv_reopen_prepare = nvme_reopen_prepare, 1162bdd6a90aSFam Zheng 1163bdd6a90aSFam Zheng .bdrv_refresh_filename = nvme_refresh_filename, 1164bdd6a90aSFam Zheng .bdrv_refresh_limits = nvme_refresh_limits, 11652654267cSMax Reitz .strong_runtime_opts = nvme_strong_runtime_opts, 1166bdd6a90aSFam Zheng 1167bdd6a90aSFam Zheng .bdrv_detach_aio_context = nvme_detach_aio_context, 1168bdd6a90aSFam Zheng .bdrv_attach_aio_context = nvme_attach_aio_context, 1169bdd6a90aSFam Zheng 1170bdd6a90aSFam Zheng .bdrv_io_plug = nvme_aio_plug, 1171bdd6a90aSFam Zheng .bdrv_io_unplug = nvme_aio_unplug, 11729ed61612SFam Zheng 11739ed61612SFam Zheng .bdrv_register_buf = nvme_register_buf, 11749ed61612SFam Zheng .bdrv_unregister_buf = nvme_unregister_buf, 1175bdd6a90aSFam Zheng }; 1176bdd6a90aSFam Zheng 1177bdd6a90aSFam Zheng static void bdrv_nvme_init(void) 1178bdd6a90aSFam Zheng { 1179bdd6a90aSFam Zheng bdrv_register(&bdrv_nvme); 1180bdd6a90aSFam Zheng } 1181bdd6a90aSFam Zheng 1182bdd6a90aSFam Zheng block_init(bdrv_nvme_init); 1183