1bdd6a90aSFam Zheng /* 2bdd6a90aSFam Zheng * NVMe block driver based on vfio 3bdd6a90aSFam Zheng * 4bdd6a90aSFam Zheng * Copyright 2016 - 2018 Red Hat, Inc. 5bdd6a90aSFam Zheng * 6bdd6a90aSFam Zheng * Authors: 7bdd6a90aSFam Zheng * Fam Zheng <famz@redhat.com> 8bdd6a90aSFam Zheng * Paolo Bonzini <pbonzini@redhat.com> 9bdd6a90aSFam Zheng * 10bdd6a90aSFam Zheng * This work is licensed under the terms of the GNU GPL, version 2 or later. 11bdd6a90aSFam Zheng * See the COPYING file in the top-level directory. 12bdd6a90aSFam Zheng */ 13bdd6a90aSFam Zheng 14bdd6a90aSFam Zheng #include "qemu/osdep.h" 15bdd6a90aSFam Zheng #include <linux/vfio.h> 16bdd6a90aSFam Zheng #include "qapi/error.h" 17bdd6a90aSFam Zheng #include "qapi/qmp/qdict.h" 18bdd6a90aSFam Zheng #include "qapi/qmp/qstring.h" 19bdd6a90aSFam Zheng #include "qemu/error-report.h" 20db725815SMarkus Armbruster #include "qemu/main-loop.h" 210b8fa32fSMarkus Armbruster #include "qemu/module.h" 22bdd6a90aSFam Zheng #include "qemu/cutils.h" 23922a01a0SMarkus Armbruster #include "qemu/option.h" 24bdd6a90aSFam Zheng #include "qemu/vfio-helpers.h" 25bdd6a90aSFam Zheng #include "block/block_int.h" 26e4ec5ad4SPavel Dovgalyuk #include "sysemu/replay.h" 27bdd6a90aSFam Zheng #include "trace.h" 28bdd6a90aSFam Zheng 29a3d9a352SFam Zheng #include "block/nvme.h" 30bdd6a90aSFam Zheng 31bdd6a90aSFam Zheng #define NVME_SQ_ENTRY_BYTES 64 32bdd6a90aSFam Zheng #define NVME_CQ_ENTRY_BYTES 16 33bdd6a90aSFam Zheng #define NVME_QUEUE_SIZE 128 34bdd6a90aSFam Zheng #define NVME_BAR_SIZE 8192 35bdd6a90aSFam Zheng 361086e95dSStefan Hajnoczi /* 371086e95dSStefan Hajnoczi * We have to leave one slot empty as that is the full queue case where 381086e95dSStefan Hajnoczi * head == tail + 1. 391086e95dSStefan Hajnoczi */ 401086e95dSStefan Hajnoczi #define NVME_NUM_REQS (NVME_QUEUE_SIZE - 1) 411086e95dSStefan Hajnoczi 42b75fd5f5SStefan Hajnoczi typedef struct BDRVNVMeState BDRVNVMeState; 43b75fd5f5SStefan Hajnoczi 44bdd6a90aSFam Zheng typedef struct { 45bdd6a90aSFam Zheng int32_t head, tail; 46bdd6a90aSFam Zheng uint8_t *queue; 47bdd6a90aSFam Zheng uint64_t iova; 48bdd6a90aSFam Zheng /* Hardware MMIO register */ 49bdd6a90aSFam Zheng volatile uint32_t *doorbell; 50bdd6a90aSFam Zheng } NVMeQueue; 51bdd6a90aSFam Zheng 52bdd6a90aSFam Zheng typedef struct { 53bdd6a90aSFam Zheng BlockCompletionFunc *cb; 54bdd6a90aSFam Zheng void *opaque; 55bdd6a90aSFam Zheng int cid; 56bdd6a90aSFam Zheng void *prp_list_page; 57bdd6a90aSFam Zheng uint64_t prp_list_iova; 581086e95dSStefan Hajnoczi int free_req_next; /* q->reqs[] index of next free req */ 59bdd6a90aSFam Zheng } NVMeRequest; 60bdd6a90aSFam Zheng 61bdd6a90aSFam Zheng typedef struct { 62bdd6a90aSFam Zheng QemuMutex lock; 63bdd6a90aSFam Zheng 64b75fd5f5SStefan Hajnoczi /* Read from I/O code path, initialized under BQL */ 65b75fd5f5SStefan Hajnoczi BDRVNVMeState *s; 66bdd6a90aSFam Zheng int index; 67b75fd5f5SStefan Hajnoczi 68b75fd5f5SStefan Hajnoczi /* Fields protected by BQL */ 69bdd6a90aSFam Zheng uint8_t *prp_list_pages; 70bdd6a90aSFam Zheng 71bdd6a90aSFam Zheng /* Fields protected by @lock */ 72a5db74f3SStefan Hajnoczi CoQueue free_req_queue; 73bdd6a90aSFam Zheng NVMeQueue sq, cq; 74bdd6a90aSFam Zheng int cq_phase; 751086e95dSStefan Hajnoczi int free_req_head; 761086e95dSStefan Hajnoczi NVMeRequest reqs[NVME_NUM_REQS]; 77bdd6a90aSFam Zheng int need_kick; 78bdd6a90aSFam Zheng int inflight; 797838c67fSStefan Hajnoczi 807838c67fSStefan Hajnoczi /* Thread-safe, no lock necessary */ 817838c67fSStefan Hajnoczi QEMUBH *completion_bh; 82bdd6a90aSFam Zheng } NVMeQueuePair; 83bdd6a90aSFam Zheng 84bdd6a90aSFam Zheng /* Memory mapped registers */ 85bdd6a90aSFam Zheng typedef volatile struct { 86bdd6a90aSFam Zheng uint64_t cap; 87bdd6a90aSFam Zheng uint32_t vs; 88bdd6a90aSFam Zheng uint32_t intms; 89bdd6a90aSFam Zheng uint32_t intmc; 90bdd6a90aSFam Zheng uint32_t cc; 91bdd6a90aSFam Zheng uint32_t reserved0; 92bdd6a90aSFam Zheng uint32_t csts; 93bdd6a90aSFam Zheng uint32_t nssr; 94bdd6a90aSFam Zheng uint32_t aqa; 95bdd6a90aSFam Zheng uint64_t asq; 96bdd6a90aSFam Zheng uint64_t acq; 97bdd6a90aSFam Zheng uint32_t cmbloc; 98bdd6a90aSFam Zheng uint32_t cmbsz; 99bdd6a90aSFam Zheng uint8_t reserved1[0xec0]; 100bdd6a90aSFam Zheng uint8_t cmd_set_specfic[0x100]; 101bdd6a90aSFam Zheng uint32_t doorbells[]; 10283c68e14SThomas Huth } NVMeRegs; 103bdd6a90aSFam Zheng 104bdd6a90aSFam Zheng QEMU_BUILD_BUG_ON(offsetof(NVMeRegs, doorbells) != 0x1000); 105bdd6a90aSFam Zheng 10673159e52SPhilippe Mathieu-Daudé #define INDEX_ADMIN 0 10773159e52SPhilippe Mathieu-Daudé #define INDEX_IO(n) (1 + n) 10873159e52SPhilippe Mathieu-Daudé 109b75fd5f5SStefan Hajnoczi struct BDRVNVMeState { 110bdd6a90aSFam Zheng AioContext *aio_context; 111bdd6a90aSFam Zheng QEMUVFIOState *vfio; 112bdd6a90aSFam Zheng NVMeRegs *regs; 113bdd6a90aSFam Zheng /* The submission/completion queue pairs. 114bdd6a90aSFam Zheng * [0]: admin queue. 115bdd6a90aSFam Zheng * [1..]: io queues. 116bdd6a90aSFam Zheng */ 117bdd6a90aSFam Zheng NVMeQueuePair **queues; 118bdd6a90aSFam Zheng int nr_queues; 119bdd6a90aSFam Zheng size_t page_size; 120bdd6a90aSFam Zheng /* How many uint32_t elements does each doorbell entry take. */ 121bdd6a90aSFam Zheng size_t doorbell_scale; 122bdd6a90aSFam Zheng bool write_cache_supported; 123bdd6a90aSFam Zheng EventNotifier irq_notifier; 124118d1b6aSMaxim Levitsky 125bdd6a90aSFam Zheng uint64_t nsze; /* Namespace size reported by identify command */ 126bdd6a90aSFam Zheng int nsid; /* The namespace id to read/write data. */ 1271120407bSMax Reitz int blkshift; 128118d1b6aSMaxim Levitsky 129bdd6a90aSFam Zheng uint64_t max_transfer; 1302f0d8947SPaolo Bonzini bool plugged; 131bdd6a90aSFam Zheng 132e0dd95e3SMaxim Levitsky bool supports_write_zeroes; 133e87a09d6SMaxim Levitsky bool supports_discard; 134e0dd95e3SMaxim Levitsky 135bdd6a90aSFam Zheng CoMutex dma_map_lock; 136bdd6a90aSFam Zheng CoQueue dma_flush_queue; 137bdd6a90aSFam Zheng 138bdd6a90aSFam Zheng /* Total size of mapped qiov, accessed under dma_map_lock */ 139bdd6a90aSFam Zheng int dma_map_count; 140cc61b074SMax Reitz 141cc61b074SMax Reitz /* PCI address (required for nvme_refresh_filename()) */ 142cc61b074SMax Reitz char *device; 143b75fd5f5SStefan Hajnoczi }; 144bdd6a90aSFam Zheng 145bdd6a90aSFam Zheng #define NVME_BLOCK_OPT_DEVICE "device" 146bdd6a90aSFam Zheng #define NVME_BLOCK_OPT_NAMESPACE "namespace" 147bdd6a90aSFam Zheng 1487838c67fSStefan Hajnoczi static void nvme_process_completion_bh(void *opaque); 1497838c67fSStefan Hajnoczi 150bdd6a90aSFam Zheng static QemuOptsList runtime_opts = { 151bdd6a90aSFam Zheng .name = "nvme", 152bdd6a90aSFam Zheng .head = QTAILQ_HEAD_INITIALIZER(runtime_opts.head), 153bdd6a90aSFam Zheng .desc = { 154bdd6a90aSFam Zheng { 155bdd6a90aSFam Zheng .name = NVME_BLOCK_OPT_DEVICE, 156bdd6a90aSFam Zheng .type = QEMU_OPT_STRING, 157bdd6a90aSFam Zheng .help = "NVMe PCI device address", 158bdd6a90aSFam Zheng }, 159bdd6a90aSFam Zheng { 160bdd6a90aSFam Zheng .name = NVME_BLOCK_OPT_NAMESPACE, 161bdd6a90aSFam Zheng .type = QEMU_OPT_NUMBER, 162bdd6a90aSFam Zheng .help = "NVMe namespace", 163bdd6a90aSFam Zheng }, 164bdd6a90aSFam Zheng { /* end of list */ } 165bdd6a90aSFam Zheng }, 166bdd6a90aSFam Zheng }; 167bdd6a90aSFam Zheng 168bdd6a90aSFam Zheng static void nvme_init_queue(BlockDriverState *bs, NVMeQueue *q, 169bdd6a90aSFam Zheng int nentries, int entry_bytes, Error **errp) 170bdd6a90aSFam Zheng { 171bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 172bdd6a90aSFam Zheng size_t bytes; 173bdd6a90aSFam Zheng int r; 174bdd6a90aSFam Zheng 175bdd6a90aSFam Zheng bytes = ROUND_UP(nentries * entry_bytes, s->page_size); 176bdd6a90aSFam Zheng q->head = q->tail = 0; 177bdd6a90aSFam Zheng q->queue = qemu_try_blockalign0(bs, bytes); 178bdd6a90aSFam Zheng 179bdd6a90aSFam Zheng if (!q->queue) { 180bdd6a90aSFam Zheng error_setg(errp, "Cannot allocate queue"); 181bdd6a90aSFam Zheng return; 182bdd6a90aSFam Zheng } 183bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, q->queue, bytes, false, &q->iova); 184bdd6a90aSFam Zheng if (r) { 185bdd6a90aSFam Zheng error_setg(errp, "Cannot map queue"); 186bdd6a90aSFam Zheng } 187bdd6a90aSFam Zheng } 188bdd6a90aSFam Zheng 189b75fd5f5SStefan Hajnoczi static void nvme_free_queue_pair(NVMeQueuePair *q) 190bdd6a90aSFam Zheng { 1917838c67fSStefan Hajnoczi if (q->completion_bh) { 1927838c67fSStefan Hajnoczi qemu_bh_delete(q->completion_bh); 1937838c67fSStefan Hajnoczi } 194bdd6a90aSFam Zheng qemu_vfree(q->prp_list_pages); 195bdd6a90aSFam Zheng qemu_vfree(q->sq.queue); 196bdd6a90aSFam Zheng qemu_vfree(q->cq.queue); 197bdd6a90aSFam Zheng qemu_mutex_destroy(&q->lock); 198bdd6a90aSFam Zheng g_free(q); 199bdd6a90aSFam Zheng } 200bdd6a90aSFam Zheng 201bdd6a90aSFam Zheng static void nvme_free_req_queue_cb(void *opaque) 202bdd6a90aSFam Zheng { 203bdd6a90aSFam Zheng NVMeQueuePair *q = opaque; 204bdd6a90aSFam Zheng 205bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 206bdd6a90aSFam Zheng while (qemu_co_enter_next(&q->free_req_queue, &q->lock)) { 207bdd6a90aSFam Zheng /* Retry all pending requests */ 208bdd6a90aSFam Zheng } 209bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 210bdd6a90aSFam Zheng } 211bdd6a90aSFam Zheng 212bdd6a90aSFam Zheng static NVMeQueuePair *nvme_create_queue_pair(BlockDriverState *bs, 213bdd6a90aSFam Zheng int idx, int size, 214bdd6a90aSFam Zheng Error **errp) 215bdd6a90aSFam Zheng { 216bdd6a90aSFam Zheng int i, r; 217bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 218bdd6a90aSFam Zheng Error *local_err = NULL; 2190ea45f76SPhilippe Mathieu-Daudé NVMeQueuePair *q; 220bdd6a90aSFam Zheng uint64_t prp_list_iova; 221bdd6a90aSFam Zheng 2220ea45f76SPhilippe Mathieu-Daudé q = g_try_new0(NVMeQueuePair, 1); 2230ea45f76SPhilippe Mathieu-Daudé if (!q) { 2240ea45f76SPhilippe Mathieu-Daudé return NULL; 2250ea45f76SPhilippe Mathieu-Daudé } 2260ea45f76SPhilippe Mathieu-Daudé q->prp_list_pages = qemu_try_blockalign0(bs, 2270ea45f76SPhilippe Mathieu-Daudé s->page_size * NVME_NUM_REQS); 2280ea45f76SPhilippe Mathieu-Daudé if (!q->prp_list_pages) { 2290ea45f76SPhilippe Mathieu-Daudé goto fail; 2300ea45f76SPhilippe Mathieu-Daudé } 231bdd6a90aSFam Zheng qemu_mutex_init(&q->lock); 232b75fd5f5SStefan Hajnoczi q->s = s; 233bdd6a90aSFam Zheng q->index = idx; 234bdd6a90aSFam Zheng qemu_co_queue_init(&q->free_req_queue); 2357838c67fSStefan Hajnoczi q->completion_bh = aio_bh_new(bdrv_get_aio_context(bs), 2367838c67fSStefan Hajnoczi nvme_process_completion_bh, q); 237bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, q->prp_list_pages, 2381086e95dSStefan Hajnoczi s->page_size * NVME_NUM_REQS, 239bdd6a90aSFam Zheng false, &prp_list_iova); 240bdd6a90aSFam Zheng if (r) { 241bdd6a90aSFam Zheng goto fail; 242bdd6a90aSFam Zheng } 2431086e95dSStefan Hajnoczi q->free_req_head = -1; 2441086e95dSStefan Hajnoczi for (i = 0; i < NVME_NUM_REQS; i++) { 245bdd6a90aSFam Zheng NVMeRequest *req = &q->reqs[i]; 246bdd6a90aSFam Zheng req->cid = i + 1; 2471086e95dSStefan Hajnoczi req->free_req_next = q->free_req_head; 2481086e95dSStefan Hajnoczi q->free_req_head = i; 249bdd6a90aSFam Zheng req->prp_list_page = q->prp_list_pages + i * s->page_size; 250bdd6a90aSFam Zheng req->prp_list_iova = prp_list_iova + i * s->page_size; 251bdd6a90aSFam Zheng } 2521086e95dSStefan Hajnoczi 253bdd6a90aSFam Zheng nvme_init_queue(bs, &q->sq, size, NVME_SQ_ENTRY_BYTES, &local_err); 254bdd6a90aSFam Zheng if (local_err) { 255bdd6a90aSFam Zheng error_propagate(errp, local_err); 256bdd6a90aSFam Zheng goto fail; 257bdd6a90aSFam Zheng } 258bdd6a90aSFam Zheng q->sq.doorbell = &s->regs->doorbells[idx * 2 * s->doorbell_scale]; 259bdd6a90aSFam Zheng 260bdd6a90aSFam Zheng nvme_init_queue(bs, &q->cq, size, NVME_CQ_ENTRY_BYTES, &local_err); 261bdd6a90aSFam Zheng if (local_err) { 262bdd6a90aSFam Zheng error_propagate(errp, local_err); 263bdd6a90aSFam Zheng goto fail; 264bdd6a90aSFam Zheng } 265461bba04SMaxim Levitsky q->cq.doorbell = &s->regs->doorbells[(idx * 2 + 1) * s->doorbell_scale]; 266bdd6a90aSFam Zheng 267bdd6a90aSFam Zheng return q; 268bdd6a90aSFam Zheng fail: 269b75fd5f5SStefan Hajnoczi nvme_free_queue_pair(q); 270bdd6a90aSFam Zheng return NULL; 271bdd6a90aSFam Zheng } 272bdd6a90aSFam Zheng 273bdd6a90aSFam Zheng /* With q->lock */ 274b75fd5f5SStefan Hajnoczi static void nvme_kick(NVMeQueuePair *q) 275bdd6a90aSFam Zheng { 276b75fd5f5SStefan Hajnoczi BDRVNVMeState *s = q->s; 277b75fd5f5SStefan Hajnoczi 278bdd6a90aSFam Zheng if (s->plugged || !q->need_kick) { 279bdd6a90aSFam Zheng return; 280bdd6a90aSFam Zheng } 281bdd6a90aSFam Zheng trace_nvme_kick(s, q->index); 282bdd6a90aSFam Zheng assert(!(q->sq.tail & 0xFF00)); 283bdd6a90aSFam Zheng /* Fence the write to submission queue entry before notifying the device. */ 284bdd6a90aSFam Zheng smp_wmb(); 285bdd6a90aSFam Zheng *q->sq.doorbell = cpu_to_le32(q->sq.tail); 286bdd6a90aSFam Zheng q->inflight += q->need_kick; 287bdd6a90aSFam Zheng q->need_kick = 0; 288bdd6a90aSFam Zheng } 289bdd6a90aSFam Zheng 290bdd6a90aSFam Zheng /* Find a free request element if any, otherwise: 291bdd6a90aSFam Zheng * a) if in coroutine context, try to wait for one to become available; 292bdd6a90aSFam Zheng * b) if not in coroutine, return NULL; 293bdd6a90aSFam Zheng */ 294bdd6a90aSFam Zheng static NVMeRequest *nvme_get_free_req(NVMeQueuePair *q) 295bdd6a90aSFam Zheng { 2961086e95dSStefan Hajnoczi NVMeRequest *req; 297bdd6a90aSFam Zheng 298bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 2991086e95dSStefan Hajnoczi 3001086e95dSStefan Hajnoczi while (q->free_req_head == -1) { 301bdd6a90aSFam Zheng if (qemu_in_coroutine()) { 302bdd6a90aSFam Zheng trace_nvme_free_req_queue_wait(q); 303bdd6a90aSFam Zheng qemu_co_queue_wait(&q->free_req_queue, &q->lock); 304bdd6a90aSFam Zheng } else { 305bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 306bdd6a90aSFam Zheng return NULL; 307bdd6a90aSFam Zheng } 308bdd6a90aSFam Zheng } 3091086e95dSStefan Hajnoczi 3101086e95dSStefan Hajnoczi req = &q->reqs[q->free_req_head]; 3111086e95dSStefan Hajnoczi q->free_req_head = req->free_req_next; 3121086e95dSStefan Hajnoczi req->free_req_next = -1; 3131086e95dSStefan Hajnoczi 314bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 315bdd6a90aSFam Zheng return req; 316bdd6a90aSFam Zheng } 317bdd6a90aSFam Zheng 3181086e95dSStefan Hajnoczi /* With q->lock */ 3191086e95dSStefan Hajnoczi static void nvme_put_free_req_locked(NVMeQueuePair *q, NVMeRequest *req) 3201086e95dSStefan Hajnoczi { 3211086e95dSStefan Hajnoczi req->free_req_next = q->free_req_head; 3221086e95dSStefan Hajnoczi q->free_req_head = req - q->reqs; 3231086e95dSStefan Hajnoczi } 3241086e95dSStefan Hajnoczi 3251086e95dSStefan Hajnoczi /* With q->lock */ 326b75fd5f5SStefan Hajnoczi static void nvme_wake_free_req_locked(NVMeQueuePair *q) 3271086e95dSStefan Hajnoczi { 3281086e95dSStefan Hajnoczi if (!qemu_co_queue_empty(&q->free_req_queue)) { 329b75fd5f5SStefan Hajnoczi replay_bh_schedule_oneshot_event(q->s->aio_context, 3301086e95dSStefan Hajnoczi nvme_free_req_queue_cb, q); 3311086e95dSStefan Hajnoczi } 3321086e95dSStefan Hajnoczi } 3331086e95dSStefan Hajnoczi 3341086e95dSStefan Hajnoczi /* Insert a request in the freelist and wake waiters */ 335b75fd5f5SStefan Hajnoczi static void nvme_put_free_req_and_wake(NVMeQueuePair *q, NVMeRequest *req) 3361086e95dSStefan Hajnoczi { 3371086e95dSStefan Hajnoczi qemu_mutex_lock(&q->lock); 3381086e95dSStefan Hajnoczi nvme_put_free_req_locked(q, req); 339b75fd5f5SStefan Hajnoczi nvme_wake_free_req_locked(q); 3401086e95dSStefan Hajnoczi qemu_mutex_unlock(&q->lock); 3411086e95dSStefan Hajnoczi } 3421086e95dSStefan Hajnoczi 343bdd6a90aSFam Zheng static inline int nvme_translate_error(const NvmeCqe *c) 344bdd6a90aSFam Zheng { 345bdd6a90aSFam Zheng uint16_t status = (le16_to_cpu(c->status) >> 1) & 0xFF; 346bdd6a90aSFam Zheng if (status) { 347bdd6a90aSFam Zheng trace_nvme_error(le32_to_cpu(c->result), 348bdd6a90aSFam Zheng le16_to_cpu(c->sq_head), 349bdd6a90aSFam Zheng le16_to_cpu(c->sq_id), 350bdd6a90aSFam Zheng le16_to_cpu(c->cid), 351bdd6a90aSFam Zheng le16_to_cpu(status)); 352bdd6a90aSFam Zheng } 353bdd6a90aSFam Zheng switch (status) { 354bdd6a90aSFam Zheng case 0: 355bdd6a90aSFam Zheng return 0; 356bdd6a90aSFam Zheng case 1: 357bdd6a90aSFam Zheng return -ENOSYS; 358bdd6a90aSFam Zheng case 2: 359bdd6a90aSFam Zheng return -EINVAL; 360bdd6a90aSFam Zheng default: 361bdd6a90aSFam Zheng return -EIO; 362bdd6a90aSFam Zheng } 363bdd6a90aSFam Zheng } 364bdd6a90aSFam Zheng 365bdd6a90aSFam Zheng /* With q->lock */ 366b75fd5f5SStefan Hajnoczi static bool nvme_process_completion(NVMeQueuePair *q) 367bdd6a90aSFam Zheng { 368b75fd5f5SStefan Hajnoczi BDRVNVMeState *s = q->s; 369bdd6a90aSFam Zheng bool progress = false; 370bdd6a90aSFam Zheng NVMeRequest *preq; 371bdd6a90aSFam Zheng NVMeRequest req; 372bdd6a90aSFam Zheng NvmeCqe *c; 373bdd6a90aSFam Zheng 374bdd6a90aSFam Zheng trace_nvme_process_completion(s, q->index, q->inflight); 3757838c67fSStefan Hajnoczi if (s->plugged) { 3767838c67fSStefan Hajnoczi trace_nvme_process_completion_queue_plugged(s, q->index); 377bdd6a90aSFam Zheng return false; 378bdd6a90aSFam Zheng } 3797838c67fSStefan Hajnoczi 3807838c67fSStefan Hajnoczi /* 3817838c67fSStefan Hajnoczi * Support re-entrancy when a request cb() function invokes aio_poll(). 3827838c67fSStefan Hajnoczi * Pending completions must be visible to aio_poll() so that a cb() 3837838c67fSStefan Hajnoczi * function can wait for the completion of another request. 3847838c67fSStefan Hajnoczi * 3857838c67fSStefan Hajnoczi * The aio_poll() loop will execute our BH and we'll resume completion 3867838c67fSStefan Hajnoczi * processing there. 3877838c67fSStefan Hajnoczi */ 3887838c67fSStefan Hajnoczi qemu_bh_schedule(q->completion_bh); 3897838c67fSStefan Hajnoczi 390bdd6a90aSFam Zheng assert(q->inflight >= 0); 391bdd6a90aSFam Zheng while (q->inflight) { 39204b3fb39SStefan Hajnoczi int ret; 393bdd6a90aSFam Zheng int16_t cid; 39404b3fb39SStefan Hajnoczi 395bdd6a90aSFam Zheng c = (NvmeCqe *)&q->cq.queue[q->cq.head * NVME_CQ_ENTRY_BYTES]; 396258867d1SMaxim Levitsky if ((le16_to_cpu(c->status) & 0x1) == q->cq_phase) { 397bdd6a90aSFam Zheng break; 398bdd6a90aSFam Zheng } 39904b3fb39SStefan Hajnoczi ret = nvme_translate_error(c); 400bdd6a90aSFam Zheng q->cq.head = (q->cq.head + 1) % NVME_QUEUE_SIZE; 401bdd6a90aSFam Zheng if (!q->cq.head) { 402bdd6a90aSFam Zheng q->cq_phase = !q->cq_phase; 403bdd6a90aSFam Zheng } 404bdd6a90aSFam Zheng cid = le16_to_cpu(c->cid); 405bdd6a90aSFam Zheng if (cid == 0 || cid > NVME_QUEUE_SIZE) { 406bdd6a90aSFam Zheng fprintf(stderr, "Unexpected CID in completion queue: %" PRIu32 "\n", 407bdd6a90aSFam Zheng cid); 408bdd6a90aSFam Zheng continue; 409bdd6a90aSFam Zheng } 410bdd6a90aSFam Zheng trace_nvme_complete_command(s, q->index, cid); 411bdd6a90aSFam Zheng preq = &q->reqs[cid - 1]; 412bdd6a90aSFam Zheng req = *preq; 413bdd6a90aSFam Zheng assert(req.cid == cid); 414bdd6a90aSFam Zheng assert(req.cb); 4151086e95dSStefan Hajnoczi nvme_put_free_req_locked(q, preq); 416bdd6a90aSFam Zheng preq->cb = preq->opaque = NULL; 4177838c67fSStefan Hajnoczi q->inflight--; 418bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 41904b3fb39SStefan Hajnoczi req.cb(req.opaque, ret); 420bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 421bdd6a90aSFam Zheng progress = true; 422bdd6a90aSFam Zheng } 423bdd6a90aSFam Zheng if (progress) { 424bdd6a90aSFam Zheng /* Notify the device so it can post more completions. */ 425bdd6a90aSFam Zheng smp_mb_release(); 426bdd6a90aSFam Zheng *q->cq.doorbell = cpu_to_le32(q->cq.head); 427b75fd5f5SStefan Hajnoczi nvme_wake_free_req_locked(q); 428bdd6a90aSFam Zheng } 4297838c67fSStefan Hajnoczi 4307838c67fSStefan Hajnoczi qemu_bh_cancel(q->completion_bh); 4317838c67fSStefan Hajnoczi 432bdd6a90aSFam Zheng return progress; 433bdd6a90aSFam Zheng } 434bdd6a90aSFam Zheng 4357838c67fSStefan Hajnoczi static void nvme_process_completion_bh(void *opaque) 4367838c67fSStefan Hajnoczi { 4377838c67fSStefan Hajnoczi NVMeQueuePair *q = opaque; 4387838c67fSStefan Hajnoczi 4397838c67fSStefan Hajnoczi /* 4407838c67fSStefan Hajnoczi * We're being invoked because a nvme_process_completion() cb() function 4417838c67fSStefan Hajnoczi * called aio_poll(). The callback may be waiting for further completions 4427838c67fSStefan Hajnoczi * so notify the device that it has space to fill in more completions now. 4437838c67fSStefan Hajnoczi */ 4447838c67fSStefan Hajnoczi smp_mb_release(); 4457838c67fSStefan Hajnoczi *q->cq.doorbell = cpu_to_le32(q->cq.head); 4467838c67fSStefan Hajnoczi nvme_wake_free_req_locked(q); 4477838c67fSStefan Hajnoczi 4487838c67fSStefan Hajnoczi nvme_process_completion(q); 4497838c67fSStefan Hajnoczi } 4507838c67fSStefan Hajnoczi 451bdd6a90aSFam Zheng static void nvme_trace_command(const NvmeCmd *cmd) 452bdd6a90aSFam Zheng { 453bdd6a90aSFam Zheng int i; 454bdd6a90aSFam Zheng 455e266f52cSPhilippe Mathieu-Daudé if (!trace_event_get_state_backends(TRACE_NVME_SUBMIT_COMMAND_RAW)) { 456e266f52cSPhilippe Mathieu-Daudé return; 457e266f52cSPhilippe Mathieu-Daudé } 458bdd6a90aSFam Zheng for (i = 0; i < 8; ++i) { 459bdd6a90aSFam Zheng uint8_t *cmdp = (uint8_t *)cmd + i * 8; 460bdd6a90aSFam Zheng trace_nvme_submit_command_raw(cmdp[0], cmdp[1], cmdp[2], cmdp[3], 461bdd6a90aSFam Zheng cmdp[4], cmdp[5], cmdp[6], cmdp[7]); 462bdd6a90aSFam Zheng } 463bdd6a90aSFam Zheng } 464bdd6a90aSFam Zheng 465b75fd5f5SStefan Hajnoczi static void nvme_submit_command(NVMeQueuePair *q, NVMeRequest *req, 466bdd6a90aSFam Zheng NvmeCmd *cmd, BlockCompletionFunc cb, 467bdd6a90aSFam Zheng void *opaque) 468bdd6a90aSFam Zheng { 469bdd6a90aSFam Zheng assert(!req->cb); 470bdd6a90aSFam Zheng req->cb = cb; 471bdd6a90aSFam Zheng req->opaque = opaque; 472bdd6a90aSFam Zheng cmd->cid = cpu_to_le32(req->cid); 473bdd6a90aSFam Zheng 474b75fd5f5SStefan Hajnoczi trace_nvme_submit_command(q->s, q->index, req->cid); 475bdd6a90aSFam Zheng nvme_trace_command(cmd); 476bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 477bdd6a90aSFam Zheng memcpy((uint8_t *)q->sq.queue + 478bdd6a90aSFam Zheng q->sq.tail * NVME_SQ_ENTRY_BYTES, cmd, sizeof(*cmd)); 479bdd6a90aSFam Zheng q->sq.tail = (q->sq.tail + 1) % NVME_QUEUE_SIZE; 480bdd6a90aSFam Zheng q->need_kick++; 481b75fd5f5SStefan Hajnoczi nvme_kick(q); 482b75fd5f5SStefan Hajnoczi nvme_process_completion(q); 483bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 484bdd6a90aSFam Zheng } 485bdd6a90aSFam Zheng 486bdd6a90aSFam Zheng static void nvme_cmd_sync_cb(void *opaque, int ret) 487bdd6a90aSFam Zheng { 488bdd6a90aSFam Zheng int *pret = opaque; 489bdd6a90aSFam Zheng *pret = ret; 4904720cbeeSKevin Wolf aio_wait_kick(); 491bdd6a90aSFam Zheng } 492bdd6a90aSFam Zheng 493bdd6a90aSFam Zheng static int nvme_cmd_sync(BlockDriverState *bs, NVMeQueuePair *q, 494bdd6a90aSFam Zheng NvmeCmd *cmd) 495bdd6a90aSFam Zheng { 496bdd6a90aSFam Zheng NVMeRequest *req; 497bdd6a90aSFam Zheng int ret = -EINPROGRESS; 498bdd6a90aSFam Zheng req = nvme_get_free_req(q); 499bdd6a90aSFam Zheng if (!req) { 500bdd6a90aSFam Zheng return -EBUSY; 501bdd6a90aSFam Zheng } 502b75fd5f5SStefan Hajnoczi nvme_submit_command(q, req, cmd, nvme_cmd_sync_cb, &ret); 503bdd6a90aSFam Zheng 504bdd6a90aSFam Zheng BDRV_POLL_WHILE(bs, ret == -EINPROGRESS); 505bdd6a90aSFam Zheng return ret; 506bdd6a90aSFam Zheng } 507bdd6a90aSFam Zheng 508bdd6a90aSFam Zheng static void nvme_identify(BlockDriverState *bs, int namespace, Error **errp) 509bdd6a90aSFam Zheng { 510bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 511bdd6a90aSFam Zheng NvmeIdCtrl *idctrl; 512bdd6a90aSFam Zheng NvmeIdNs *idns; 513118d1b6aSMaxim Levitsky NvmeLBAF *lbaf; 514bdd6a90aSFam Zheng uint8_t *resp; 515e0dd95e3SMaxim Levitsky uint16_t oncs; 5161120407bSMax Reitz int r; 517bdd6a90aSFam Zheng uint64_t iova; 518bdd6a90aSFam Zheng NvmeCmd cmd = { 519bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_IDENTIFY, 520bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(0x1), 521bdd6a90aSFam Zheng }; 522bdd6a90aSFam Zheng 523bdd6a90aSFam Zheng resp = qemu_try_blockalign0(bs, sizeof(NvmeIdCtrl)); 524bdd6a90aSFam Zheng if (!resp) { 525bdd6a90aSFam Zheng error_setg(errp, "Cannot allocate buffer for identify response"); 526bdd6a90aSFam Zheng goto out; 527bdd6a90aSFam Zheng } 528bdd6a90aSFam Zheng idctrl = (NvmeIdCtrl *)resp; 529bdd6a90aSFam Zheng idns = (NvmeIdNs *)resp; 530bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, resp, sizeof(NvmeIdCtrl), true, &iova); 531bdd6a90aSFam Zheng if (r) { 532bdd6a90aSFam Zheng error_setg(errp, "Cannot map buffer for DMA"); 533bdd6a90aSFam Zheng goto out; 534bdd6a90aSFam Zheng } 535c26f2173SKlaus Jensen cmd.dptr.prp1 = cpu_to_le64(iova); 536bdd6a90aSFam Zheng 53773159e52SPhilippe Mathieu-Daudé if (nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd)) { 538bdd6a90aSFam Zheng error_setg(errp, "Failed to identify controller"); 539bdd6a90aSFam Zheng goto out; 540bdd6a90aSFam Zheng } 541bdd6a90aSFam Zheng 542bdd6a90aSFam Zheng if (le32_to_cpu(idctrl->nn) < namespace) { 543bdd6a90aSFam Zheng error_setg(errp, "Invalid namespace"); 544bdd6a90aSFam Zheng goto out; 545bdd6a90aSFam Zheng } 546bdd6a90aSFam Zheng s->write_cache_supported = le32_to_cpu(idctrl->vwc) & 0x1; 547bdd6a90aSFam Zheng s->max_transfer = (idctrl->mdts ? 1 << idctrl->mdts : 0) * s->page_size; 548bdd6a90aSFam Zheng /* For now the page list buffer per command is one page, to hold at most 549bdd6a90aSFam Zheng * s->page_size / sizeof(uint64_t) entries. */ 550bdd6a90aSFam Zheng s->max_transfer = MIN_NON_ZERO(s->max_transfer, 551bdd6a90aSFam Zheng s->page_size / sizeof(uint64_t) * s->page_size); 552bdd6a90aSFam Zheng 553e0dd95e3SMaxim Levitsky oncs = le16_to_cpu(idctrl->oncs); 55469265150SKlaus Jensen s->supports_write_zeroes = !!(oncs & NVME_ONCS_WRITE_ZEROES); 555e87a09d6SMaxim Levitsky s->supports_discard = !!(oncs & NVME_ONCS_DSM); 556e0dd95e3SMaxim Levitsky 557bdd6a90aSFam Zheng memset(resp, 0, 4096); 558bdd6a90aSFam Zheng 559bdd6a90aSFam Zheng cmd.cdw10 = 0; 560bdd6a90aSFam Zheng cmd.nsid = cpu_to_le32(namespace); 56173159e52SPhilippe Mathieu-Daudé if (nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd)) { 562bdd6a90aSFam Zheng error_setg(errp, "Failed to identify namespace"); 563bdd6a90aSFam Zheng goto out; 564bdd6a90aSFam Zheng } 565bdd6a90aSFam Zheng 566bdd6a90aSFam Zheng s->nsze = le64_to_cpu(idns->nsze); 567118d1b6aSMaxim Levitsky lbaf = &idns->lbaf[NVME_ID_NS_FLBAS_INDEX(idns->flbas)]; 568bdd6a90aSFam Zheng 569e0dd95e3SMaxim Levitsky if (NVME_ID_NS_DLFEAT_WRITE_ZEROES(idns->dlfeat) && 570e0dd95e3SMaxim Levitsky NVME_ID_NS_DLFEAT_READ_BEHAVIOR(idns->dlfeat) == 571e0dd95e3SMaxim Levitsky NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES) { 572e0dd95e3SMaxim Levitsky bs->supported_write_flags |= BDRV_REQ_MAY_UNMAP; 573e0dd95e3SMaxim Levitsky } 574e0dd95e3SMaxim Levitsky 575118d1b6aSMaxim Levitsky if (lbaf->ms) { 576118d1b6aSMaxim Levitsky error_setg(errp, "Namespaces with metadata are not yet supported"); 577118d1b6aSMaxim Levitsky goto out; 578118d1b6aSMaxim Levitsky } 579118d1b6aSMaxim Levitsky 5801120407bSMax Reitz if (lbaf->ds < BDRV_SECTOR_BITS || lbaf->ds > 12 || 5811120407bSMax Reitz (1 << lbaf->ds) > s->page_size) 5821120407bSMax Reitz { 5831120407bSMax Reitz error_setg(errp, "Namespace has unsupported block size (2^%d)", 5841120407bSMax Reitz lbaf->ds); 585118d1b6aSMaxim Levitsky goto out; 586118d1b6aSMaxim Levitsky } 587118d1b6aSMaxim Levitsky 588118d1b6aSMaxim Levitsky s->blkshift = lbaf->ds; 589bdd6a90aSFam Zheng out: 590bdd6a90aSFam Zheng qemu_vfio_dma_unmap(s->vfio, resp); 591bdd6a90aSFam Zheng qemu_vfree(resp); 592bdd6a90aSFam Zheng } 593bdd6a90aSFam Zheng 594bdd6a90aSFam Zheng static bool nvme_poll_queues(BDRVNVMeState *s) 595bdd6a90aSFam Zheng { 596bdd6a90aSFam Zheng bool progress = false; 597bdd6a90aSFam Zheng int i; 598bdd6a90aSFam Zheng 599bdd6a90aSFam Zheng for (i = 0; i < s->nr_queues; i++) { 600bdd6a90aSFam Zheng NVMeQueuePair *q = s->queues[i]; 6012446e0e2SStefan Hajnoczi const size_t cqe_offset = q->cq.head * NVME_CQ_ENTRY_BYTES; 6022446e0e2SStefan Hajnoczi NvmeCqe *cqe = (NvmeCqe *)&q->cq.queue[cqe_offset]; 6032446e0e2SStefan Hajnoczi 6042446e0e2SStefan Hajnoczi /* 6052446e0e2SStefan Hajnoczi * Do an early check for completions. q->lock isn't needed because 6062446e0e2SStefan Hajnoczi * nvme_process_completion() only runs in the event loop thread and 6072446e0e2SStefan Hajnoczi * cannot race with itself. 6082446e0e2SStefan Hajnoczi */ 6092446e0e2SStefan Hajnoczi if ((le16_to_cpu(cqe->status) & 0x1) == q->cq_phase) { 6102446e0e2SStefan Hajnoczi continue; 6112446e0e2SStefan Hajnoczi } 6122446e0e2SStefan Hajnoczi 613bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 614b75fd5f5SStefan Hajnoczi while (nvme_process_completion(q)) { 615bdd6a90aSFam Zheng /* Keep polling */ 616bdd6a90aSFam Zheng progress = true; 617bdd6a90aSFam Zheng } 618bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 619bdd6a90aSFam Zheng } 620bdd6a90aSFam Zheng return progress; 621bdd6a90aSFam Zheng } 622bdd6a90aSFam Zheng 623bdd6a90aSFam Zheng static void nvme_handle_event(EventNotifier *n) 624bdd6a90aSFam Zheng { 625bdd6a90aSFam Zheng BDRVNVMeState *s = container_of(n, BDRVNVMeState, irq_notifier); 626bdd6a90aSFam Zheng 627bdd6a90aSFam Zheng trace_nvme_handle_event(s); 628bdd6a90aSFam Zheng event_notifier_test_and_clear(n); 629bdd6a90aSFam Zheng nvme_poll_queues(s); 630bdd6a90aSFam Zheng } 631bdd6a90aSFam Zheng 632bdd6a90aSFam Zheng static bool nvme_add_io_queue(BlockDriverState *bs, Error **errp) 633bdd6a90aSFam Zheng { 634bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 635bdd6a90aSFam Zheng int n = s->nr_queues; 636bdd6a90aSFam Zheng NVMeQueuePair *q; 637bdd6a90aSFam Zheng NvmeCmd cmd; 638bdd6a90aSFam Zheng int queue_size = NVME_QUEUE_SIZE; 639bdd6a90aSFam Zheng 640bdd6a90aSFam Zheng q = nvme_create_queue_pair(bs, n, queue_size, errp); 641bdd6a90aSFam Zheng if (!q) { 642bdd6a90aSFam Zheng return false; 643bdd6a90aSFam Zheng } 644bdd6a90aSFam Zheng cmd = (NvmeCmd) { 645bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_CREATE_CQ, 646c26f2173SKlaus Jensen .dptr.prp1 = cpu_to_le64(q->cq.iova), 647bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | (n & 0xFFFF)), 648bdd6a90aSFam Zheng .cdw11 = cpu_to_le32(0x3), 649bdd6a90aSFam Zheng }; 65073159e52SPhilippe Mathieu-Daudé if (nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd)) { 651*bf6ce5ecSPhilippe Mathieu-Daudé error_setg(errp, "Failed to create CQ io queue [%d]", n); 652b75fd5f5SStefan Hajnoczi nvme_free_queue_pair(q); 653bdd6a90aSFam Zheng return false; 654bdd6a90aSFam Zheng } 655bdd6a90aSFam Zheng cmd = (NvmeCmd) { 656bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_CREATE_SQ, 657c26f2173SKlaus Jensen .dptr.prp1 = cpu_to_le64(q->sq.iova), 658bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | (n & 0xFFFF)), 659bdd6a90aSFam Zheng .cdw11 = cpu_to_le32(0x1 | (n << 16)), 660bdd6a90aSFam Zheng }; 66173159e52SPhilippe Mathieu-Daudé if (nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd)) { 662*bf6ce5ecSPhilippe Mathieu-Daudé error_setg(errp, "Failed to create SQ io queue [%d]", n); 663b75fd5f5SStefan Hajnoczi nvme_free_queue_pair(q); 664bdd6a90aSFam Zheng return false; 665bdd6a90aSFam Zheng } 666bdd6a90aSFam Zheng s->queues = g_renew(NVMeQueuePair *, s->queues, n + 1); 667bdd6a90aSFam Zheng s->queues[n] = q; 668bdd6a90aSFam Zheng s->nr_queues++; 669bdd6a90aSFam Zheng return true; 670bdd6a90aSFam Zheng } 671bdd6a90aSFam Zheng 672bdd6a90aSFam Zheng static bool nvme_poll_cb(void *opaque) 673bdd6a90aSFam Zheng { 674bdd6a90aSFam Zheng EventNotifier *e = opaque; 675bdd6a90aSFam Zheng BDRVNVMeState *s = container_of(e, BDRVNVMeState, irq_notifier); 676bdd6a90aSFam Zheng 677bdd6a90aSFam Zheng trace_nvme_poll_cb(s); 678b3ac2b94SSimran Singhal return nvme_poll_queues(s); 679bdd6a90aSFam Zheng } 680bdd6a90aSFam Zheng 681bdd6a90aSFam Zheng static int nvme_init(BlockDriverState *bs, const char *device, int namespace, 682bdd6a90aSFam Zheng Error **errp) 683bdd6a90aSFam Zheng { 684bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 685bdd6a90aSFam Zheng int ret; 686bdd6a90aSFam Zheng uint64_t cap; 687bdd6a90aSFam Zheng uint64_t timeout_ms; 688bdd6a90aSFam Zheng uint64_t deadline, now; 689bdd6a90aSFam Zheng Error *local_err = NULL; 690bdd6a90aSFam Zheng 691bdd6a90aSFam Zheng qemu_co_mutex_init(&s->dma_map_lock); 692bdd6a90aSFam Zheng qemu_co_queue_init(&s->dma_flush_queue); 693cc61b074SMax Reitz s->device = g_strdup(device); 694bdd6a90aSFam Zheng s->nsid = namespace; 695bdd6a90aSFam Zheng s->aio_context = bdrv_get_aio_context(bs); 696bdd6a90aSFam Zheng ret = event_notifier_init(&s->irq_notifier, 0); 697bdd6a90aSFam Zheng if (ret) { 698bdd6a90aSFam Zheng error_setg(errp, "Failed to init event notifier"); 699bdd6a90aSFam Zheng return ret; 700bdd6a90aSFam Zheng } 701bdd6a90aSFam Zheng 702bdd6a90aSFam Zheng s->vfio = qemu_vfio_open_pci(device, errp); 703bdd6a90aSFam Zheng if (!s->vfio) { 704bdd6a90aSFam Zheng ret = -EINVAL; 7059582f357SFam Zheng goto out; 706bdd6a90aSFam Zheng } 707bdd6a90aSFam Zheng 708bdd6a90aSFam Zheng s->regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, NVME_BAR_SIZE, errp); 709bdd6a90aSFam Zheng if (!s->regs) { 710bdd6a90aSFam Zheng ret = -EINVAL; 7119582f357SFam Zheng goto out; 712bdd6a90aSFam Zheng } 713bdd6a90aSFam Zheng 714bdd6a90aSFam Zheng /* Perform initialize sequence as described in NVMe spec "7.6.1 715bdd6a90aSFam Zheng * Initialization". */ 716bdd6a90aSFam Zheng 717bdd6a90aSFam Zheng cap = le64_to_cpu(s->regs->cap); 718bdd6a90aSFam Zheng if (!(cap & (1ULL << 37))) { 719bdd6a90aSFam Zheng error_setg(errp, "Device doesn't support NVMe command set"); 720bdd6a90aSFam Zheng ret = -EINVAL; 7219582f357SFam Zheng goto out; 722bdd6a90aSFam Zheng } 723bdd6a90aSFam Zheng 724bdd6a90aSFam Zheng s->page_size = MAX(4096, 1 << (12 + ((cap >> 48) & 0xF))); 725bdd6a90aSFam Zheng s->doorbell_scale = (4 << (((cap >> 32) & 0xF))) / sizeof(uint32_t); 726bdd6a90aSFam Zheng bs->bl.opt_mem_alignment = s->page_size; 727bdd6a90aSFam Zheng timeout_ms = MIN(500 * ((cap >> 24) & 0xFF), 30000); 728bdd6a90aSFam Zheng 729bdd6a90aSFam Zheng /* Reset device to get a clean state. */ 730bdd6a90aSFam Zheng s->regs->cc = cpu_to_le32(le32_to_cpu(s->regs->cc) & 0xFE); 731bdd6a90aSFam Zheng /* Wait for CSTS.RDY = 0. */ 732e4f310feSPhilippe Mathieu-Daudé deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCALE_MS; 733bdd6a90aSFam Zheng while (le32_to_cpu(s->regs->csts) & 0x1) { 734bdd6a90aSFam Zheng if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 735bdd6a90aSFam Zheng error_setg(errp, "Timeout while waiting for device to reset (%" 736bdd6a90aSFam Zheng PRId64 " ms)", 737bdd6a90aSFam Zheng timeout_ms); 738bdd6a90aSFam Zheng ret = -ETIMEDOUT; 7399582f357SFam Zheng goto out; 740bdd6a90aSFam Zheng } 741bdd6a90aSFam Zheng } 742bdd6a90aSFam Zheng 743bdd6a90aSFam Zheng /* Set up admin queue. */ 744bdd6a90aSFam Zheng s->queues = g_new(NVMeQueuePair *, 1); 74573159e52SPhilippe Mathieu-Daudé s->queues[INDEX_ADMIN] = nvme_create_queue_pair(bs, 0, 74673159e52SPhilippe Mathieu-Daudé NVME_QUEUE_SIZE, 74773159e52SPhilippe Mathieu-Daudé errp); 74873159e52SPhilippe Mathieu-Daudé if (!s->queues[INDEX_ADMIN]) { 749bdd6a90aSFam Zheng ret = -EINVAL; 7509582f357SFam Zheng goto out; 751bdd6a90aSFam Zheng } 75295667c3bSMichal Privoznik s->nr_queues = 1; 753bdd6a90aSFam Zheng QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000); 754bdd6a90aSFam Zheng s->regs->aqa = cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE); 75573159e52SPhilippe Mathieu-Daudé s->regs->asq = cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); 75673159e52SPhilippe Mathieu-Daudé s->regs->acq = cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); 757bdd6a90aSFam Zheng 758bdd6a90aSFam Zheng /* After setting up all control registers we can enable device now. */ 759bdd6a90aSFam Zheng s->regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | 760bdd6a90aSFam Zheng (ctz32(NVME_SQ_ENTRY_BYTES) << 16) | 761bdd6a90aSFam Zheng 0x1); 762bdd6a90aSFam Zheng /* Wait for CSTS.RDY = 1. */ 763bdd6a90aSFam Zheng now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 764bdd6a90aSFam Zheng deadline = now + timeout_ms * 1000000; 765bdd6a90aSFam Zheng while (!(le32_to_cpu(s->regs->csts) & 0x1)) { 766bdd6a90aSFam Zheng if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 767bdd6a90aSFam Zheng error_setg(errp, "Timeout while waiting for device to start (%" 768bdd6a90aSFam Zheng PRId64 " ms)", 769bdd6a90aSFam Zheng timeout_ms); 770bdd6a90aSFam Zheng ret = -ETIMEDOUT; 7719582f357SFam Zheng goto out; 772bdd6a90aSFam Zheng } 773bdd6a90aSFam Zheng } 774bdd6a90aSFam Zheng 775bdd6a90aSFam Zheng ret = qemu_vfio_pci_init_irq(s->vfio, &s->irq_notifier, 776bdd6a90aSFam Zheng VFIO_PCI_MSIX_IRQ_INDEX, errp); 777bdd6a90aSFam Zheng if (ret) { 7789582f357SFam Zheng goto out; 779bdd6a90aSFam Zheng } 780bdd6a90aSFam Zheng aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier, 781bdd6a90aSFam Zheng false, nvme_handle_event, nvme_poll_cb); 782bdd6a90aSFam Zheng 78378d8c99eSPaolo Bonzini nvme_identify(bs, namespace, &local_err); 784bdd6a90aSFam Zheng if (local_err) { 785bdd6a90aSFam Zheng error_propagate(errp, local_err); 786bdd6a90aSFam Zheng ret = -EIO; 7879582f357SFam Zheng goto out; 788bdd6a90aSFam Zheng } 789bdd6a90aSFam Zheng 790bdd6a90aSFam Zheng /* Set up command queues. */ 791bdd6a90aSFam Zheng if (!nvme_add_io_queue(bs, errp)) { 792bdd6a90aSFam Zheng ret = -EIO; 793bdd6a90aSFam Zheng } 7949582f357SFam Zheng out: 7959582f357SFam Zheng /* Cleaning up is done in nvme_file_open() upon error. */ 796bdd6a90aSFam Zheng return ret; 797bdd6a90aSFam Zheng } 798bdd6a90aSFam Zheng 799bdd6a90aSFam Zheng /* Parse a filename in the format of nvme://XXXX:XX:XX.X/X. Example: 800bdd6a90aSFam Zheng * 801bdd6a90aSFam Zheng * nvme://0000:44:00.0/1 802bdd6a90aSFam Zheng * 803bdd6a90aSFam Zheng * where the "nvme://" is a fixed form of the protocol prefix, the middle part 804bdd6a90aSFam Zheng * is the PCI address, and the last part is the namespace number starting from 805bdd6a90aSFam Zheng * 1 according to the NVMe spec. */ 806bdd6a90aSFam Zheng static void nvme_parse_filename(const char *filename, QDict *options, 807bdd6a90aSFam Zheng Error **errp) 808bdd6a90aSFam Zheng { 809bdd6a90aSFam Zheng int pref = strlen("nvme://"); 810bdd6a90aSFam Zheng 811bdd6a90aSFam Zheng if (strlen(filename) > pref && !strncmp(filename, "nvme://", pref)) { 812bdd6a90aSFam Zheng const char *tmp = filename + pref; 813bdd6a90aSFam Zheng char *device; 814bdd6a90aSFam Zheng const char *namespace; 815bdd6a90aSFam Zheng unsigned long ns; 816bdd6a90aSFam Zheng const char *slash = strchr(tmp, '/'); 817bdd6a90aSFam Zheng if (!slash) { 818625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, tmp); 819bdd6a90aSFam Zheng return; 820bdd6a90aSFam Zheng } 821bdd6a90aSFam Zheng device = g_strndup(tmp, slash - tmp); 822625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, device); 823bdd6a90aSFam Zheng g_free(device); 824bdd6a90aSFam Zheng namespace = slash + 1; 825bdd6a90aSFam Zheng if (*namespace && qemu_strtoul(namespace, NULL, 10, &ns)) { 826bdd6a90aSFam Zheng error_setg(errp, "Invalid namespace '%s', positive number expected", 827bdd6a90aSFam Zheng namespace); 828bdd6a90aSFam Zheng return; 829bdd6a90aSFam Zheng } 830625eaca9SLaurent Vivier qdict_put_str(options, NVME_BLOCK_OPT_NAMESPACE, 831625eaca9SLaurent Vivier *namespace ? namespace : "1"); 832bdd6a90aSFam Zheng } 833bdd6a90aSFam Zheng } 834bdd6a90aSFam Zheng 835bdd6a90aSFam Zheng static int nvme_enable_disable_write_cache(BlockDriverState *bs, bool enable, 836bdd6a90aSFam Zheng Error **errp) 837bdd6a90aSFam Zheng { 838bdd6a90aSFam Zheng int ret; 839bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 840bdd6a90aSFam Zheng NvmeCmd cmd = { 841bdd6a90aSFam Zheng .opcode = NVME_ADM_CMD_SET_FEATURES, 842bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 843bdd6a90aSFam Zheng .cdw10 = cpu_to_le32(0x06), 844bdd6a90aSFam Zheng .cdw11 = cpu_to_le32(enable ? 0x01 : 0x00), 845bdd6a90aSFam Zheng }; 846bdd6a90aSFam Zheng 84773159e52SPhilippe Mathieu-Daudé ret = nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd); 848bdd6a90aSFam Zheng if (ret) { 849bdd6a90aSFam Zheng error_setg(errp, "Failed to configure NVMe write cache"); 850bdd6a90aSFam Zheng } 851bdd6a90aSFam Zheng return ret; 852bdd6a90aSFam Zheng } 853bdd6a90aSFam Zheng 854bdd6a90aSFam Zheng static void nvme_close(BlockDriverState *bs) 855bdd6a90aSFam Zheng { 856bdd6a90aSFam Zheng int i; 857bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 858bdd6a90aSFam Zheng 859bdd6a90aSFam Zheng for (i = 0; i < s->nr_queues; ++i) { 860b75fd5f5SStefan Hajnoczi nvme_free_queue_pair(s->queues[i]); 861bdd6a90aSFam Zheng } 8629582f357SFam Zheng g_free(s->queues); 863bdd6a90aSFam Zheng aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier, 864bdd6a90aSFam Zheng false, NULL, NULL); 8659582f357SFam Zheng event_notifier_cleanup(&s->irq_notifier); 866bdd6a90aSFam Zheng qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->regs, 0, NVME_BAR_SIZE); 867bdd6a90aSFam Zheng qemu_vfio_close(s->vfio); 868cc61b074SMax Reitz 869cc61b074SMax Reitz g_free(s->device); 870bdd6a90aSFam Zheng } 871bdd6a90aSFam Zheng 872bdd6a90aSFam Zheng static int nvme_file_open(BlockDriverState *bs, QDict *options, int flags, 873bdd6a90aSFam Zheng Error **errp) 874bdd6a90aSFam Zheng { 875bdd6a90aSFam Zheng const char *device; 876bdd6a90aSFam Zheng QemuOpts *opts; 877bdd6a90aSFam Zheng int namespace; 878bdd6a90aSFam Zheng int ret; 879bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 880bdd6a90aSFam Zheng 881e0dd95e3SMaxim Levitsky bs->supported_write_flags = BDRV_REQ_FUA; 882e0dd95e3SMaxim Levitsky 883bdd6a90aSFam Zheng opts = qemu_opts_create(&runtime_opts, NULL, 0, &error_abort); 884bdd6a90aSFam Zheng qemu_opts_absorb_qdict(opts, options, &error_abort); 885bdd6a90aSFam Zheng device = qemu_opt_get(opts, NVME_BLOCK_OPT_DEVICE); 886bdd6a90aSFam Zheng if (!device) { 887bdd6a90aSFam Zheng error_setg(errp, "'" NVME_BLOCK_OPT_DEVICE "' option is required"); 888bdd6a90aSFam Zheng qemu_opts_del(opts); 889bdd6a90aSFam Zheng return -EINVAL; 890bdd6a90aSFam Zheng } 891bdd6a90aSFam Zheng 892bdd6a90aSFam Zheng namespace = qemu_opt_get_number(opts, NVME_BLOCK_OPT_NAMESPACE, 1); 893bdd6a90aSFam Zheng ret = nvme_init(bs, device, namespace, errp); 894bdd6a90aSFam Zheng qemu_opts_del(opts); 895bdd6a90aSFam Zheng if (ret) { 896bdd6a90aSFam Zheng goto fail; 897bdd6a90aSFam Zheng } 898bdd6a90aSFam Zheng if (flags & BDRV_O_NOCACHE) { 899bdd6a90aSFam Zheng if (!s->write_cache_supported) { 900bdd6a90aSFam Zheng error_setg(errp, 901bdd6a90aSFam Zheng "NVMe controller doesn't support write cache configuration"); 902bdd6a90aSFam Zheng ret = -EINVAL; 903bdd6a90aSFam Zheng } else { 904bdd6a90aSFam Zheng ret = nvme_enable_disable_write_cache(bs, !(flags & BDRV_O_NOCACHE), 905bdd6a90aSFam Zheng errp); 906bdd6a90aSFam Zheng } 907bdd6a90aSFam Zheng if (ret) { 908bdd6a90aSFam Zheng goto fail; 909bdd6a90aSFam Zheng } 910bdd6a90aSFam Zheng } 911bdd6a90aSFam Zheng return 0; 912bdd6a90aSFam Zheng fail: 913bdd6a90aSFam Zheng nvme_close(bs); 914bdd6a90aSFam Zheng return ret; 915bdd6a90aSFam Zheng } 916bdd6a90aSFam Zheng 917bdd6a90aSFam Zheng static int64_t nvme_getlength(BlockDriverState *bs) 918bdd6a90aSFam Zheng { 919bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 920118d1b6aSMaxim Levitsky return s->nsze << s->blkshift; 921118d1b6aSMaxim Levitsky } 922bdd6a90aSFam Zheng 9231120407bSMax Reitz static uint32_t nvme_get_blocksize(BlockDriverState *bs) 924118d1b6aSMaxim Levitsky { 925118d1b6aSMaxim Levitsky BDRVNVMeState *s = bs->opaque; 9261120407bSMax Reitz assert(s->blkshift >= BDRV_SECTOR_BITS && s->blkshift <= 12); 9271120407bSMax Reitz return UINT32_C(1) << s->blkshift; 928118d1b6aSMaxim Levitsky } 929118d1b6aSMaxim Levitsky 930118d1b6aSMaxim Levitsky static int nvme_probe_blocksizes(BlockDriverState *bs, BlockSizes *bsz) 931118d1b6aSMaxim Levitsky { 9321120407bSMax Reitz uint32_t blocksize = nvme_get_blocksize(bs); 933118d1b6aSMaxim Levitsky bsz->phys = blocksize; 934118d1b6aSMaxim Levitsky bsz->log = blocksize; 935118d1b6aSMaxim Levitsky return 0; 936bdd6a90aSFam Zheng } 937bdd6a90aSFam Zheng 938bdd6a90aSFam Zheng /* Called with s->dma_map_lock */ 939bdd6a90aSFam Zheng static coroutine_fn int nvme_cmd_unmap_qiov(BlockDriverState *bs, 940bdd6a90aSFam Zheng QEMUIOVector *qiov) 941bdd6a90aSFam Zheng { 942bdd6a90aSFam Zheng int r = 0; 943bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 944bdd6a90aSFam Zheng 945bdd6a90aSFam Zheng s->dma_map_count -= qiov->size; 946bdd6a90aSFam Zheng if (!s->dma_map_count && !qemu_co_queue_empty(&s->dma_flush_queue)) { 947bdd6a90aSFam Zheng r = qemu_vfio_dma_reset_temporary(s->vfio); 948bdd6a90aSFam Zheng if (!r) { 949bdd6a90aSFam Zheng qemu_co_queue_restart_all(&s->dma_flush_queue); 950bdd6a90aSFam Zheng } 951bdd6a90aSFam Zheng } 952bdd6a90aSFam Zheng return r; 953bdd6a90aSFam Zheng } 954bdd6a90aSFam Zheng 955bdd6a90aSFam Zheng /* Called with s->dma_map_lock */ 956bdd6a90aSFam Zheng static coroutine_fn int nvme_cmd_map_qiov(BlockDriverState *bs, NvmeCmd *cmd, 957bdd6a90aSFam Zheng NVMeRequest *req, QEMUIOVector *qiov) 958bdd6a90aSFam Zheng { 959bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 960bdd6a90aSFam Zheng uint64_t *pagelist = req->prp_list_page; 961bdd6a90aSFam Zheng int i, j, r; 962bdd6a90aSFam Zheng int entries = 0; 963bdd6a90aSFam Zheng 964bdd6a90aSFam Zheng assert(qiov->size); 965bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(qiov->size, s->page_size)); 966bdd6a90aSFam Zheng assert(qiov->size / s->page_size <= s->page_size / sizeof(uint64_t)); 967bdd6a90aSFam Zheng for (i = 0; i < qiov->niov; ++i) { 968bdd6a90aSFam Zheng bool retry = true; 969bdd6a90aSFam Zheng uint64_t iova; 970bdd6a90aSFam Zheng try_map: 971bdd6a90aSFam Zheng r = qemu_vfio_dma_map(s->vfio, 972bdd6a90aSFam Zheng qiov->iov[i].iov_base, 973bdd6a90aSFam Zheng qiov->iov[i].iov_len, 974bdd6a90aSFam Zheng true, &iova); 975bdd6a90aSFam Zheng if (r == -ENOMEM && retry) { 976bdd6a90aSFam Zheng retry = false; 977bdd6a90aSFam Zheng trace_nvme_dma_flush_queue_wait(s); 978bdd6a90aSFam Zheng if (s->dma_map_count) { 979bdd6a90aSFam Zheng trace_nvme_dma_map_flush(s); 980bdd6a90aSFam Zheng qemu_co_queue_wait(&s->dma_flush_queue, &s->dma_map_lock); 981bdd6a90aSFam Zheng } else { 982bdd6a90aSFam Zheng r = qemu_vfio_dma_reset_temporary(s->vfio); 983bdd6a90aSFam Zheng if (r) { 984bdd6a90aSFam Zheng goto fail; 985bdd6a90aSFam Zheng } 986bdd6a90aSFam Zheng } 987bdd6a90aSFam Zheng goto try_map; 988bdd6a90aSFam Zheng } 989bdd6a90aSFam Zheng if (r) { 990bdd6a90aSFam Zheng goto fail; 991bdd6a90aSFam Zheng } 992bdd6a90aSFam Zheng 993bdd6a90aSFam Zheng for (j = 0; j < qiov->iov[i].iov_len / s->page_size; j++) { 9942916405aSLi Feng pagelist[entries++] = cpu_to_le64(iova + j * s->page_size); 995bdd6a90aSFam Zheng } 996bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov_iov(s, i, qiov->iov[i].iov_base, 997bdd6a90aSFam Zheng qiov->iov[i].iov_len / s->page_size); 998bdd6a90aSFam Zheng } 999bdd6a90aSFam Zheng 1000bdd6a90aSFam Zheng s->dma_map_count += qiov->size; 1001bdd6a90aSFam Zheng 1002bdd6a90aSFam Zheng assert(entries <= s->page_size / sizeof(uint64_t)); 1003bdd6a90aSFam Zheng switch (entries) { 1004bdd6a90aSFam Zheng case 0: 1005bdd6a90aSFam Zheng abort(); 1006bdd6a90aSFam Zheng case 1: 1007c26f2173SKlaus Jensen cmd->dptr.prp1 = pagelist[0]; 1008c26f2173SKlaus Jensen cmd->dptr.prp2 = 0; 1009bdd6a90aSFam Zheng break; 1010bdd6a90aSFam Zheng case 2: 1011c26f2173SKlaus Jensen cmd->dptr.prp1 = pagelist[0]; 1012c26f2173SKlaus Jensen cmd->dptr.prp2 = pagelist[1]; 1013bdd6a90aSFam Zheng break; 1014bdd6a90aSFam Zheng default: 1015c26f2173SKlaus Jensen cmd->dptr.prp1 = pagelist[0]; 1016c26f2173SKlaus Jensen cmd->dptr.prp2 = cpu_to_le64(req->prp_list_iova + sizeof(uint64_t)); 1017bdd6a90aSFam Zheng break; 1018bdd6a90aSFam Zheng } 1019bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov(s, cmd, req, qiov, entries); 1020bdd6a90aSFam Zheng for (i = 0; i < entries; ++i) { 1021bdd6a90aSFam Zheng trace_nvme_cmd_map_qiov_pages(s, i, pagelist[i]); 1022bdd6a90aSFam Zheng } 1023bdd6a90aSFam Zheng return 0; 1024bdd6a90aSFam Zheng fail: 1025bdd6a90aSFam Zheng /* No need to unmap [0 - i) iovs even if we've failed, since we don't 1026bdd6a90aSFam Zheng * increment s->dma_map_count. This is okay for fixed mapping memory areas 1027bdd6a90aSFam Zheng * because they are already mapped before calling this function; for 1028bdd6a90aSFam Zheng * temporary mappings, a later nvme_cmd_(un)map_qiov will reclaim by 1029bdd6a90aSFam Zheng * calling qemu_vfio_dma_reset_temporary when necessary. */ 1030bdd6a90aSFam Zheng return r; 1031bdd6a90aSFam Zheng } 1032bdd6a90aSFam Zheng 1033bdd6a90aSFam Zheng typedef struct { 1034bdd6a90aSFam Zheng Coroutine *co; 1035bdd6a90aSFam Zheng int ret; 1036bdd6a90aSFam Zheng AioContext *ctx; 1037bdd6a90aSFam Zheng } NVMeCoData; 1038bdd6a90aSFam Zheng 1039bdd6a90aSFam Zheng static void nvme_rw_cb_bh(void *opaque) 1040bdd6a90aSFam Zheng { 1041bdd6a90aSFam Zheng NVMeCoData *data = opaque; 1042bdd6a90aSFam Zheng qemu_coroutine_enter(data->co); 1043bdd6a90aSFam Zheng } 1044bdd6a90aSFam Zheng 1045bdd6a90aSFam Zheng static void nvme_rw_cb(void *opaque, int ret) 1046bdd6a90aSFam Zheng { 1047bdd6a90aSFam Zheng NVMeCoData *data = opaque; 1048bdd6a90aSFam Zheng data->ret = ret; 1049bdd6a90aSFam Zheng if (!data->co) { 1050bdd6a90aSFam Zheng /* The rw coroutine hasn't yielded, don't try to enter. */ 1051bdd6a90aSFam Zheng return; 1052bdd6a90aSFam Zheng } 1053e4ec5ad4SPavel Dovgalyuk replay_bh_schedule_oneshot_event(data->ctx, nvme_rw_cb_bh, data); 1054bdd6a90aSFam Zheng } 1055bdd6a90aSFam Zheng 1056bdd6a90aSFam Zheng static coroutine_fn int nvme_co_prw_aligned(BlockDriverState *bs, 1057bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 1058bdd6a90aSFam Zheng QEMUIOVector *qiov, 1059bdd6a90aSFam Zheng bool is_write, 1060bdd6a90aSFam Zheng int flags) 1061bdd6a90aSFam Zheng { 1062bdd6a90aSFam Zheng int r; 1063bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 106473159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1065bdd6a90aSFam Zheng NVMeRequest *req; 1066118d1b6aSMaxim Levitsky 1067118d1b6aSMaxim Levitsky uint32_t cdw12 = (((bytes >> s->blkshift) - 1) & 0xFFFF) | 1068bdd6a90aSFam Zheng (flags & BDRV_REQ_FUA ? 1 << 30 : 0); 1069bdd6a90aSFam Zheng NvmeCmd cmd = { 1070bdd6a90aSFam Zheng .opcode = is_write ? NVME_CMD_WRITE : NVME_CMD_READ, 1071bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 1072118d1b6aSMaxim Levitsky .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF), 1073118d1b6aSMaxim Levitsky .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF), 1074bdd6a90aSFam Zheng .cdw12 = cpu_to_le32(cdw12), 1075bdd6a90aSFam Zheng }; 1076bdd6a90aSFam Zheng NVMeCoData data = { 1077bdd6a90aSFam Zheng .ctx = bdrv_get_aio_context(bs), 1078bdd6a90aSFam Zheng .ret = -EINPROGRESS, 1079bdd6a90aSFam Zheng }; 1080bdd6a90aSFam Zheng 1081bdd6a90aSFam Zheng trace_nvme_prw_aligned(s, is_write, offset, bytes, flags, qiov->niov); 1082bdd6a90aSFam Zheng assert(s->nr_queues > 1); 1083bdd6a90aSFam Zheng req = nvme_get_free_req(ioq); 1084bdd6a90aSFam Zheng assert(req); 1085bdd6a90aSFam Zheng 1086bdd6a90aSFam Zheng qemu_co_mutex_lock(&s->dma_map_lock); 1087bdd6a90aSFam Zheng r = nvme_cmd_map_qiov(bs, &cmd, req, qiov); 1088bdd6a90aSFam Zheng qemu_co_mutex_unlock(&s->dma_map_lock); 1089bdd6a90aSFam Zheng if (r) { 1090b75fd5f5SStefan Hajnoczi nvme_put_free_req_and_wake(ioq, req); 1091bdd6a90aSFam Zheng return r; 1092bdd6a90aSFam Zheng } 1093b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1094bdd6a90aSFam Zheng 1095bdd6a90aSFam Zheng data.co = qemu_coroutine_self(); 1096bdd6a90aSFam Zheng while (data.ret == -EINPROGRESS) { 1097bdd6a90aSFam Zheng qemu_coroutine_yield(); 1098bdd6a90aSFam Zheng } 1099bdd6a90aSFam Zheng 1100bdd6a90aSFam Zheng qemu_co_mutex_lock(&s->dma_map_lock); 1101bdd6a90aSFam Zheng r = nvme_cmd_unmap_qiov(bs, qiov); 1102bdd6a90aSFam Zheng qemu_co_mutex_unlock(&s->dma_map_lock); 1103bdd6a90aSFam Zheng if (r) { 1104bdd6a90aSFam Zheng return r; 1105bdd6a90aSFam Zheng } 1106bdd6a90aSFam Zheng 1107bdd6a90aSFam Zheng trace_nvme_rw_done(s, is_write, offset, bytes, data.ret); 1108bdd6a90aSFam Zheng return data.ret; 1109bdd6a90aSFam Zheng } 1110bdd6a90aSFam Zheng 1111bdd6a90aSFam Zheng static inline bool nvme_qiov_aligned(BlockDriverState *bs, 1112bdd6a90aSFam Zheng const QEMUIOVector *qiov) 1113bdd6a90aSFam Zheng { 1114bdd6a90aSFam Zheng int i; 1115bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1116bdd6a90aSFam Zheng 1117bdd6a90aSFam Zheng for (i = 0; i < qiov->niov; ++i) { 1118bdd6a90aSFam Zheng if (!QEMU_PTR_IS_ALIGNED(qiov->iov[i].iov_base, s->page_size) || 1119bdd6a90aSFam Zheng !QEMU_IS_ALIGNED(qiov->iov[i].iov_len, s->page_size)) { 1120bdd6a90aSFam Zheng trace_nvme_qiov_unaligned(qiov, i, qiov->iov[i].iov_base, 1121bdd6a90aSFam Zheng qiov->iov[i].iov_len, s->page_size); 1122bdd6a90aSFam Zheng return false; 1123bdd6a90aSFam Zheng } 1124bdd6a90aSFam Zheng } 1125bdd6a90aSFam Zheng return true; 1126bdd6a90aSFam Zheng } 1127bdd6a90aSFam Zheng 1128bdd6a90aSFam Zheng static int nvme_co_prw(BlockDriverState *bs, uint64_t offset, uint64_t bytes, 1129bdd6a90aSFam Zheng QEMUIOVector *qiov, bool is_write, int flags) 1130bdd6a90aSFam Zheng { 1131bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1132bdd6a90aSFam Zheng int r; 1133bdd6a90aSFam Zheng uint8_t *buf = NULL; 1134bdd6a90aSFam Zheng QEMUIOVector local_qiov; 1135bdd6a90aSFam Zheng 1136bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(offset, s->page_size)); 1137bdd6a90aSFam Zheng assert(QEMU_IS_ALIGNED(bytes, s->page_size)); 1138bdd6a90aSFam Zheng assert(bytes <= s->max_transfer); 1139bdd6a90aSFam Zheng if (nvme_qiov_aligned(bs, qiov)) { 1140bdd6a90aSFam Zheng return nvme_co_prw_aligned(bs, offset, bytes, qiov, is_write, flags); 1141bdd6a90aSFam Zheng } 1142bdd6a90aSFam Zheng trace_nvme_prw_buffered(s, offset, bytes, qiov->niov, is_write); 1143bdd6a90aSFam Zheng buf = qemu_try_blockalign(bs, bytes); 1144bdd6a90aSFam Zheng 1145bdd6a90aSFam Zheng if (!buf) { 1146bdd6a90aSFam Zheng return -ENOMEM; 1147bdd6a90aSFam Zheng } 1148bdd6a90aSFam Zheng qemu_iovec_init(&local_qiov, 1); 1149bdd6a90aSFam Zheng if (is_write) { 1150bdd6a90aSFam Zheng qemu_iovec_to_buf(qiov, 0, buf, bytes); 1151bdd6a90aSFam Zheng } 1152bdd6a90aSFam Zheng qemu_iovec_add(&local_qiov, buf, bytes); 1153bdd6a90aSFam Zheng r = nvme_co_prw_aligned(bs, offset, bytes, &local_qiov, is_write, flags); 1154bdd6a90aSFam Zheng qemu_iovec_destroy(&local_qiov); 1155bdd6a90aSFam Zheng if (!r && !is_write) { 1156bdd6a90aSFam Zheng qemu_iovec_from_buf(qiov, 0, buf, bytes); 1157bdd6a90aSFam Zheng } 1158bdd6a90aSFam Zheng qemu_vfree(buf); 1159bdd6a90aSFam Zheng return r; 1160bdd6a90aSFam Zheng } 1161bdd6a90aSFam Zheng 1162bdd6a90aSFam Zheng static coroutine_fn int nvme_co_preadv(BlockDriverState *bs, 1163bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 1164bdd6a90aSFam Zheng QEMUIOVector *qiov, int flags) 1165bdd6a90aSFam Zheng { 1166bdd6a90aSFam Zheng return nvme_co_prw(bs, offset, bytes, qiov, false, flags); 1167bdd6a90aSFam Zheng } 1168bdd6a90aSFam Zheng 1169bdd6a90aSFam Zheng static coroutine_fn int nvme_co_pwritev(BlockDriverState *bs, 1170bdd6a90aSFam Zheng uint64_t offset, uint64_t bytes, 1171bdd6a90aSFam Zheng QEMUIOVector *qiov, int flags) 1172bdd6a90aSFam Zheng { 1173bdd6a90aSFam Zheng return nvme_co_prw(bs, offset, bytes, qiov, true, flags); 1174bdd6a90aSFam Zheng } 1175bdd6a90aSFam Zheng 1176bdd6a90aSFam Zheng static coroutine_fn int nvme_co_flush(BlockDriverState *bs) 1177bdd6a90aSFam Zheng { 1178bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 117973159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1180bdd6a90aSFam Zheng NVMeRequest *req; 1181bdd6a90aSFam Zheng NvmeCmd cmd = { 1182bdd6a90aSFam Zheng .opcode = NVME_CMD_FLUSH, 1183bdd6a90aSFam Zheng .nsid = cpu_to_le32(s->nsid), 1184bdd6a90aSFam Zheng }; 1185bdd6a90aSFam Zheng NVMeCoData data = { 1186bdd6a90aSFam Zheng .ctx = bdrv_get_aio_context(bs), 1187bdd6a90aSFam Zheng .ret = -EINPROGRESS, 1188bdd6a90aSFam Zheng }; 1189bdd6a90aSFam Zheng 1190bdd6a90aSFam Zheng assert(s->nr_queues > 1); 1191bdd6a90aSFam Zheng req = nvme_get_free_req(ioq); 1192bdd6a90aSFam Zheng assert(req); 1193b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1194bdd6a90aSFam Zheng 1195bdd6a90aSFam Zheng data.co = qemu_coroutine_self(); 1196bdd6a90aSFam Zheng if (data.ret == -EINPROGRESS) { 1197bdd6a90aSFam Zheng qemu_coroutine_yield(); 1198bdd6a90aSFam Zheng } 1199bdd6a90aSFam Zheng 1200bdd6a90aSFam Zheng return data.ret; 1201bdd6a90aSFam Zheng } 1202bdd6a90aSFam Zheng 1203bdd6a90aSFam Zheng 1204e0dd95e3SMaxim Levitsky static coroutine_fn int nvme_co_pwrite_zeroes(BlockDriverState *bs, 1205e0dd95e3SMaxim Levitsky int64_t offset, 1206e0dd95e3SMaxim Levitsky int bytes, 1207e0dd95e3SMaxim Levitsky BdrvRequestFlags flags) 1208e0dd95e3SMaxim Levitsky { 1209e0dd95e3SMaxim Levitsky BDRVNVMeState *s = bs->opaque; 121073159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1211e0dd95e3SMaxim Levitsky NVMeRequest *req; 1212e0dd95e3SMaxim Levitsky 1213e0dd95e3SMaxim Levitsky uint32_t cdw12 = ((bytes >> s->blkshift) - 1) & 0xFFFF; 1214e0dd95e3SMaxim Levitsky 1215e0dd95e3SMaxim Levitsky if (!s->supports_write_zeroes) { 1216e0dd95e3SMaxim Levitsky return -ENOTSUP; 1217e0dd95e3SMaxim Levitsky } 1218e0dd95e3SMaxim Levitsky 1219e0dd95e3SMaxim Levitsky NvmeCmd cmd = { 122069265150SKlaus Jensen .opcode = NVME_CMD_WRITE_ZEROES, 1221e0dd95e3SMaxim Levitsky .nsid = cpu_to_le32(s->nsid), 1222e0dd95e3SMaxim Levitsky .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF), 1223e0dd95e3SMaxim Levitsky .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF), 1224e0dd95e3SMaxim Levitsky }; 1225e0dd95e3SMaxim Levitsky 1226e0dd95e3SMaxim Levitsky NVMeCoData data = { 1227e0dd95e3SMaxim Levitsky .ctx = bdrv_get_aio_context(bs), 1228e0dd95e3SMaxim Levitsky .ret = -EINPROGRESS, 1229e0dd95e3SMaxim Levitsky }; 1230e0dd95e3SMaxim Levitsky 1231e0dd95e3SMaxim Levitsky if (flags & BDRV_REQ_MAY_UNMAP) { 1232e0dd95e3SMaxim Levitsky cdw12 |= (1 << 25); 1233e0dd95e3SMaxim Levitsky } 1234e0dd95e3SMaxim Levitsky 1235e0dd95e3SMaxim Levitsky if (flags & BDRV_REQ_FUA) { 1236e0dd95e3SMaxim Levitsky cdw12 |= (1 << 30); 1237e0dd95e3SMaxim Levitsky } 1238e0dd95e3SMaxim Levitsky 1239e0dd95e3SMaxim Levitsky cmd.cdw12 = cpu_to_le32(cdw12); 1240e0dd95e3SMaxim Levitsky 1241e0dd95e3SMaxim Levitsky trace_nvme_write_zeroes(s, offset, bytes, flags); 1242e0dd95e3SMaxim Levitsky assert(s->nr_queues > 1); 1243e0dd95e3SMaxim Levitsky req = nvme_get_free_req(ioq); 1244e0dd95e3SMaxim Levitsky assert(req); 1245e0dd95e3SMaxim Levitsky 1246b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1247e0dd95e3SMaxim Levitsky 1248e0dd95e3SMaxim Levitsky data.co = qemu_coroutine_self(); 1249e0dd95e3SMaxim Levitsky while (data.ret == -EINPROGRESS) { 1250e0dd95e3SMaxim Levitsky qemu_coroutine_yield(); 1251e0dd95e3SMaxim Levitsky } 1252e0dd95e3SMaxim Levitsky 1253e0dd95e3SMaxim Levitsky trace_nvme_rw_done(s, true, offset, bytes, data.ret); 1254e0dd95e3SMaxim Levitsky return data.ret; 1255e0dd95e3SMaxim Levitsky } 1256e0dd95e3SMaxim Levitsky 1257e0dd95e3SMaxim Levitsky 1258e87a09d6SMaxim Levitsky static int coroutine_fn nvme_co_pdiscard(BlockDriverState *bs, 1259e87a09d6SMaxim Levitsky int64_t offset, 1260e87a09d6SMaxim Levitsky int bytes) 1261e87a09d6SMaxim Levitsky { 1262e87a09d6SMaxim Levitsky BDRVNVMeState *s = bs->opaque; 126373159e52SPhilippe Mathieu-Daudé NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1264e87a09d6SMaxim Levitsky NVMeRequest *req; 1265e87a09d6SMaxim Levitsky NvmeDsmRange *buf; 1266e87a09d6SMaxim Levitsky QEMUIOVector local_qiov; 1267e87a09d6SMaxim Levitsky int ret; 1268e87a09d6SMaxim Levitsky 1269e87a09d6SMaxim Levitsky NvmeCmd cmd = { 1270e87a09d6SMaxim Levitsky .opcode = NVME_CMD_DSM, 1271e87a09d6SMaxim Levitsky .nsid = cpu_to_le32(s->nsid), 1272e87a09d6SMaxim Levitsky .cdw10 = cpu_to_le32(0), /*number of ranges - 0 based*/ 1273e87a09d6SMaxim Levitsky .cdw11 = cpu_to_le32(1 << 2), /*deallocate bit*/ 1274e87a09d6SMaxim Levitsky }; 1275e87a09d6SMaxim Levitsky 1276e87a09d6SMaxim Levitsky NVMeCoData data = { 1277e87a09d6SMaxim Levitsky .ctx = bdrv_get_aio_context(bs), 1278e87a09d6SMaxim Levitsky .ret = -EINPROGRESS, 1279e87a09d6SMaxim Levitsky }; 1280e87a09d6SMaxim Levitsky 1281e87a09d6SMaxim Levitsky if (!s->supports_discard) { 1282e87a09d6SMaxim Levitsky return -ENOTSUP; 1283e87a09d6SMaxim Levitsky } 1284e87a09d6SMaxim Levitsky 1285e87a09d6SMaxim Levitsky assert(s->nr_queues > 1); 1286e87a09d6SMaxim Levitsky 1287e87a09d6SMaxim Levitsky buf = qemu_try_blockalign0(bs, s->page_size); 1288e87a09d6SMaxim Levitsky if (!buf) { 1289e87a09d6SMaxim Levitsky return -ENOMEM; 1290e87a09d6SMaxim Levitsky } 1291e87a09d6SMaxim Levitsky 1292e87a09d6SMaxim Levitsky buf->nlb = cpu_to_le32(bytes >> s->blkshift); 1293e87a09d6SMaxim Levitsky buf->slba = cpu_to_le64(offset >> s->blkshift); 1294e87a09d6SMaxim Levitsky buf->cattr = 0; 1295e87a09d6SMaxim Levitsky 1296e87a09d6SMaxim Levitsky qemu_iovec_init(&local_qiov, 1); 1297e87a09d6SMaxim Levitsky qemu_iovec_add(&local_qiov, buf, 4096); 1298e87a09d6SMaxim Levitsky 1299e87a09d6SMaxim Levitsky req = nvme_get_free_req(ioq); 1300e87a09d6SMaxim Levitsky assert(req); 1301e87a09d6SMaxim Levitsky 1302e87a09d6SMaxim Levitsky qemu_co_mutex_lock(&s->dma_map_lock); 1303e87a09d6SMaxim Levitsky ret = nvme_cmd_map_qiov(bs, &cmd, req, &local_qiov); 1304e87a09d6SMaxim Levitsky qemu_co_mutex_unlock(&s->dma_map_lock); 1305e87a09d6SMaxim Levitsky 1306e87a09d6SMaxim Levitsky if (ret) { 1307b75fd5f5SStefan Hajnoczi nvme_put_free_req_and_wake(ioq, req); 1308e87a09d6SMaxim Levitsky goto out; 1309e87a09d6SMaxim Levitsky } 1310e87a09d6SMaxim Levitsky 1311e87a09d6SMaxim Levitsky trace_nvme_dsm(s, offset, bytes); 1312e87a09d6SMaxim Levitsky 1313b75fd5f5SStefan Hajnoczi nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1314e87a09d6SMaxim Levitsky 1315e87a09d6SMaxim Levitsky data.co = qemu_coroutine_self(); 1316e87a09d6SMaxim Levitsky while (data.ret == -EINPROGRESS) { 1317e87a09d6SMaxim Levitsky qemu_coroutine_yield(); 1318e87a09d6SMaxim Levitsky } 1319e87a09d6SMaxim Levitsky 1320e87a09d6SMaxim Levitsky qemu_co_mutex_lock(&s->dma_map_lock); 1321e87a09d6SMaxim Levitsky ret = nvme_cmd_unmap_qiov(bs, &local_qiov); 1322e87a09d6SMaxim Levitsky qemu_co_mutex_unlock(&s->dma_map_lock); 1323e87a09d6SMaxim Levitsky 1324e87a09d6SMaxim Levitsky if (ret) { 1325e87a09d6SMaxim Levitsky goto out; 1326e87a09d6SMaxim Levitsky } 1327e87a09d6SMaxim Levitsky 1328e87a09d6SMaxim Levitsky ret = data.ret; 1329e87a09d6SMaxim Levitsky trace_nvme_dsm_done(s, offset, bytes, ret); 1330e87a09d6SMaxim Levitsky out: 1331e87a09d6SMaxim Levitsky qemu_iovec_destroy(&local_qiov); 1332e87a09d6SMaxim Levitsky qemu_vfree(buf); 1333e87a09d6SMaxim Levitsky return ret; 1334e87a09d6SMaxim Levitsky 1335e87a09d6SMaxim Levitsky } 1336e87a09d6SMaxim Levitsky 1337e87a09d6SMaxim Levitsky 1338bdd6a90aSFam Zheng static int nvme_reopen_prepare(BDRVReopenState *reopen_state, 1339bdd6a90aSFam Zheng BlockReopenQueue *queue, Error **errp) 1340bdd6a90aSFam Zheng { 1341bdd6a90aSFam Zheng return 0; 1342bdd6a90aSFam Zheng } 1343bdd6a90aSFam Zheng 1344998b3a1eSMax Reitz static void nvme_refresh_filename(BlockDriverState *bs) 1345bdd6a90aSFam Zheng { 1346cc61b074SMax Reitz BDRVNVMeState *s = bs->opaque; 1347bdd6a90aSFam Zheng 1348cc61b074SMax Reitz snprintf(bs->exact_filename, sizeof(bs->exact_filename), "nvme://%s/%i", 1349cc61b074SMax Reitz s->device, s->nsid); 1350bdd6a90aSFam Zheng } 1351bdd6a90aSFam Zheng 1352bdd6a90aSFam Zheng static void nvme_refresh_limits(BlockDriverState *bs, Error **errp) 1353bdd6a90aSFam Zheng { 1354bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1355bdd6a90aSFam Zheng 1356bdd6a90aSFam Zheng bs->bl.opt_mem_alignment = s->page_size; 1357bdd6a90aSFam Zheng bs->bl.request_alignment = s->page_size; 1358bdd6a90aSFam Zheng bs->bl.max_transfer = s->max_transfer; 1359bdd6a90aSFam Zheng } 1360bdd6a90aSFam Zheng 1361bdd6a90aSFam Zheng static void nvme_detach_aio_context(BlockDriverState *bs) 1362bdd6a90aSFam Zheng { 1363bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1364bdd6a90aSFam Zheng 13657838c67fSStefan Hajnoczi for (int i = 0; i < s->nr_queues; i++) { 13667838c67fSStefan Hajnoczi NVMeQueuePair *q = s->queues[i]; 13677838c67fSStefan Hajnoczi 13687838c67fSStefan Hajnoczi qemu_bh_delete(q->completion_bh); 13697838c67fSStefan Hajnoczi q->completion_bh = NULL; 13707838c67fSStefan Hajnoczi } 13717838c67fSStefan Hajnoczi 1372bdd6a90aSFam Zheng aio_set_event_notifier(bdrv_get_aio_context(bs), &s->irq_notifier, 1373bdd6a90aSFam Zheng false, NULL, NULL); 1374bdd6a90aSFam Zheng } 1375bdd6a90aSFam Zheng 1376bdd6a90aSFam Zheng static void nvme_attach_aio_context(BlockDriverState *bs, 1377bdd6a90aSFam Zheng AioContext *new_context) 1378bdd6a90aSFam Zheng { 1379bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1380bdd6a90aSFam Zheng 1381bdd6a90aSFam Zheng s->aio_context = new_context; 1382bdd6a90aSFam Zheng aio_set_event_notifier(new_context, &s->irq_notifier, 1383bdd6a90aSFam Zheng false, nvme_handle_event, nvme_poll_cb); 13847838c67fSStefan Hajnoczi 13857838c67fSStefan Hajnoczi for (int i = 0; i < s->nr_queues; i++) { 13867838c67fSStefan Hajnoczi NVMeQueuePair *q = s->queues[i]; 13877838c67fSStefan Hajnoczi 13887838c67fSStefan Hajnoczi q->completion_bh = 13897838c67fSStefan Hajnoczi aio_bh_new(new_context, nvme_process_completion_bh, q); 13907838c67fSStefan Hajnoczi } 1391bdd6a90aSFam Zheng } 1392bdd6a90aSFam Zheng 1393bdd6a90aSFam Zheng static void nvme_aio_plug(BlockDriverState *bs) 1394bdd6a90aSFam Zheng { 1395bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 13962f0d8947SPaolo Bonzini assert(!s->plugged); 13972f0d8947SPaolo Bonzini s->plugged = true; 1398bdd6a90aSFam Zheng } 1399bdd6a90aSFam Zheng 1400bdd6a90aSFam Zheng static void nvme_aio_unplug(BlockDriverState *bs) 1401bdd6a90aSFam Zheng { 1402bdd6a90aSFam Zheng int i; 1403bdd6a90aSFam Zheng BDRVNVMeState *s = bs->opaque; 1404bdd6a90aSFam Zheng assert(s->plugged); 14052f0d8947SPaolo Bonzini s->plugged = false; 140673159e52SPhilippe Mathieu-Daudé for (i = INDEX_IO(0); i < s->nr_queues; i++) { 1407bdd6a90aSFam Zheng NVMeQueuePair *q = s->queues[i]; 1408bdd6a90aSFam Zheng qemu_mutex_lock(&q->lock); 1409b75fd5f5SStefan Hajnoczi nvme_kick(q); 1410b75fd5f5SStefan Hajnoczi nvme_process_completion(q); 1411bdd6a90aSFam Zheng qemu_mutex_unlock(&q->lock); 1412bdd6a90aSFam Zheng } 1413bdd6a90aSFam Zheng } 1414bdd6a90aSFam Zheng 14159ed61612SFam Zheng static void nvme_register_buf(BlockDriverState *bs, void *host, size_t size) 14169ed61612SFam Zheng { 14179ed61612SFam Zheng int ret; 14189ed61612SFam Zheng BDRVNVMeState *s = bs->opaque; 14199ed61612SFam Zheng 14209ed61612SFam Zheng ret = qemu_vfio_dma_map(s->vfio, host, size, false, NULL); 14219ed61612SFam Zheng if (ret) { 14229ed61612SFam Zheng /* FIXME: we may run out of IOVA addresses after repeated 14239ed61612SFam Zheng * bdrv_register_buf/bdrv_unregister_buf, because nvme_vfio_dma_unmap 14249ed61612SFam Zheng * doesn't reclaim addresses for fixed mappings. */ 14259ed61612SFam Zheng error_report("nvme_register_buf failed: %s", strerror(-ret)); 14269ed61612SFam Zheng } 14279ed61612SFam Zheng } 14289ed61612SFam Zheng 14299ed61612SFam Zheng static void nvme_unregister_buf(BlockDriverState *bs, void *host) 14309ed61612SFam Zheng { 14319ed61612SFam Zheng BDRVNVMeState *s = bs->opaque; 14329ed61612SFam Zheng 14339ed61612SFam Zheng qemu_vfio_dma_unmap(s->vfio, host); 14349ed61612SFam Zheng } 14359ed61612SFam Zheng 14362654267cSMax Reitz static const char *const nvme_strong_runtime_opts[] = { 14372654267cSMax Reitz NVME_BLOCK_OPT_DEVICE, 14382654267cSMax Reitz NVME_BLOCK_OPT_NAMESPACE, 14392654267cSMax Reitz 14402654267cSMax Reitz NULL 14412654267cSMax Reitz }; 14422654267cSMax Reitz 1443bdd6a90aSFam Zheng static BlockDriver bdrv_nvme = { 1444bdd6a90aSFam Zheng .format_name = "nvme", 1445bdd6a90aSFam Zheng .protocol_name = "nvme", 1446bdd6a90aSFam Zheng .instance_size = sizeof(BDRVNVMeState), 1447bdd6a90aSFam Zheng 14485a5e7f8cSMaxim Levitsky .bdrv_co_create_opts = bdrv_co_create_opts_simple, 14495a5e7f8cSMaxim Levitsky .create_opts = &bdrv_create_opts_simple, 14505a5e7f8cSMaxim Levitsky 1451bdd6a90aSFam Zheng .bdrv_parse_filename = nvme_parse_filename, 1452bdd6a90aSFam Zheng .bdrv_file_open = nvme_file_open, 1453bdd6a90aSFam Zheng .bdrv_close = nvme_close, 1454bdd6a90aSFam Zheng .bdrv_getlength = nvme_getlength, 1455118d1b6aSMaxim Levitsky .bdrv_probe_blocksizes = nvme_probe_blocksizes, 1456bdd6a90aSFam Zheng 1457bdd6a90aSFam Zheng .bdrv_co_preadv = nvme_co_preadv, 1458bdd6a90aSFam Zheng .bdrv_co_pwritev = nvme_co_pwritev, 1459e0dd95e3SMaxim Levitsky 1460e0dd95e3SMaxim Levitsky .bdrv_co_pwrite_zeroes = nvme_co_pwrite_zeroes, 1461e87a09d6SMaxim Levitsky .bdrv_co_pdiscard = nvme_co_pdiscard, 1462e0dd95e3SMaxim Levitsky 1463bdd6a90aSFam Zheng .bdrv_co_flush_to_disk = nvme_co_flush, 1464bdd6a90aSFam Zheng .bdrv_reopen_prepare = nvme_reopen_prepare, 1465bdd6a90aSFam Zheng 1466bdd6a90aSFam Zheng .bdrv_refresh_filename = nvme_refresh_filename, 1467bdd6a90aSFam Zheng .bdrv_refresh_limits = nvme_refresh_limits, 14682654267cSMax Reitz .strong_runtime_opts = nvme_strong_runtime_opts, 1469bdd6a90aSFam Zheng 1470bdd6a90aSFam Zheng .bdrv_detach_aio_context = nvme_detach_aio_context, 1471bdd6a90aSFam Zheng .bdrv_attach_aio_context = nvme_attach_aio_context, 1472bdd6a90aSFam Zheng 1473bdd6a90aSFam Zheng .bdrv_io_plug = nvme_aio_plug, 1474bdd6a90aSFam Zheng .bdrv_io_unplug = nvme_aio_unplug, 14759ed61612SFam Zheng 14769ed61612SFam Zheng .bdrv_register_buf = nvme_register_buf, 14779ed61612SFam Zheng .bdrv_unregister_buf = nvme_unregister_buf, 1478bdd6a90aSFam Zheng }; 1479bdd6a90aSFam Zheng 1480bdd6a90aSFam Zheng static void bdrv_nvme_init(void) 1481bdd6a90aSFam Zheng { 1482bdd6a90aSFam Zheng bdrv_register(&bdrv_nvme); 1483bdd6a90aSFam Zheng } 1484bdd6a90aSFam Zheng 1485bdd6a90aSFam Zheng block_init(bdrv_nvme_init); 1486