1 /* 2 * NVMe block driver based on vfio 3 * 4 * Copyright 2016 - 2018 Red Hat, Inc. 5 * 6 * Authors: 7 * Fam Zheng <famz@redhat.com> 8 * Paolo Bonzini <pbonzini@redhat.com> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2 or later. 11 * See the COPYING file in the top-level directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include <linux/vfio.h> 16 #include "qapi/error.h" 17 #include "qapi/qmp/qdict.h" 18 #include "qapi/qmp/qstring.h" 19 #include "qemu/error-report.h" 20 #include "qemu/main-loop.h" 21 #include "qemu/module.h" 22 #include "qemu/cutils.h" 23 #include "qemu/option.h" 24 #include "qemu/memalign.h" 25 #include "qemu/vfio-helpers.h" 26 #include "block/block-io.h" 27 #include "block/block_int.h" 28 #include "sysemu/block-backend.h" 29 #include "sysemu/replay.h" 30 #include "trace.h" 31 32 #include "block/nvme.h" 33 34 #define NVME_SQ_ENTRY_BYTES 64 35 #define NVME_CQ_ENTRY_BYTES 16 36 #define NVME_QUEUE_SIZE 128 37 #define NVME_DOORBELL_SIZE 4096 38 39 /* 40 * We have to leave one slot empty as that is the full queue case where 41 * head == tail + 1. 42 */ 43 #define NVME_NUM_REQS (NVME_QUEUE_SIZE - 1) 44 45 typedef struct BDRVNVMeState BDRVNVMeState; 46 47 /* Same index is used for queues and IRQs */ 48 #define INDEX_ADMIN 0 49 #define INDEX_IO(n) (1 + n) 50 51 /* This driver shares a single MSIX IRQ for the admin and I/O queues */ 52 enum { 53 MSIX_SHARED_IRQ_IDX = 0, 54 MSIX_IRQ_COUNT = 1 55 }; 56 57 typedef struct { 58 int32_t head, tail; 59 uint8_t *queue; 60 uint64_t iova; 61 /* Hardware MMIO register */ 62 volatile uint32_t *doorbell; 63 } NVMeQueue; 64 65 typedef struct { 66 BlockCompletionFunc *cb; 67 void *opaque; 68 int cid; 69 void *prp_list_page; 70 uint64_t prp_list_iova; 71 int free_req_next; /* q->reqs[] index of next free req */ 72 } NVMeRequest; 73 74 typedef struct { 75 QemuMutex lock; 76 77 /* Read from I/O code path, initialized under BQL */ 78 BDRVNVMeState *s; 79 int index; 80 81 /* Fields protected by BQL */ 82 uint8_t *prp_list_pages; 83 84 /* Fields protected by @lock */ 85 CoQueue free_req_queue; 86 NVMeQueue sq, cq; 87 int cq_phase; 88 int free_req_head; 89 NVMeRequest reqs[NVME_NUM_REQS]; 90 int need_kick; 91 int inflight; 92 93 /* Thread-safe, no lock necessary */ 94 QEMUBH *completion_bh; 95 } NVMeQueuePair; 96 97 struct BDRVNVMeState { 98 AioContext *aio_context; 99 QEMUVFIOState *vfio; 100 void *bar0_wo_map; 101 /* Memory mapped registers */ 102 volatile struct { 103 uint32_t sq_tail; 104 uint32_t cq_head; 105 } *doorbells; 106 /* The submission/completion queue pairs. 107 * [0]: admin queue. 108 * [1..]: io queues. 109 */ 110 NVMeQueuePair **queues; 111 unsigned queue_count; 112 size_t page_size; 113 /* How many uint32_t elements does each doorbell entry take. */ 114 size_t doorbell_scale; 115 bool write_cache_supported; 116 EventNotifier irq_notifier[MSIX_IRQ_COUNT]; 117 118 uint64_t nsze; /* Namespace size reported by identify command */ 119 int nsid; /* The namespace id to read/write data. */ 120 int blkshift; 121 122 uint64_t max_transfer; 123 124 bool supports_write_zeroes; 125 bool supports_discard; 126 127 CoMutex dma_map_lock; 128 CoQueue dma_flush_queue; 129 130 /* Total size of mapped qiov, accessed under dma_map_lock */ 131 int dma_map_count; 132 133 /* PCI address (required for nvme_refresh_filename()) */ 134 char *device; 135 136 struct { 137 uint64_t completion_errors; 138 uint64_t aligned_accesses; 139 uint64_t unaligned_accesses; 140 } stats; 141 }; 142 143 #define NVME_BLOCK_OPT_DEVICE "device" 144 #define NVME_BLOCK_OPT_NAMESPACE "namespace" 145 146 static void nvme_process_completion_bh(void *opaque); 147 148 static QemuOptsList runtime_opts = { 149 .name = "nvme", 150 .head = QTAILQ_HEAD_INITIALIZER(runtime_opts.head), 151 .desc = { 152 { 153 .name = NVME_BLOCK_OPT_DEVICE, 154 .type = QEMU_OPT_STRING, 155 .help = "NVMe PCI device address", 156 }, 157 { 158 .name = NVME_BLOCK_OPT_NAMESPACE, 159 .type = QEMU_OPT_NUMBER, 160 .help = "NVMe namespace", 161 }, 162 { /* end of list */ } 163 }, 164 }; 165 166 /* Returns true on success, false on failure. */ 167 static bool nvme_init_queue(BDRVNVMeState *s, NVMeQueue *q, 168 unsigned nentries, size_t entry_bytes, Error **errp) 169 { 170 size_t bytes; 171 int r; 172 173 bytes = ROUND_UP(nentries * entry_bytes, qemu_real_host_page_size()); 174 q->head = q->tail = 0; 175 q->queue = qemu_try_memalign(qemu_real_host_page_size(), bytes); 176 if (!q->queue) { 177 error_setg(errp, "Cannot allocate queue"); 178 return false; 179 } 180 memset(q->queue, 0, bytes); 181 r = qemu_vfio_dma_map(s->vfio, q->queue, bytes, false, &q->iova, errp); 182 if (r) { 183 error_prepend(errp, "Cannot map queue: "); 184 } 185 return r == 0; 186 } 187 188 static void nvme_free_queue(NVMeQueue *q) 189 { 190 qemu_vfree(q->queue); 191 } 192 193 static void nvme_free_queue_pair(NVMeQueuePair *q) 194 { 195 trace_nvme_free_queue_pair(q->index, q, &q->cq, &q->sq); 196 if (q->completion_bh) { 197 qemu_bh_delete(q->completion_bh); 198 } 199 nvme_free_queue(&q->sq); 200 nvme_free_queue(&q->cq); 201 qemu_vfree(q->prp_list_pages); 202 qemu_mutex_destroy(&q->lock); 203 g_free(q); 204 } 205 206 static void nvme_free_req_queue_cb(void *opaque) 207 { 208 NVMeQueuePair *q = opaque; 209 210 qemu_mutex_lock(&q->lock); 211 while (q->free_req_head != -1 && 212 qemu_co_enter_next(&q->free_req_queue, &q->lock)) { 213 /* Retry waiting requests */ 214 } 215 qemu_mutex_unlock(&q->lock); 216 } 217 218 static NVMeQueuePair *nvme_create_queue_pair(BDRVNVMeState *s, 219 AioContext *aio_context, 220 unsigned idx, size_t size, 221 Error **errp) 222 { 223 int i, r; 224 NVMeQueuePair *q; 225 uint64_t prp_list_iova; 226 size_t bytes; 227 228 q = g_try_new0(NVMeQueuePair, 1); 229 if (!q) { 230 error_setg(errp, "Cannot allocate queue pair"); 231 return NULL; 232 } 233 trace_nvme_create_queue_pair(idx, q, size, aio_context, 234 event_notifier_get_fd(s->irq_notifier)); 235 bytes = QEMU_ALIGN_UP(s->page_size * NVME_NUM_REQS, 236 qemu_real_host_page_size()); 237 q->prp_list_pages = qemu_try_memalign(qemu_real_host_page_size(), bytes); 238 if (!q->prp_list_pages) { 239 error_setg(errp, "Cannot allocate PRP page list"); 240 goto fail; 241 } 242 memset(q->prp_list_pages, 0, bytes); 243 qemu_mutex_init(&q->lock); 244 q->s = s; 245 q->index = idx; 246 qemu_co_queue_init(&q->free_req_queue); 247 q->completion_bh = aio_bh_new(aio_context, nvme_process_completion_bh, q); 248 r = qemu_vfio_dma_map(s->vfio, q->prp_list_pages, bytes, 249 false, &prp_list_iova, errp); 250 if (r) { 251 error_prepend(errp, "Cannot map buffer for DMA: "); 252 goto fail; 253 } 254 q->free_req_head = -1; 255 for (i = 0; i < NVME_NUM_REQS; i++) { 256 NVMeRequest *req = &q->reqs[i]; 257 req->cid = i + 1; 258 req->free_req_next = q->free_req_head; 259 q->free_req_head = i; 260 req->prp_list_page = q->prp_list_pages + i * s->page_size; 261 req->prp_list_iova = prp_list_iova + i * s->page_size; 262 } 263 264 if (!nvme_init_queue(s, &q->sq, size, NVME_SQ_ENTRY_BYTES, errp)) { 265 goto fail; 266 } 267 q->sq.doorbell = &s->doorbells[idx * s->doorbell_scale].sq_tail; 268 269 if (!nvme_init_queue(s, &q->cq, size, NVME_CQ_ENTRY_BYTES, errp)) { 270 goto fail; 271 } 272 q->cq.doorbell = &s->doorbells[idx * s->doorbell_scale].cq_head; 273 274 return q; 275 fail: 276 nvme_free_queue_pair(q); 277 return NULL; 278 } 279 280 /* With q->lock */ 281 static void nvme_kick(NVMeQueuePair *q) 282 { 283 BDRVNVMeState *s = q->s; 284 285 if (!q->need_kick) { 286 return; 287 } 288 trace_nvme_kick(s, q->index); 289 assert(!(q->sq.tail & 0xFF00)); 290 /* Fence the write to submission queue entry before notifying the device. */ 291 smp_wmb(); 292 *q->sq.doorbell = cpu_to_le32(q->sq.tail); 293 q->inflight += q->need_kick; 294 q->need_kick = 0; 295 } 296 297 static NVMeRequest *nvme_get_free_req_nofail_locked(NVMeQueuePair *q) 298 { 299 NVMeRequest *req; 300 301 req = &q->reqs[q->free_req_head]; 302 q->free_req_head = req->free_req_next; 303 req->free_req_next = -1; 304 return req; 305 } 306 307 /* Return a free request element if any, otherwise return NULL. */ 308 static NVMeRequest *nvme_get_free_req_nowait(NVMeQueuePair *q) 309 { 310 QEMU_LOCK_GUARD(&q->lock); 311 if (q->free_req_head == -1) { 312 return NULL; 313 } 314 return nvme_get_free_req_nofail_locked(q); 315 } 316 317 /* 318 * Wait for a free request to become available if necessary, then 319 * return it. 320 */ 321 static coroutine_fn NVMeRequest *nvme_get_free_req(NVMeQueuePair *q) 322 { 323 QEMU_LOCK_GUARD(&q->lock); 324 325 while (q->free_req_head == -1) { 326 trace_nvme_free_req_queue_wait(q->s, q->index); 327 qemu_co_queue_wait(&q->free_req_queue, &q->lock); 328 } 329 330 return nvme_get_free_req_nofail_locked(q); 331 } 332 333 /* With q->lock */ 334 static void nvme_put_free_req_locked(NVMeQueuePair *q, NVMeRequest *req) 335 { 336 req->free_req_next = q->free_req_head; 337 q->free_req_head = req - q->reqs; 338 } 339 340 /* With q->lock */ 341 static void nvme_wake_free_req_locked(NVMeQueuePair *q) 342 { 343 if (!qemu_co_queue_empty(&q->free_req_queue)) { 344 replay_bh_schedule_oneshot_event(q->s->aio_context, 345 nvme_free_req_queue_cb, q); 346 } 347 } 348 349 /* Insert a request in the freelist and wake waiters */ 350 static void nvme_put_free_req_and_wake(NVMeQueuePair *q, NVMeRequest *req) 351 { 352 qemu_mutex_lock(&q->lock); 353 nvme_put_free_req_locked(q, req); 354 nvme_wake_free_req_locked(q); 355 qemu_mutex_unlock(&q->lock); 356 } 357 358 static inline int nvme_translate_error(const NvmeCqe *c) 359 { 360 uint16_t status = (le16_to_cpu(c->status) >> 1) & 0xFF; 361 if (status) { 362 trace_nvme_error(le32_to_cpu(c->result), 363 le16_to_cpu(c->sq_head), 364 le16_to_cpu(c->sq_id), 365 le16_to_cpu(c->cid), 366 le16_to_cpu(status)); 367 } 368 switch (status) { 369 case 0: 370 return 0; 371 case 1: 372 return -ENOSYS; 373 case 2: 374 return -EINVAL; 375 default: 376 return -EIO; 377 } 378 } 379 380 /* With q->lock */ 381 static bool nvme_process_completion(NVMeQueuePair *q) 382 { 383 BDRVNVMeState *s = q->s; 384 bool progress = false; 385 NVMeRequest *preq; 386 NVMeRequest req; 387 NvmeCqe *c; 388 389 trace_nvme_process_completion(s, q->index, q->inflight); 390 391 /* 392 * Support re-entrancy when a request cb() function invokes aio_poll(). 393 * Pending completions must be visible to aio_poll() so that a cb() 394 * function can wait for the completion of another request. 395 * 396 * The aio_poll() loop will execute our BH and we'll resume completion 397 * processing there. 398 */ 399 qemu_bh_schedule(q->completion_bh); 400 401 assert(q->inflight >= 0); 402 while (q->inflight) { 403 int ret; 404 int16_t cid; 405 406 c = (NvmeCqe *)&q->cq.queue[q->cq.head * NVME_CQ_ENTRY_BYTES]; 407 if ((le16_to_cpu(c->status) & 0x1) == q->cq_phase) { 408 break; 409 } 410 ret = nvme_translate_error(c); 411 if (ret) { 412 s->stats.completion_errors++; 413 } 414 q->cq.head = (q->cq.head + 1) % NVME_QUEUE_SIZE; 415 if (!q->cq.head) { 416 q->cq_phase = !q->cq_phase; 417 } 418 cid = le16_to_cpu(c->cid); 419 if (cid == 0 || cid > NVME_QUEUE_SIZE) { 420 warn_report("NVMe: Unexpected CID in completion queue: %"PRIu32", " 421 "queue size: %u", cid, NVME_QUEUE_SIZE); 422 continue; 423 } 424 trace_nvme_complete_command(s, q->index, cid); 425 preq = &q->reqs[cid - 1]; 426 req = *preq; 427 assert(req.cid == cid); 428 assert(req.cb); 429 nvme_put_free_req_locked(q, preq); 430 preq->cb = preq->opaque = NULL; 431 q->inflight--; 432 qemu_mutex_unlock(&q->lock); 433 req.cb(req.opaque, ret); 434 qemu_mutex_lock(&q->lock); 435 progress = true; 436 } 437 if (progress) { 438 /* Notify the device so it can post more completions. */ 439 smp_mb_release(); 440 *q->cq.doorbell = cpu_to_le32(q->cq.head); 441 nvme_wake_free_req_locked(q); 442 } 443 444 qemu_bh_cancel(q->completion_bh); 445 446 return progress; 447 } 448 449 static void nvme_process_completion_bh(void *opaque) 450 { 451 NVMeQueuePair *q = opaque; 452 453 /* 454 * We're being invoked because a nvme_process_completion() cb() function 455 * called aio_poll(). The callback may be waiting for further completions 456 * so notify the device that it has space to fill in more completions now. 457 */ 458 smp_mb_release(); 459 *q->cq.doorbell = cpu_to_le32(q->cq.head); 460 nvme_wake_free_req_locked(q); 461 462 nvme_process_completion(q); 463 } 464 465 static void nvme_trace_command(const NvmeCmd *cmd) 466 { 467 int i; 468 469 if (!trace_event_get_state_backends(TRACE_NVME_SUBMIT_COMMAND_RAW)) { 470 return; 471 } 472 for (i = 0; i < 8; ++i) { 473 uint8_t *cmdp = (uint8_t *)cmd + i * 8; 474 trace_nvme_submit_command_raw(cmdp[0], cmdp[1], cmdp[2], cmdp[3], 475 cmdp[4], cmdp[5], cmdp[6], cmdp[7]); 476 } 477 } 478 479 static void nvme_unplug_fn(void *opaque) 480 { 481 NVMeQueuePair *q = opaque; 482 483 QEMU_LOCK_GUARD(&q->lock); 484 nvme_kick(q); 485 nvme_process_completion(q); 486 } 487 488 static void nvme_submit_command(NVMeQueuePair *q, NVMeRequest *req, 489 NvmeCmd *cmd, BlockCompletionFunc cb, 490 void *opaque) 491 { 492 assert(!req->cb); 493 req->cb = cb; 494 req->opaque = opaque; 495 cmd->cid = cpu_to_le16(req->cid); 496 497 trace_nvme_submit_command(q->s, q->index, req->cid); 498 nvme_trace_command(cmd); 499 qemu_mutex_lock(&q->lock); 500 memcpy((uint8_t *)q->sq.queue + 501 q->sq.tail * NVME_SQ_ENTRY_BYTES, cmd, sizeof(*cmd)); 502 q->sq.tail = (q->sq.tail + 1) % NVME_QUEUE_SIZE; 503 q->need_kick++; 504 blk_io_plug_call(nvme_unplug_fn, q); 505 qemu_mutex_unlock(&q->lock); 506 } 507 508 static void nvme_admin_cmd_sync_cb(void *opaque, int ret) 509 { 510 int *pret = opaque; 511 *pret = ret; 512 aio_wait_kick(); 513 } 514 515 static int nvme_admin_cmd_sync(BlockDriverState *bs, NvmeCmd *cmd) 516 { 517 BDRVNVMeState *s = bs->opaque; 518 NVMeQueuePair *q = s->queues[INDEX_ADMIN]; 519 AioContext *aio_context = bdrv_get_aio_context(bs); 520 NVMeRequest *req; 521 int ret = -EINPROGRESS; 522 req = nvme_get_free_req_nowait(q); 523 if (!req) { 524 return -EBUSY; 525 } 526 nvme_submit_command(q, req, cmd, nvme_admin_cmd_sync_cb, &ret); 527 528 AIO_WAIT_WHILE(aio_context, ret == -EINPROGRESS); 529 return ret; 530 } 531 532 /* Returns true on success, false on failure. */ 533 static bool nvme_identify(BlockDriverState *bs, int namespace, Error **errp) 534 { 535 BDRVNVMeState *s = bs->opaque; 536 bool ret = false; 537 QEMU_AUTO_VFREE union { 538 NvmeIdCtrl ctrl; 539 NvmeIdNs ns; 540 } *id = NULL; 541 NvmeLBAF *lbaf; 542 uint16_t oncs; 543 int r; 544 uint64_t iova; 545 NvmeCmd cmd = { 546 .opcode = NVME_ADM_CMD_IDENTIFY, 547 .cdw10 = cpu_to_le32(0x1), 548 }; 549 size_t id_size = QEMU_ALIGN_UP(sizeof(*id), qemu_real_host_page_size()); 550 551 id = qemu_try_memalign(qemu_real_host_page_size(), id_size); 552 if (!id) { 553 error_setg(errp, "Cannot allocate buffer for identify response"); 554 goto out; 555 } 556 r = qemu_vfio_dma_map(s->vfio, id, id_size, true, &iova, errp); 557 if (r) { 558 error_prepend(errp, "Cannot map buffer for DMA: "); 559 goto out; 560 } 561 562 memset(id, 0, id_size); 563 cmd.dptr.prp1 = cpu_to_le64(iova); 564 if (nvme_admin_cmd_sync(bs, &cmd)) { 565 error_setg(errp, "Failed to identify controller"); 566 goto out; 567 } 568 569 if (le32_to_cpu(id->ctrl.nn) < namespace) { 570 error_setg(errp, "Invalid namespace"); 571 goto out; 572 } 573 s->write_cache_supported = le32_to_cpu(id->ctrl.vwc) & 0x1; 574 s->max_transfer = (id->ctrl.mdts ? 1 << id->ctrl.mdts : 0) * s->page_size; 575 /* For now the page list buffer per command is one page, to hold at most 576 * s->page_size / sizeof(uint64_t) entries. */ 577 s->max_transfer = MIN_NON_ZERO(s->max_transfer, 578 s->page_size / sizeof(uint64_t) * s->page_size); 579 580 oncs = le16_to_cpu(id->ctrl.oncs); 581 s->supports_write_zeroes = !!(oncs & NVME_ONCS_WRITE_ZEROES); 582 s->supports_discard = !!(oncs & NVME_ONCS_DSM); 583 584 memset(id, 0, id_size); 585 cmd.cdw10 = 0; 586 cmd.nsid = cpu_to_le32(namespace); 587 if (nvme_admin_cmd_sync(bs, &cmd)) { 588 error_setg(errp, "Failed to identify namespace"); 589 goto out; 590 } 591 592 s->nsze = le64_to_cpu(id->ns.nsze); 593 lbaf = &id->ns.lbaf[NVME_ID_NS_FLBAS_INDEX(id->ns.flbas)]; 594 595 if (NVME_ID_NS_DLFEAT_WRITE_ZEROES(id->ns.dlfeat) && 596 NVME_ID_NS_DLFEAT_READ_BEHAVIOR(id->ns.dlfeat) == 597 NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES) { 598 bs->supported_write_flags |= BDRV_REQ_MAY_UNMAP; 599 } 600 601 if (lbaf->ms) { 602 error_setg(errp, "Namespaces with metadata are not yet supported"); 603 goto out; 604 } 605 606 if (lbaf->ds < BDRV_SECTOR_BITS || lbaf->ds > 12 || 607 (1 << lbaf->ds) > s->page_size) 608 { 609 error_setg(errp, "Namespace has unsupported block size (2^%d)", 610 lbaf->ds); 611 goto out; 612 } 613 614 ret = true; 615 s->blkshift = lbaf->ds; 616 out: 617 qemu_vfio_dma_unmap(s->vfio, id); 618 619 return ret; 620 } 621 622 static void nvme_poll_queue(NVMeQueuePair *q) 623 { 624 const size_t cqe_offset = q->cq.head * NVME_CQ_ENTRY_BYTES; 625 NvmeCqe *cqe = (NvmeCqe *)&q->cq.queue[cqe_offset]; 626 627 trace_nvme_poll_queue(q->s, q->index); 628 /* 629 * Do an early check for completions. q->lock isn't needed because 630 * nvme_process_completion() only runs in the event loop thread and 631 * cannot race with itself. 632 */ 633 if ((le16_to_cpu(cqe->status) & 0x1) == q->cq_phase) { 634 return; 635 } 636 637 qemu_mutex_lock(&q->lock); 638 while (nvme_process_completion(q)) { 639 /* Keep polling */ 640 } 641 qemu_mutex_unlock(&q->lock); 642 } 643 644 static void nvme_poll_queues(BDRVNVMeState *s) 645 { 646 int i; 647 648 for (i = 0; i < s->queue_count; i++) { 649 nvme_poll_queue(s->queues[i]); 650 } 651 } 652 653 static void nvme_handle_event(EventNotifier *n) 654 { 655 BDRVNVMeState *s = container_of(n, BDRVNVMeState, 656 irq_notifier[MSIX_SHARED_IRQ_IDX]); 657 658 trace_nvme_handle_event(s); 659 event_notifier_test_and_clear(n); 660 nvme_poll_queues(s); 661 } 662 663 static bool nvme_add_io_queue(BlockDriverState *bs, Error **errp) 664 { 665 BDRVNVMeState *s = bs->opaque; 666 unsigned n = s->queue_count; 667 NVMeQueuePair *q; 668 NvmeCmd cmd; 669 unsigned queue_size = NVME_QUEUE_SIZE; 670 671 assert(n <= UINT16_MAX); 672 q = nvme_create_queue_pair(s, bdrv_get_aio_context(bs), 673 n, queue_size, errp); 674 if (!q) { 675 return false; 676 } 677 cmd = (NvmeCmd) { 678 .opcode = NVME_ADM_CMD_CREATE_CQ, 679 .dptr.prp1 = cpu_to_le64(q->cq.iova), 680 .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n), 681 .cdw11 = cpu_to_le32(NVME_CQ_IEN | NVME_CQ_PC), 682 }; 683 if (nvme_admin_cmd_sync(bs, &cmd)) { 684 error_setg(errp, "Failed to create CQ io queue [%u]", n); 685 goto out_error; 686 } 687 cmd = (NvmeCmd) { 688 .opcode = NVME_ADM_CMD_CREATE_SQ, 689 .dptr.prp1 = cpu_to_le64(q->sq.iova), 690 .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n), 691 .cdw11 = cpu_to_le32(NVME_SQ_PC | (n << 16)), 692 }; 693 if (nvme_admin_cmd_sync(bs, &cmd)) { 694 error_setg(errp, "Failed to create SQ io queue [%u]", n); 695 goto out_error; 696 } 697 s->queues = g_renew(NVMeQueuePair *, s->queues, n + 1); 698 s->queues[n] = q; 699 s->queue_count++; 700 return true; 701 out_error: 702 nvme_free_queue_pair(q); 703 return false; 704 } 705 706 static bool nvme_poll_cb(void *opaque) 707 { 708 EventNotifier *e = opaque; 709 BDRVNVMeState *s = container_of(e, BDRVNVMeState, 710 irq_notifier[MSIX_SHARED_IRQ_IDX]); 711 int i; 712 713 for (i = 0; i < s->queue_count; i++) { 714 NVMeQueuePair *q = s->queues[i]; 715 const size_t cqe_offset = q->cq.head * NVME_CQ_ENTRY_BYTES; 716 NvmeCqe *cqe = (NvmeCqe *)&q->cq.queue[cqe_offset]; 717 718 /* 719 * q->lock isn't needed because nvme_process_completion() only runs in 720 * the event loop thread and cannot race with itself. 721 */ 722 if ((le16_to_cpu(cqe->status) & 0x1) != q->cq_phase) { 723 return true; 724 } 725 } 726 return false; 727 } 728 729 static void nvme_poll_ready(EventNotifier *e) 730 { 731 BDRVNVMeState *s = container_of(e, BDRVNVMeState, 732 irq_notifier[MSIX_SHARED_IRQ_IDX]); 733 734 nvme_poll_queues(s); 735 } 736 737 static int nvme_init(BlockDriverState *bs, const char *device, int namespace, 738 Error **errp) 739 { 740 BDRVNVMeState *s = bs->opaque; 741 NVMeQueuePair *q; 742 AioContext *aio_context = bdrv_get_aio_context(bs); 743 int ret; 744 uint64_t cap; 745 uint32_t ver; 746 uint64_t timeout_ms; 747 uint64_t deadline, now; 748 volatile NvmeBar *regs = NULL; 749 750 qemu_co_mutex_init(&s->dma_map_lock); 751 qemu_co_queue_init(&s->dma_flush_queue); 752 s->device = g_strdup(device); 753 s->nsid = namespace; 754 s->aio_context = bdrv_get_aio_context(bs); 755 ret = event_notifier_init(&s->irq_notifier[MSIX_SHARED_IRQ_IDX], 0); 756 if (ret) { 757 error_setg(errp, "Failed to init event notifier"); 758 return ret; 759 } 760 761 s->vfio = qemu_vfio_open_pci(device, errp); 762 if (!s->vfio) { 763 ret = -EINVAL; 764 goto out; 765 } 766 767 regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, sizeof(NvmeBar), 768 PROT_READ | PROT_WRITE, errp); 769 if (!regs) { 770 ret = -EINVAL; 771 goto out; 772 } 773 /* Perform initialize sequence as described in NVMe spec "7.6.1 774 * Initialization". */ 775 776 cap = le64_to_cpu(regs->cap); 777 trace_nvme_controller_capability_raw(cap); 778 trace_nvme_controller_capability("Maximum Queue Entries Supported", 779 1 + NVME_CAP_MQES(cap)); 780 trace_nvme_controller_capability("Contiguous Queues Required", 781 NVME_CAP_CQR(cap)); 782 trace_nvme_controller_capability("Doorbell Stride", 783 1 << (2 + NVME_CAP_DSTRD(cap))); 784 trace_nvme_controller_capability("Subsystem Reset Supported", 785 NVME_CAP_NSSRS(cap)); 786 trace_nvme_controller_capability("Memory Page Size Minimum", 787 1 << (12 + NVME_CAP_MPSMIN(cap))); 788 trace_nvme_controller_capability("Memory Page Size Maximum", 789 1 << (12 + NVME_CAP_MPSMAX(cap))); 790 if (!NVME_CAP_CSS(cap)) { 791 error_setg(errp, "Device doesn't support NVMe command set"); 792 ret = -EINVAL; 793 goto out; 794 } 795 796 s->page_size = 1u << (12 + NVME_CAP_MPSMIN(cap)); 797 s->doorbell_scale = (4 << NVME_CAP_DSTRD(cap)) / sizeof(uint32_t); 798 bs->bl.opt_mem_alignment = s->page_size; 799 bs->bl.request_alignment = s->page_size; 800 timeout_ms = MIN(500 * NVME_CAP_TO(cap), 30000); 801 802 ver = le32_to_cpu(regs->vs); 803 trace_nvme_controller_spec_version(extract32(ver, 16, 16), 804 extract32(ver, 8, 8), 805 extract32(ver, 0, 8)); 806 807 /* Reset device to get a clean state. */ 808 regs->cc = cpu_to_le32(le32_to_cpu(regs->cc) & 0xFE); 809 /* Wait for CSTS.RDY = 0. */ 810 deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCALE_MS; 811 while (NVME_CSTS_RDY(le32_to_cpu(regs->csts))) { 812 if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 813 error_setg(errp, "Timeout while waiting for device to reset (%" 814 PRId64 " ms)", 815 timeout_ms); 816 ret = -ETIMEDOUT; 817 goto out; 818 } 819 } 820 821 s->bar0_wo_map = qemu_vfio_pci_map_bar(s->vfio, 0, 0, 822 sizeof(NvmeBar) + NVME_DOORBELL_SIZE, 823 PROT_WRITE, errp); 824 s->doorbells = (void *)((uintptr_t)s->bar0_wo_map + sizeof(NvmeBar)); 825 if (!s->doorbells) { 826 ret = -EINVAL; 827 goto out; 828 } 829 830 /* Set up admin queue. */ 831 s->queues = g_new(NVMeQueuePair *, 1); 832 q = nvme_create_queue_pair(s, aio_context, 0, NVME_QUEUE_SIZE, errp); 833 if (!q) { 834 ret = -EINVAL; 835 goto out; 836 } 837 s->queues[INDEX_ADMIN] = q; 838 s->queue_count = 1; 839 QEMU_BUILD_BUG_ON((NVME_QUEUE_SIZE - 1) & 0xF000); 840 regs->aqa = cpu_to_le32(((NVME_QUEUE_SIZE - 1) << AQA_ACQS_SHIFT) | 841 ((NVME_QUEUE_SIZE - 1) << AQA_ASQS_SHIFT)); 842 regs->asq = cpu_to_le64(q->sq.iova); 843 regs->acq = cpu_to_le64(q->cq.iova); 844 845 /* After setting up all control registers we can enable device now. */ 846 regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << CC_IOCQES_SHIFT) | 847 (ctz32(NVME_SQ_ENTRY_BYTES) << CC_IOSQES_SHIFT) | 848 CC_EN_MASK); 849 /* Wait for CSTS.RDY = 1. */ 850 now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 851 deadline = now + timeout_ms * SCALE_MS; 852 while (!NVME_CSTS_RDY(le32_to_cpu(regs->csts))) { 853 if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 854 error_setg(errp, "Timeout while waiting for device to start (%" 855 PRId64 " ms)", 856 timeout_ms); 857 ret = -ETIMEDOUT; 858 goto out; 859 } 860 } 861 862 ret = qemu_vfio_pci_init_irq(s->vfio, s->irq_notifier, 863 VFIO_PCI_MSIX_IRQ_INDEX, errp); 864 if (ret) { 865 goto out; 866 } 867 aio_set_event_notifier(bdrv_get_aio_context(bs), 868 &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 869 nvme_handle_event, nvme_poll_cb, 870 nvme_poll_ready); 871 872 if (!nvme_identify(bs, namespace, errp)) { 873 ret = -EIO; 874 goto out; 875 } 876 877 /* Set up command queues. */ 878 if (!nvme_add_io_queue(bs, errp)) { 879 ret = -EIO; 880 } 881 out: 882 if (regs) { 883 qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)regs, 0, sizeof(NvmeBar)); 884 } 885 886 /* Cleaning up is done in nvme_file_open() upon error. */ 887 return ret; 888 } 889 890 /* Parse a filename in the format of nvme://XXXX:XX:XX.X/X. Example: 891 * 892 * nvme://0000:44:00.0/1 893 * 894 * where the "nvme://" is a fixed form of the protocol prefix, the middle part 895 * is the PCI address, and the last part is the namespace number starting from 896 * 1 according to the NVMe spec. */ 897 static void nvme_parse_filename(const char *filename, QDict *options, 898 Error **errp) 899 { 900 int pref = strlen("nvme://"); 901 902 if (strlen(filename) > pref && !strncmp(filename, "nvme://", pref)) { 903 const char *tmp = filename + pref; 904 char *device; 905 const char *namespace; 906 unsigned long ns; 907 const char *slash = strchr(tmp, '/'); 908 if (!slash) { 909 qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, tmp); 910 return; 911 } 912 device = g_strndup(tmp, slash - tmp); 913 qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, device); 914 g_free(device); 915 namespace = slash + 1; 916 if (*namespace && qemu_strtoul(namespace, NULL, 10, &ns)) { 917 error_setg(errp, "Invalid namespace '%s', positive number expected", 918 namespace); 919 return; 920 } 921 qdict_put_str(options, NVME_BLOCK_OPT_NAMESPACE, 922 *namespace ? namespace : "1"); 923 } 924 } 925 926 static int nvme_enable_disable_write_cache(BlockDriverState *bs, bool enable, 927 Error **errp) 928 { 929 int ret; 930 BDRVNVMeState *s = bs->opaque; 931 NvmeCmd cmd = { 932 .opcode = NVME_ADM_CMD_SET_FEATURES, 933 .nsid = cpu_to_le32(s->nsid), 934 .cdw10 = cpu_to_le32(0x06), 935 .cdw11 = cpu_to_le32(enable ? 0x01 : 0x00), 936 }; 937 938 ret = nvme_admin_cmd_sync(bs, &cmd); 939 if (ret) { 940 error_setg(errp, "Failed to configure NVMe write cache"); 941 } 942 return ret; 943 } 944 945 static void nvme_close(BlockDriverState *bs) 946 { 947 BDRVNVMeState *s = bs->opaque; 948 949 for (unsigned i = 0; i < s->queue_count; ++i) { 950 nvme_free_queue_pair(s->queues[i]); 951 } 952 g_free(s->queues); 953 aio_set_event_notifier(bdrv_get_aio_context(bs), 954 &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 955 NULL, NULL, NULL); 956 event_notifier_cleanup(&s->irq_notifier[MSIX_SHARED_IRQ_IDX]); 957 qemu_vfio_pci_unmap_bar(s->vfio, 0, s->bar0_wo_map, 958 0, sizeof(NvmeBar) + NVME_DOORBELL_SIZE); 959 qemu_vfio_close(s->vfio); 960 961 g_free(s->device); 962 } 963 964 static int nvme_file_open(BlockDriverState *bs, QDict *options, int flags, 965 Error **errp) 966 { 967 const char *device; 968 QemuOpts *opts; 969 int namespace; 970 int ret; 971 BDRVNVMeState *s = bs->opaque; 972 973 bs->supported_write_flags = BDRV_REQ_FUA; 974 975 opts = qemu_opts_create(&runtime_opts, NULL, 0, &error_abort); 976 qemu_opts_absorb_qdict(opts, options, &error_abort); 977 device = qemu_opt_get(opts, NVME_BLOCK_OPT_DEVICE); 978 if (!device) { 979 error_setg(errp, "'" NVME_BLOCK_OPT_DEVICE "' option is required"); 980 qemu_opts_del(opts); 981 return -EINVAL; 982 } 983 984 namespace = qemu_opt_get_number(opts, NVME_BLOCK_OPT_NAMESPACE, 1); 985 ret = nvme_init(bs, device, namespace, errp); 986 qemu_opts_del(opts); 987 if (ret) { 988 goto fail; 989 } 990 if (flags & BDRV_O_NOCACHE) { 991 if (!s->write_cache_supported) { 992 error_setg(errp, 993 "NVMe controller doesn't support write cache configuration"); 994 ret = -EINVAL; 995 } else { 996 ret = nvme_enable_disable_write_cache(bs, !(flags & BDRV_O_NOCACHE), 997 errp); 998 } 999 if (ret) { 1000 goto fail; 1001 } 1002 } 1003 return 0; 1004 fail: 1005 nvme_close(bs); 1006 return ret; 1007 } 1008 1009 static int64_t coroutine_fn nvme_co_getlength(BlockDriverState *bs) 1010 { 1011 BDRVNVMeState *s = bs->opaque; 1012 return s->nsze << s->blkshift; 1013 } 1014 1015 static uint32_t nvme_get_blocksize(BlockDriverState *bs) 1016 { 1017 BDRVNVMeState *s = bs->opaque; 1018 assert(s->blkshift >= BDRV_SECTOR_BITS && s->blkshift <= 12); 1019 return UINT32_C(1) << s->blkshift; 1020 } 1021 1022 static int nvme_probe_blocksizes(BlockDriverState *bs, BlockSizes *bsz) 1023 { 1024 uint32_t blocksize = nvme_get_blocksize(bs); 1025 bsz->phys = blocksize; 1026 bsz->log = blocksize; 1027 return 0; 1028 } 1029 1030 /* Called with s->dma_map_lock */ 1031 static coroutine_fn int nvme_cmd_unmap_qiov(BlockDriverState *bs, 1032 QEMUIOVector *qiov) 1033 { 1034 int r = 0; 1035 BDRVNVMeState *s = bs->opaque; 1036 1037 s->dma_map_count -= qiov->size; 1038 if (!s->dma_map_count && !qemu_co_queue_empty(&s->dma_flush_queue)) { 1039 r = qemu_vfio_dma_reset_temporary(s->vfio); 1040 if (!r) { 1041 qemu_co_queue_restart_all(&s->dma_flush_queue); 1042 } 1043 } 1044 return r; 1045 } 1046 1047 /* Called with s->dma_map_lock */ 1048 static coroutine_fn int nvme_cmd_map_qiov(BlockDriverState *bs, NvmeCmd *cmd, 1049 NVMeRequest *req, QEMUIOVector *qiov) 1050 { 1051 BDRVNVMeState *s = bs->opaque; 1052 uint64_t *pagelist = req->prp_list_page; 1053 int i, j, r; 1054 int entries = 0; 1055 Error *local_err = NULL, **errp = NULL; 1056 1057 assert(qiov->size); 1058 assert(QEMU_IS_ALIGNED(qiov->size, s->page_size)); 1059 assert(qiov->size / s->page_size <= s->page_size / sizeof(uint64_t)); 1060 for (i = 0; i < qiov->niov; ++i) { 1061 bool retry = true; 1062 uint64_t iova; 1063 size_t len = QEMU_ALIGN_UP(qiov->iov[i].iov_len, 1064 qemu_real_host_page_size()); 1065 try_map: 1066 r = qemu_vfio_dma_map(s->vfio, 1067 qiov->iov[i].iov_base, 1068 len, true, &iova, errp); 1069 if (r == -ENOSPC) { 1070 /* 1071 * In addition to the -ENOMEM error, the VFIO_IOMMU_MAP_DMA 1072 * ioctl returns -ENOSPC to signal the user exhausted the DMA 1073 * mappings available for a container since Linux kernel commit 1074 * 492855939bdb ("vfio/type1: Limit DMA mappings per container", 1075 * April 2019, see CVE-2019-3882). 1076 * 1077 * This block driver already handles this error path by checking 1078 * for the -ENOMEM error, so we directly replace -ENOSPC by 1079 * -ENOMEM. Beside, -ENOSPC has a specific meaning for blockdev 1080 * coroutines: it triggers BLOCKDEV_ON_ERROR_ENOSPC and 1081 * BLOCK_ERROR_ACTION_STOP which stops the VM, asking the operator 1082 * to add more storage to the blockdev. Not something we can do 1083 * easily with an IOMMU :) 1084 */ 1085 r = -ENOMEM; 1086 } 1087 if (r == -ENOMEM && retry) { 1088 /* 1089 * We exhausted the DMA mappings available for our container: 1090 * recycle the volatile IOVA mappings. 1091 */ 1092 retry = false; 1093 trace_nvme_dma_flush_queue_wait(s); 1094 if (s->dma_map_count) { 1095 trace_nvme_dma_map_flush(s); 1096 qemu_co_queue_wait(&s->dma_flush_queue, &s->dma_map_lock); 1097 } else { 1098 r = qemu_vfio_dma_reset_temporary(s->vfio); 1099 if (r) { 1100 goto fail; 1101 } 1102 } 1103 errp = &local_err; 1104 1105 goto try_map; 1106 } 1107 if (r) { 1108 goto fail; 1109 } 1110 1111 for (j = 0; j < qiov->iov[i].iov_len / s->page_size; j++) { 1112 pagelist[entries++] = cpu_to_le64(iova + j * s->page_size); 1113 } 1114 trace_nvme_cmd_map_qiov_iov(s, i, qiov->iov[i].iov_base, 1115 qiov->iov[i].iov_len / s->page_size); 1116 } 1117 1118 s->dma_map_count += qiov->size; 1119 1120 assert(entries <= s->page_size / sizeof(uint64_t)); 1121 switch (entries) { 1122 case 0: 1123 abort(); 1124 case 1: 1125 cmd->dptr.prp1 = pagelist[0]; 1126 cmd->dptr.prp2 = 0; 1127 break; 1128 case 2: 1129 cmd->dptr.prp1 = pagelist[0]; 1130 cmd->dptr.prp2 = pagelist[1]; 1131 break; 1132 default: 1133 cmd->dptr.prp1 = pagelist[0]; 1134 cmd->dptr.prp2 = cpu_to_le64(req->prp_list_iova + sizeof(uint64_t)); 1135 break; 1136 } 1137 trace_nvme_cmd_map_qiov(s, cmd, req, qiov, entries); 1138 for (i = 0; i < entries; ++i) { 1139 trace_nvme_cmd_map_qiov_pages(s, i, pagelist[i]); 1140 } 1141 return 0; 1142 fail: 1143 /* No need to unmap [0 - i) iovs even if we've failed, since we don't 1144 * increment s->dma_map_count. This is okay for fixed mapping memory areas 1145 * because they are already mapped before calling this function; for 1146 * temporary mappings, a later nvme_cmd_(un)map_qiov will reclaim by 1147 * calling qemu_vfio_dma_reset_temporary when necessary. */ 1148 if (local_err) { 1149 error_reportf_err(local_err, "Cannot map buffer for DMA: "); 1150 } 1151 return r; 1152 } 1153 1154 typedef struct { 1155 Coroutine *co; 1156 int ret; 1157 AioContext *ctx; 1158 } NVMeCoData; 1159 1160 static void nvme_rw_cb_bh(void *opaque) 1161 { 1162 NVMeCoData *data = opaque; 1163 qemu_coroutine_enter(data->co); 1164 } 1165 1166 static void nvme_rw_cb(void *opaque, int ret) 1167 { 1168 NVMeCoData *data = opaque; 1169 data->ret = ret; 1170 if (!data->co) { 1171 /* The rw coroutine hasn't yielded, don't try to enter. */ 1172 return; 1173 } 1174 replay_bh_schedule_oneshot_event(data->ctx, nvme_rw_cb_bh, data); 1175 } 1176 1177 static coroutine_fn int nvme_co_prw_aligned(BlockDriverState *bs, 1178 uint64_t offset, uint64_t bytes, 1179 QEMUIOVector *qiov, 1180 bool is_write, 1181 int flags) 1182 { 1183 int r; 1184 BDRVNVMeState *s = bs->opaque; 1185 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1186 NVMeRequest *req; 1187 1188 uint32_t cdw12 = (((bytes >> s->blkshift) - 1) & 0xFFFF) | 1189 (flags & BDRV_REQ_FUA ? 1 << 30 : 0); 1190 NvmeCmd cmd = { 1191 .opcode = is_write ? NVME_CMD_WRITE : NVME_CMD_READ, 1192 .nsid = cpu_to_le32(s->nsid), 1193 .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF), 1194 .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF), 1195 .cdw12 = cpu_to_le32(cdw12), 1196 }; 1197 NVMeCoData data = { 1198 .ctx = bdrv_get_aio_context(bs), 1199 .ret = -EINPROGRESS, 1200 }; 1201 1202 trace_nvme_prw_aligned(s, is_write, offset, bytes, flags, qiov->niov); 1203 assert(s->queue_count > 1); 1204 req = nvme_get_free_req(ioq); 1205 assert(req); 1206 1207 qemu_co_mutex_lock(&s->dma_map_lock); 1208 r = nvme_cmd_map_qiov(bs, &cmd, req, qiov); 1209 qemu_co_mutex_unlock(&s->dma_map_lock); 1210 if (r) { 1211 nvme_put_free_req_and_wake(ioq, req); 1212 return r; 1213 } 1214 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1215 1216 data.co = qemu_coroutine_self(); 1217 while (data.ret == -EINPROGRESS) { 1218 qemu_coroutine_yield(); 1219 } 1220 1221 qemu_co_mutex_lock(&s->dma_map_lock); 1222 r = nvme_cmd_unmap_qiov(bs, qiov); 1223 qemu_co_mutex_unlock(&s->dma_map_lock); 1224 if (r) { 1225 return r; 1226 } 1227 1228 trace_nvme_rw_done(s, is_write, offset, bytes, data.ret); 1229 return data.ret; 1230 } 1231 1232 static inline bool nvme_qiov_aligned(BlockDriverState *bs, 1233 const QEMUIOVector *qiov) 1234 { 1235 int i; 1236 BDRVNVMeState *s = bs->opaque; 1237 1238 for (i = 0; i < qiov->niov; ++i) { 1239 if (!QEMU_PTR_IS_ALIGNED(qiov->iov[i].iov_base, 1240 qemu_real_host_page_size()) || 1241 !QEMU_IS_ALIGNED(qiov->iov[i].iov_len, qemu_real_host_page_size())) { 1242 trace_nvme_qiov_unaligned(qiov, i, qiov->iov[i].iov_base, 1243 qiov->iov[i].iov_len, s->page_size); 1244 return false; 1245 } 1246 } 1247 return true; 1248 } 1249 1250 static coroutine_fn int nvme_co_prw(BlockDriverState *bs, 1251 uint64_t offset, uint64_t bytes, 1252 QEMUIOVector *qiov, bool is_write, 1253 int flags) 1254 { 1255 BDRVNVMeState *s = bs->opaque; 1256 int r; 1257 QEMU_AUTO_VFREE uint8_t *buf = NULL; 1258 QEMUIOVector local_qiov; 1259 size_t len = QEMU_ALIGN_UP(bytes, qemu_real_host_page_size()); 1260 assert(QEMU_IS_ALIGNED(offset, s->page_size)); 1261 assert(QEMU_IS_ALIGNED(bytes, s->page_size)); 1262 assert(bytes <= s->max_transfer); 1263 if (nvme_qiov_aligned(bs, qiov)) { 1264 s->stats.aligned_accesses++; 1265 return nvme_co_prw_aligned(bs, offset, bytes, qiov, is_write, flags); 1266 } 1267 s->stats.unaligned_accesses++; 1268 trace_nvme_prw_buffered(s, offset, bytes, qiov->niov, is_write); 1269 buf = qemu_try_memalign(qemu_real_host_page_size(), len); 1270 1271 if (!buf) { 1272 return -ENOMEM; 1273 } 1274 qemu_iovec_init(&local_qiov, 1); 1275 if (is_write) { 1276 qemu_iovec_to_buf(qiov, 0, buf, bytes); 1277 } 1278 qemu_iovec_add(&local_qiov, buf, bytes); 1279 r = nvme_co_prw_aligned(bs, offset, bytes, &local_qiov, is_write, flags); 1280 qemu_iovec_destroy(&local_qiov); 1281 if (!r && !is_write) { 1282 qemu_iovec_from_buf(qiov, 0, buf, bytes); 1283 } 1284 return r; 1285 } 1286 1287 static coroutine_fn int nvme_co_preadv(BlockDriverState *bs, 1288 int64_t offset, int64_t bytes, 1289 QEMUIOVector *qiov, 1290 BdrvRequestFlags flags) 1291 { 1292 return nvme_co_prw(bs, offset, bytes, qiov, false, flags); 1293 } 1294 1295 static coroutine_fn int nvme_co_pwritev(BlockDriverState *bs, 1296 int64_t offset, int64_t bytes, 1297 QEMUIOVector *qiov, 1298 BdrvRequestFlags flags) 1299 { 1300 return nvme_co_prw(bs, offset, bytes, qiov, true, flags); 1301 } 1302 1303 static coroutine_fn int nvme_co_flush(BlockDriverState *bs) 1304 { 1305 BDRVNVMeState *s = bs->opaque; 1306 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1307 NVMeRequest *req; 1308 NvmeCmd cmd = { 1309 .opcode = NVME_CMD_FLUSH, 1310 .nsid = cpu_to_le32(s->nsid), 1311 }; 1312 NVMeCoData data = { 1313 .ctx = bdrv_get_aio_context(bs), 1314 .ret = -EINPROGRESS, 1315 }; 1316 1317 assert(s->queue_count > 1); 1318 req = nvme_get_free_req(ioq); 1319 assert(req); 1320 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1321 1322 data.co = qemu_coroutine_self(); 1323 if (data.ret == -EINPROGRESS) { 1324 qemu_coroutine_yield(); 1325 } 1326 1327 return data.ret; 1328 } 1329 1330 1331 static coroutine_fn int nvme_co_pwrite_zeroes(BlockDriverState *bs, 1332 int64_t offset, 1333 int64_t bytes, 1334 BdrvRequestFlags flags) 1335 { 1336 BDRVNVMeState *s = bs->opaque; 1337 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1338 NVMeRequest *req; 1339 uint32_t cdw12; 1340 1341 if (!s->supports_write_zeroes) { 1342 return -ENOTSUP; 1343 } 1344 1345 if (bytes == 0) { 1346 return 0; 1347 } 1348 1349 cdw12 = ((bytes >> s->blkshift) - 1) & 0xFFFF; 1350 /* 1351 * We should not lose information. pwrite_zeroes_alignment and 1352 * max_pwrite_zeroes guarantees it. 1353 */ 1354 assert(((cdw12 + 1) << s->blkshift) == bytes); 1355 1356 NvmeCmd cmd = { 1357 .opcode = NVME_CMD_WRITE_ZEROES, 1358 .nsid = cpu_to_le32(s->nsid), 1359 .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF), 1360 .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF), 1361 }; 1362 1363 NVMeCoData data = { 1364 .ctx = bdrv_get_aio_context(bs), 1365 .ret = -EINPROGRESS, 1366 }; 1367 1368 if (flags & BDRV_REQ_MAY_UNMAP) { 1369 cdw12 |= (1 << 25); 1370 } 1371 1372 if (flags & BDRV_REQ_FUA) { 1373 cdw12 |= (1 << 30); 1374 } 1375 1376 cmd.cdw12 = cpu_to_le32(cdw12); 1377 1378 trace_nvme_write_zeroes(s, offset, bytes, flags); 1379 assert(s->queue_count > 1); 1380 req = nvme_get_free_req(ioq); 1381 assert(req); 1382 1383 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1384 1385 data.co = qemu_coroutine_self(); 1386 while (data.ret == -EINPROGRESS) { 1387 qemu_coroutine_yield(); 1388 } 1389 1390 trace_nvme_rw_done(s, true, offset, bytes, data.ret); 1391 return data.ret; 1392 } 1393 1394 1395 static int coroutine_fn nvme_co_pdiscard(BlockDriverState *bs, 1396 int64_t offset, 1397 int64_t bytes) 1398 { 1399 BDRVNVMeState *s = bs->opaque; 1400 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1401 NVMeRequest *req; 1402 QEMU_AUTO_VFREE NvmeDsmRange *buf = NULL; 1403 QEMUIOVector local_qiov; 1404 int ret; 1405 1406 NvmeCmd cmd = { 1407 .opcode = NVME_CMD_DSM, 1408 .nsid = cpu_to_le32(s->nsid), 1409 .cdw10 = cpu_to_le32(0), /*number of ranges - 0 based*/ 1410 .cdw11 = cpu_to_le32(1 << 2), /*deallocate bit*/ 1411 }; 1412 1413 NVMeCoData data = { 1414 .ctx = bdrv_get_aio_context(bs), 1415 .ret = -EINPROGRESS, 1416 }; 1417 1418 if (!s->supports_discard) { 1419 return -ENOTSUP; 1420 } 1421 1422 assert(s->queue_count > 1); 1423 1424 /* 1425 * Filling the @buf requires @offset and @bytes to satisfy restrictions 1426 * defined in nvme_refresh_limits(). 1427 */ 1428 assert(QEMU_IS_ALIGNED(bytes, 1UL << s->blkshift)); 1429 assert(QEMU_IS_ALIGNED(offset, 1UL << s->blkshift)); 1430 assert((bytes >> s->blkshift) <= UINT32_MAX); 1431 1432 buf = qemu_try_memalign(s->page_size, s->page_size); 1433 if (!buf) { 1434 return -ENOMEM; 1435 } 1436 memset(buf, 0, s->page_size); 1437 buf->nlb = cpu_to_le32(bytes >> s->blkshift); 1438 buf->slba = cpu_to_le64(offset >> s->blkshift); 1439 buf->cattr = 0; 1440 1441 qemu_iovec_init(&local_qiov, 1); 1442 qemu_iovec_add(&local_qiov, buf, 4096); 1443 1444 req = nvme_get_free_req(ioq); 1445 assert(req); 1446 1447 qemu_co_mutex_lock(&s->dma_map_lock); 1448 ret = nvme_cmd_map_qiov(bs, &cmd, req, &local_qiov); 1449 qemu_co_mutex_unlock(&s->dma_map_lock); 1450 1451 if (ret) { 1452 nvme_put_free_req_and_wake(ioq, req); 1453 goto out; 1454 } 1455 1456 trace_nvme_dsm(s, offset, bytes); 1457 1458 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1459 1460 data.co = qemu_coroutine_self(); 1461 while (data.ret == -EINPROGRESS) { 1462 qemu_coroutine_yield(); 1463 } 1464 1465 qemu_co_mutex_lock(&s->dma_map_lock); 1466 ret = nvme_cmd_unmap_qiov(bs, &local_qiov); 1467 qemu_co_mutex_unlock(&s->dma_map_lock); 1468 1469 if (ret) { 1470 goto out; 1471 } 1472 1473 ret = data.ret; 1474 trace_nvme_dsm_done(s, offset, bytes, ret); 1475 out: 1476 qemu_iovec_destroy(&local_qiov); 1477 return ret; 1478 1479 } 1480 1481 static int coroutine_fn nvme_co_truncate(BlockDriverState *bs, int64_t offset, 1482 bool exact, PreallocMode prealloc, 1483 BdrvRequestFlags flags, Error **errp) 1484 { 1485 int64_t cur_length; 1486 1487 if (prealloc != PREALLOC_MODE_OFF) { 1488 error_setg(errp, "Unsupported preallocation mode '%s'", 1489 PreallocMode_str(prealloc)); 1490 return -ENOTSUP; 1491 } 1492 1493 cur_length = nvme_co_getlength(bs); 1494 if (offset != cur_length && exact) { 1495 error_setg(errp, "Cannot resize NVMe devices"); 1496 return -ENOTSUP; 1497 } else if (offset > cur_length) { 1498 error_setg(errp, "Cannot grow NVMe devices"); 1499 return -EINVAL; 1500 } 1501 1502 return 0; 1503 } 1504 1505 static int nvme_reopen_prepare(BDRVReopenState *reopen_state, 1506 BlockReopenQueue *queue, Error **errp) 1507 { 1508 return 0; 1509 } 1510 1511 static void nvme_refresh_filename(BlockDriverState *bs) 1512 { 1513 BDRVNVMeState *s = bs->opaque; 1514 1515 snprintf(bs->exact_filename, sizeof(bs->exact_filename), "nvme://%s/%i", 1516 s->device, s->nsid); 1517 } 1518 1519 static void nvme_refresh_limits(BlockDriverState *bs, Error **errp) 1520 { 1521 BDRVNVMeState *s = bs->opaque; 1522 1523 bs->bl.opt_mem_alignment = s->page_size; 1524 bs->bl.request_alignment = s->page_size; 1525 bs->bl.max_transfer = s->max_transfer; 1526 1527 /* 1528 * Look at nvme_co_pwrite_zeroes: after shift and decrement we should get 1529 * at most 0xFFFF 1530 */ 1531 bs->bl.max_pwrite_zeroes = 1ULL << (s->blkshift + 16); 1532 bs->bl.pwrite_zeroes_alignment = MAX(bs->bl.request_alignment, 1533 1UL << s->blkshift); 1534 1535 bs->bl.max_pdiscard = (uint64_t)UINT32_MAX << s->blkshift; 1536 bs->bl.pdiscard_alignment = MAX(bs->bl.request_alignment, 1537 1UL << s->blkshift); 1538 } 1539 1540 static void nvme_detach_aio_context(BlockDriverState *bs) 1541 { 1542 BDRVNVMeState *s = bs->opaque; 1543 1544 for (unsigned i = 0; i < s->queue_count; i++) { 1545 NVMeQueuePair *q = s->queues[i]; 1546 1547 qemu_bh_delete(q->completion_bh); 1548 q->completion_bh = NULL; 1549 } 1550 1551 aio_set_event_notifier(bdrv_get_aio_context(bs), 1552 &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 1553 NULL, NULL, NULL); 1554 } 1555 1556 static void nvme_attach_aio_context(BlockDriverState *bs, 1557 AioContext *new_context) 1558 { 1559 BDRVNVMeState *s = bs->opaque; 1560 1561 s->aio_context = new_context; 1562 aio_set_event_notifier(new_context, &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 1563 nvme_handle_event, nvme_poll_cb, 1564 nvme_poll_ready); 1565 1566 for (unsigned i = 0; i < s->queue_count; i++) { 1567 NVMeQueuePair *q = s->queues[i]; 1568 1569 q->completion_bh = 1570 aio_bh_new(new_context, nvme_process_completion_bh, q); 1571 } 1572 } 1573 1574 static bool nvme_register_buf(BlockDriverState *bs, void *host, size_t size, 1575 Error **errp) 1576 { 1577 int ret; 1578 BDRVNVMeState *s = bs->opaque; 1579 1580 /* 1581 * FIXME: we may run out of IOVA addresses after repeated 1582 * bdrv_register_buf/bdrv_unregister_buf, because nvme_vfio_dma_unmap 1583 * doesn't reclaim addresses for fixed mappings. 1584 */ 1585 ret = qemu_vfio_dma_map(s->vfio, host, size, false, NULL, errp); 1586 return ret == 0; 1587 } 1588 1589 static void nvme_unregister_buf(BlockDriverState *bs, void *host, size_t size) 1590 { 1591 BDRVNVMeState *s = bs->opaque; 1592 1593 qemu_vfio_dma_unmap(s->vfio, host); 1594 } 1595 1596 static BlockStatsSpecific *nvme_get_specific_stats(BlockDriverState *bs) 1597 { 1598 BlockStatsSpecific *stats = g_new(BlockStatsSpecific, 1); 1599 BDRVNVMeState *s = bs->opaque; 1600 1601 stats->driver = BLOCKDEV_DRIVER_NVME; 1602 stats->u.nvme = (BlockStatsSpecificNvme) { 1603 .completion_errors = s->stats.completion_errors, 1604 .aligned_accesses = s->stats.aligned_accesses, 1605 .unaligned_accesses = s->stats.unaligned_accesses, 1606 }; 1607 1608 return stats; 1609 } 1610 1611 static const char *const nvme_strong_runtime_opts[] = { 1612 NVME_BLOCK_OPT_DEVICE, 1613 NVME_BLOCK_OPT_NAMESPACE, 1614 1615 NULL 1616 }; 1617 1618 static BlockDriver bdrv_nvme = { 1619 .format_name = "nvme", 1620 .protocol_name = "nvme", 1621 .instance_size = sizeof(BDRVNVMeState), 1622 1623 .bdrv_co_create_opts = bdrv_co_create_opts_simple, 1624 .create_opts = &bdrv_create_opts_simple, 1625 1626 .bdrv_parse_filename = nvme_parse_filename, 1627 .bdrv_file_open = nvme_file_open, 1628 .bdrv_close = nvme_close, 1629 .bdrv_co_getlength = nvme_co_getlength, 1630 .bdrv_probe_blocksizes = nvme_probe_blocksizes, 1631 .bdrv_co_truncate = nvme_co_truncate, 1632 1633 .bdrv_co_preadv = nvme_co_preadv, 1634 .bdrv_co_pwritev = nvme_co_pwritev, 1635 1636 .bdrv_co_pwrite_zeroes = nvme_co_pwrite_zeroes, 1637 .bdrv_co_pdiscard = nvme_co_pdiscard, 1638 1639 .bdrv_co_flush_to_disk = nvme_co_flush, 1640 .bdrv_reopen_prepare = nvme_reopen_prepare, 1641 1642 .bdrv_refresh_filename = nvme_refresh_filename, 1643 .bdrv_refresh_limits = nvme_refresh_limits, 1644 .strong_runtime_opts = nvme_strong_runtime_opts, 1645 .bdrv_get_specific_stats = nvme_get_specific_stats, 1646 1647 .bdrv_detach_aio_context = nvme_detach_aio_context, 1648 .bdrv_attach_aio_context = nvme_attach_aio_context, 1649 1650 .bdrv_register_buf = nvme_register_buf, 1651 .bdrv_unregister_buf = nvme_unregister_buf, 1652 }; 1653 1654 static void bdrv_nvme_init(void) 1655 { 1656 bdrv_register(&bdrv_nvme); 1657 } 1658 1659 block_init(bdrv_nvme_init); 1660