1d52c454aSMarc-André Lureau /*
2d52c454aSMarc-André Lureau * Virtio vhost-user GPU Device
3d52c454aSMarc-André Lureau *
4d52c454aSMarc-André Lureau * Copyright Red Hat, Inc. 2013-2018
5d52c454aSMarc-André Lureau *
6d52c454aSMarc-André Lureau * Authors:
7d52c454aSMarc-André Lureau * Dave Airlie <airlied@redhat.com>
8d52c454aSMarc-André Lureau * Gerd Hoffmann <kraxel@redhat.com>
9d52c454aSMarc-André Lureau * Marc-André Lureau <marcandre.lureau@redhat.com>
10d52c454aSMarc-André Lureau *
11d52c454aSMarc-André Lureau * This work is licensed under the terms of the GNU GPL, version 2 or later.
12d52c454aSMarc-André Lureau * See the COPYING file in the top-level directory.
13d52c454aSMarc-André Lureau */
14d52c454aSMarc-André Lureau
154bd802b2SMarkus Armbruster #include "qemu/osdep.h"
16d52c454aSMarc-André Lureau #include <virglrenderer.h>
17d52c454aSMarc-André Lureau #include "virgl.h"
18d52c454aSMarc-André Lureau
190c27b9c5SMarc-André Lureau #include <epoxy/gl.h>
200c27b9c5SMarc-André Lureau
21d52c454aSMarc-André Lureau void
vg_virgl_update_cursor_data(VuGpu * g,uint32_t resource_id,gpointer data)22d52c454aSMarc-André Lureau vg_virgl_update_cursor_data(VuGpu *g, uint32_t resource_id,
23d52c454aSMarc-André Lureau gpointer data)
24d52c454aSMarc-André Lureau {
25d52c454aSMarc-André Lureau uint32_t width, height;
26d52c454aSMarc-André Lureau uint32_t *cursor;
27d52c454aSMarc-André Lureau
28d52c454aSMarc-André Lureau cursor = virgl_renderer_get_cursor_data(resource_id, &width, &height);
29d52c454aSMarc-André Lureau g_return_if_fail(cursor != NULL);
30d52c454aSMarc-André Lureau g_return_if_fail(width == 64);
31d52c454aSMarc-André Lureau g_return_if_fail(height == 64);
32d52c454aSMarc-André Lureau
33d52c454aSMarc-André Lureau memcpy(data, cursor, 64 * 64 * sizeof(uint32_t));
34d52c454aSMarc-André Lureau free(cursor);
35d52c454aSMarc-André Lureau }
36d52c454aSMarc-André Lureau
37d52c454aSMarc-André Lureau static void
virgl_cmd_context_create(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)38d52c454aSMarc-André Lureau virgl_cmd_context_create(VuGpu *g,
39d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
40d52c454aSMarc-André Lureau {
41d52c454aSMarc-André Lureau struct virtio_gpu_ctx_create cc;
42d52c454aSMarc-André Lureau
43d52c454aSMarc-André Lureau VUGPU_FILL_CMD(cc);
44d52c454aSMarc-André Lureau
45d52c454aSMarc-André Lureau virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen,
46d52c454aSMarc-André Lureau cc.debug_name);
47d52c454aSMarc-André Lureau }
48d52c454aSMarc-André Lureau
49d52c454aSMarc-André Lureau static void
virgl_cmd_context_destroy(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)50d52c454aSMarc-André Lureau virgl_cmd_context_destroy(VuGpu *g,
51d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
52d52c454aSMarc-André Lureau {
53d52c454aSMarc-André Lureau struct virtio_gpu_ctx_destroy cd;
54d52c454aSMarc-André Lureau
55d52c454aSMarc-André Lureau VUGPU_FILL_CMD(cd);
56d52c454aSMarc-André Lureau
57d52c454aSMarc-André Lureau virgl_renderer_context_destroy(cd.hdr.ctx_id);
58d52c454aSMarc-André Lureau }
59d52c454aSMarc-André Lureau
60d52c454aSMarc-André Lureau static void
virgl_cmd_create_resource_2d(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)61d52c454aSMarc-André Lureau virgl_cmd_create_resource_2d(VuGpu *g,
62d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
63d52c454aSMarc-André Lureau {
64d52c454aSMarc-André Lureau struct virtio_gpu_resource_create_2d c2d;
65d52c454aSMarc-André Lureau struct virgl_renderer_resource_create_args args;
66d52c454aSMarc-André Lureau
67d52c454aSMarc-André Lureau VUGPU_FILL_CMD(c2d);
68d52c454aSMarc-André Lureau
69d52c454aSMarc-André Lureau args.handle = c2d.resource_id;
70d52c454aSMarc-André Lureau args.target = 2;
71d52c454aSMarc-André Lureau args.format = c2d.format;
72d52c454aSMarc-André Lureau args.bind = (1 << 1);
73d52c454aSMarc-André Lureau args.width = c2d.width;
74d52c454aSMarc-André Lureau args.height = c2d.height;
75d52c454aSMarc-André Lureau args.depth = 1;
76d52c454aSMarc-André Lureau args.array_size = 1;
77d52c454aSMarc-André Lureau args.last_level = 0;
78d52c454aSMarc-André Lureau args.nr_samples = 0;
79d52c454aSMarc-André Lureau args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP;
80d52c454aSMarc-André Lureau virgl_renderer_resource_create(&args, NULL, 0);
81d52c454aSMarc-André Lureau }
82d52c454aSMarc-André Lureau
83d52c454aSMarc-André Lureau static void
virgl_cmd_create_resource_3d(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)84d52c454aSMarc-André Lureau virgl_cmd_create_resource_3d(VuGpu *g,
85d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
86d52c454aSMarc-André Lureau {
87d52c454aSMarc-André Lureau struct virtio_gpu_resource_create_3d c3d;
88d52c454aSMarc-André Lureau struct virgl_renderer_resource_create_args args;
89d52c454aSMarc-André Lureau
90d52c454aSMarc-André Lureau VUGPU_FILL_CMD(c3d);
91d52c454aSMarc-André Lureau
92d52c454aSMarc-André Lureau args.handle = c3d.resource_id;
93d52c454aSMarc-André Lureau args.target = c3d.target;
94d52c454aSMarc-André Lureau args.format = c3d.format;
95d52c454aSMarc-André Lureau args.bind = c3d.bind;
96d52c454aSMarc-André Lureau args.width = c3d.width;
97d52c454aSMarc-André Lureau args.height = c3d.height;
98d52c454aSMarc-André Lureau args.depth = c3d.depth;
99d52c454aSMarc-André Lureau args.array_size = c3d.array_size;
100d52c454aSMarc-André Lureau args.last_level = c3d.last_level;
101d52c454aSMarc-André Lureau args.nr_samples = c3d.nr_samples;
102d52c454aSMarc-André Lureau args.flags = c3d.flags;
103d52c454aSMarc-André Lureau virgl_renderer_resource_create(&args, NULL, 0);
104d52c454aSMarc-André Lureau }
105d52c454aSMarc-André Lureau
106d52c454aSMarc-André Lureau static void
virgl_cmd_resource_unref(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)107d52c454aSMarc-André Lureau virgl_cmd_resource_unref(VuGpu *g,
108d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
109d52c454aSMarc-André Lureau {
110d52c454aSMarc-André Lureau struct virtio_gpu_resource_unref unref;
111f6091d86SLi Qiang struct iovec *res_iovs = NULL;
112f6091d86SLi Qiang int num_iovs = 0;
113d52c454aSMarc-André Lureau
114d52c454aSMarc-André Lureau VUGPU_FILL_CMD(unref);
115d52c454aSMarc-André Lureau
116f6091d86SLi Qiang virgl_renderer_resource_detach_iov(unref.resource_id,
117f6091d86SLi Qiang &res_iovs,
118f6091d86SLi Qiang &num_iovs);
1193ea32d13SLi Qiang if (res_iovs != NULL && num_iovs != 0) {
1203ea32d13SLi Qiang vg_cleanup_mapping_iov(g, res_iovs, num_iovs);
1213ea32d13SLi Qiang }
122d52c454aSMarc-André Lureau virgl_renderer_resource_unref(unref.resource_id);
123d52c454aSMarc-André Lureau }
124d52c454aSMarc-André Lureau
125d52c454aSMarc-André Lureau /* Not yet(?) defined in standard-headers, remove when possible */
126d52c454aSMarc-André Lureau #ifndef VIRTIO_GPU_CAPSET_VIRGL2
127d52c454aSMarc-André Lureau #define VIRTIO_GPU_CAPSET_VIRGL2 2
128d52c454aSMarc-André Lureau #endif
129d52c454aSMarc-André Lureau
130d52c454aSMarc-André Lureau static void
virgl_cmd_get_capset_info(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)131d52c454aSMarc-André Lureau virgl_cmd_get_capset_info(VuGpu *g,
132d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
133d52c454aSMarc-André Lureau {
134d52c454aSMarc-André Lureau struct virtio_gpu_get_capset_info info;
135d52c454aSMarc-André Lureau struct virtio_gpu_resp_capset_info resp;
136d52c454aSMarc-André Lureau
137d52c454aSMarc-André Lureau VUGPU_FILL_CMD(info);
138d52c454aSMarc-André Lureau
139121841b2SLi Qiang memset(&resp, 0, sizeof(resp));
140d52c454aSMarc-André Lureau if (info.capset_index == 0) {
141d52c454aSMarc-André Lureau resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL;
142d52c454aSMarc-André Lureau virgl_renderer_get_cap_set(resp.capset_id,
143d52c454aSMarc-André Lureau &resp.capset_max_version,
144d52c454aSMarc-André Lureau &resp.capset_max_size);
145d52c454aSMarc-André Lureau } else if (info.capset_index == 1) {
146d52c454aSMarc-André Lureau resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL2;
147d52c454aSMarc-André Lureau virgl_renderer_get_cap_set(resp.capset_id,
148d52c454aSMarc-André Lureau &resp.capset_max_version,
149d52c454aSMarc-André Lureau &resp.capset_max_size);
150d52c454aSMarc-André Lureau } else {
151d52c454aSMarc-André Lureau resp.capset_max_version = 0;
152d52c454aSMarc-André Lureau resp.capset_max_size = 0;
153d52c454aSMarc-André Lureau }
154d52c454aSMarc-André Lureau resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO;
155d52c454aSMarc-André Lureau vg_ctrl_response(g, cmd, &resp.hdr, sizeof(resp));
156d52c454aSMarc-André Lureau }
157d52c454aSMarc-André Lureau
158d52c454aSMarc-André Lureau uint32_t
vg_virgl_get_num_capsets(void)159d52c454aSMarc-André Lureau vg_virgl_get_num_capsets(void)
160d52c454aSMarc-André Lureau {
161d52c454aSMarc-André Lureau uint32_t capset2_max_ver, capset2_max_size;
162d52c454aSMarc-André Lureau virgl_renderer_get_cap_set(VIRTIO_GPU_CAPSET_VIRGL2,
163d52c454aSMarc-André Lureau &capset2_max_ver,
164d52c454aSMarc-André Lureau &capset2_max_size);
165d52c454aSMarc-André Lureau
166d52c454aSMarc-André Lureau return capset2_max_ver ? 2 : 1;
167d52c454aSMarc-André Lureau }
168d52c454aSMarc-André Lureau
169d52c454aSMarc-André Lureau static void
virgl_cmd_get_capset(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)170d52c454aSMarc-André Lureau virgl_cmd_get_capset(VuGpu *g,
171d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
172d52c454aSMarc-André Lureau {
173d52c454aSMarc-André Lureau struct virtio_gpu_get_capset gc;
174d52c454aSMarc-André Lureau struct virtio_gpu_resp_capset *resp;
175d52c454aSMarc-André Lureau uint32_t max_ver, max_size;
176d52c454aSMarc-André Lureau
177d52c454aSMarc-André Lureau VUGPU_FILL_CMD(gc);
178d52c454aSMarc-André Lureau
179d52c454aSMarc-André Lureau virgl_renderer_get_cap_set(gc.capset_id, &max_ver,
180d52c454aSMarc-André Lureau &max_size);
1819f22893aSLi Qiang if (!max_size) {
1829f22893aSLi Qiang cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
1839f22893aSLi Qiang return;
1849f22893aSLi Qiang }
185d52c454aSMarc-André Lureau resp = g_malloc0(sizeof(*resp) + max_size);
186d52c454aSMarc-André Lureau
187d52c454aSMarc-André Lureau resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET;
188d52c454aSMarc-André Lureau virgl_renderer_fill_caps(gc.capset_id,
189d52c454aSMarc-André Lureau gc.capset_version,
190d52c454aSMarc-André Lureau (void *)resp->capset_data);
191d52c454aSMarc-André Lureau vg_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size);
192d52c454aSMarc-André Lureau g_free(resp);
193d52c454aSMarc-André Lureau }
194d52c454aSMarc-André Lureau
195d52c454aSMarc-André Lureau static void
virgl_cmd_submit_3d(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)196d52c454aSMarc-André Lureau virgl_cmd_submit_3d(VuGpu *g,
197d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
198d52c454aSMarc-André Lureau {
199d52c454aSMarc-André Lureau struct virtio_gpu_cmd_submit cs;
200d52c454aSMarc-André Lureau void *buf;
201d52c454aSMarc-André Lureau size_t s;
202d52c454aSMarc-André Lureau
203d52c454aSMarc-André Lureau VUGPU_FILL_CMD(cs);
204d52c454aSMarc-André Lureau
205d52c454aSMarc-André Lureau buf = g_malloc(cs.size);
206d52c454aSMarc-André Lureau s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
207d52c454aSMarc-André Lureau sizeof(cs), buf, cs.size);
208d52c454aSMarc-André Lureau if (s != cs.size) {
209d52c454aSMarc-André Lureau g_critical("%s: size mismatch (%zd/%d)", __func__, s, cs.size);
210d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
211d52c454aSMarc-André Lureau goto out;
212d52c454aSMarc-André Lureau }
213d52c454aSMarc-André Lureau
214d52c454aSMarc-André Lureau virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4);
215d52c454aSMarc-André Lureau
216d52c454aSMarc-André Lureau out:
217d52c454aSMarc-André Lureau g_free(buf);
218d52c454aSMarc-André Lureau }
219d52c454aSMarc-André Lureau
220d52c454aSMarc-André Lureau static void
virgl_cmd_transfer_to_host_2d(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)221d52c454aSMarc-André Lureau virgl_cmd_transfer_to_host_2d(VuGpu *g,
222d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
223d52c454aSMarc-André Lureau {
224d52c454aSMarc-André Lureau struct virtio_gpu_transfer_to_host_2d t2d;
225d52c454aSMarc-André Lureau struct virtio_gpu_box box;
226d52c454aSMarc-André Lureau
227d52c454aSMarc-André Lureau VUGPU_FILL_CMD(t2d);
228d52c454aSMarc-André Lureau
229d52c454aSMarc-André Lureau box.x = t2d.r.x;
230d52c454aSMarc-André Lureau box.y = t2d.r.y;
231d52c454aSMarc-André Lureau box.z = 0;
232d52c454aSMarc-André Lureau box.w = t2d.r.width;
233d52c454aSMarc-André Lureau box.h = t2d.r.height;
234d52c454aSMarc-André Lureau box.d = 1;
235d52c454aSMarc-André Lureau
236d52c454aSMarc-André Lureau virgl_renderer_transfer_write_iov(t2d.resource_id,
237d52c454aSMarc-André Lureau 0,
238d52c454aSMarc-André Lureau 0,
239d52c454aSMarc-André Lureau 0,
240d52c454aSMarc-André Lureau 0,
241d52c454aSMarc-André Lureau (struct virgl_box *)&box,
242d52c454aSMarc-André Lureau t2d.offset, NULL, 0);
243d52c454aSMarc-André Lureau }
244d52c454aSMarc-André Lureau
245d52c454aSMarc-André Lureau static void
virgl_cmd_transfer_to_host_3d(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)246d52c454aSMarc-André Lureau virgl_cmd_transfer_to_host_3d(VuGpu *g,
247d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
248d52c454aSMarc-André Lureau {
249d52c454aSMarc-André Lureau struct virtio_gpu_transfer_host_3d t3d;
250d52c454aSMarc-André Lureau
251d52c454aSMarc-André Lureau VUGPU_FILL_CMD(t3d);
252d52c454aSMarc-André Lureau
253d52c454aSMarc-André Lureau virgl_renderer_transfer_write_iov(t3d.resource_id,
254d52c454aSMarc-André Lureau t3d.hdr.ctx_id,
255d52c454aSMarc-André Lureau t3d.level,
256d52c454aSMarc-André Lureau t3d.stride,
257d52c454aSMarc-André Lureau t3d.layer_stride,
258d52c454aSMarc-André Lureau (struct virgl_box *)&t3d.box,
259d52c454aSMarc-André Lureau t3d.offset, NULL, 0);
260d52c454aSMarc-André Lureau }
261d52c454aSMarc-André Lureau
262d52c454aSMarc-André Lureau static void
virgl_cmd_transfer_from_host_3d(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)263d52c454aSMarc-André Lureau virgl_cmd_transfer_from_host_3d(VuGpu *g,
264d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
265d52c454aSMarc-André Lureau {
266d52c454aSMarc-André Lureau struct virtio_gpu_transfer_host_3d tf3d;
267d52c454aSMarc-André Lureau
268d52c454aSMarc-André Lureau VUGPU_FILL_CMD(tf3d);
269d52c454aSMarc-André Lureau
270d52c454aSMarc-André Lureau virgl_renderer_transfer_read_iov(tf3d.resource_id,
271d52c454aSMarc-André Lureau tf3d.hdr.ctx_id,
272d52c454aSMarc-André Lureau tf3d.level,
273d52c454aSMarc-André Lureau tf3d.stride,
274d52c454aSMarc-André Lureau tf3d.layer_stride,
275d52c454aSMarc-André Lureau (struct virgl_box *)&tf3d.box,
276d52c454aSMarc-André Lureau tf3d.offset, NULL, 0);
277d52c454aSMarc-André Lureau }
278d52c454aSMarc-André Lureau
279d52c454aSMarc-André Lureau static void
virgl_resource_attach_backing(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)280d52c454aSMarc-André Lureau virgl_resource_attach_backing(VuGpu *g,
281d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
282d52c454aSMarc-André Lureau {
283d52c454aSMarc-André Lureau struct virtio_gpu_resource_attach_backing att_rb;
284d52c454aSMarc-André Lureau struct iovec *res_iovs;
285d52c454aSMarc-André Lureau int ret;
286d52c454aSMarc-André Lureau
287d52c454aSMarc-André Lureau VUGPU_FILL_CMD(att_rb);
288d52c454aSMarc-André Lureau
289d52c454aSMarc-André Lureau ret = vg_create_mapping_iov(g, &att_rb, cmd, &res_iovs);
290d52c454aSMarc-André Lureau if (ret != 0) {
291d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
292d52c454aSMarc-André Lureau return;
293d52c454aSMarc-André Lureau }
294d52c454aSMarc-André Lureau
29563736af5SLi Qiang ret = virgl_renderer_resource_attach_iov(att_rb.resource_id,
296d52c454aSMarc-André Lureau res_iovs, att_rb.nr_entries);
29763736af5SLi Qiang if (ret != 0) {
2983ea32d13SLi Qiang vg_cleanup_mapping_iov(g, res_iovs, att_rb.nr_entries);
29963736af5SLi Qiang }
300d52c454aSMarc-André Lureau }
301d52c454aSMarc-André Lureau
302d52c454aSMarc-André Lureau static void
virgl_resource_detach_backing(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)303d52c454aSMarc-André Lureau virgl_resource_detach_backing(VuGpu *g,
304d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
305d52c454aSMarc-André Lureau {
306d52c454aSMarc-André Lureau struct virtio_gpu_resource_detach_backing detach_rb;
307d52c454aSMarc-André Lureau struct iovec *res_iovs = NULL;
308d52c454aSMarc-André Lureau int num_iovs = 0;
309d52c454aSMarc-André Lureau
310d52c454aSMarc-André Lureau VUGPU_FILL_CMD(detach_rb);
311d52c454aSMarc-André Lureau
312d52c454aSMarc-André Lureau virgl_renderer_resource_detach_iov(detach_rb.resource_id,
313d52c454aSMarc-André Lureau &res_iovs,
314d52c454aSMarc-André Lureau &num_iovs);
315d52c454aSMarc-André Lureau if (res_iovs == NULL || num_iovs == 0) {
316d52c454aSMarc-André Lureau return;
317d52c454aSMarc-André Lureau }
3183ea32d13SLi Qiang vg_cleanup_mapping_iov(g, res_iovs, num_iovs);
319d52c454aSMarc-André Lureau }
320d52c454aSMarc-André Lureau
321e3c82fe0SErico Nunes static int
virgl_get_resource_info_modifiers(uint32_t resource_id,struct virgl_renderer_resource_info * info,uint64_t * modifiers)322e3c82fe0SErico Nunes virgl_get_resource_info_modifiers(uint32_t resource_id,
323e3c82fe0SErico Nunes struct virgl_renderer_resource_info *info,
324e3c82fe0SErico Nunes uint64_t *modifiers)
325e3c82fe0SErico Nunes {
326e3c82fe0SErico Nunes int ret;
327e3c82fe0SErico Nunes #ifdef VIRGL_RENDERER_RESOURCE_INFO_EXT_VERSION
328e3c82fe0SErico Nunes struct virgl_renderer_resource_info_ext info_ext;
329e3c82fe0SErico Nunes ret = virgl_renderer_resource_get_info_ext(resource_id, &info_ext);
330*574b64aaSDmitry Osipenko if (ret) {
331e3c82fe0SErico Nunes return ret;
332e3c82fe0SErico Nunes }
333e3c82fe0SErico Nunes
334e3c82fe0SErico Nunes *info = info_ext.base;
335e3c82fe0SErico Nunes *modifiers = info_ext.modifiers;
336e3c82fe0SErico Nunes #else
337e3c82fe0SErico Nunes ret = virgl_renderer_resource_get_info(resource_id, info);
338*574b64aaSDmitry Osipenko if (ret) {
339e3c82fe0SErico Nunes return ret;
340e3c82fe0SErico Nunes }
341e3c82fe0SErico Nunes
342e3c82fe0SErico Nunes /*
343e3c82fe0SErico Nunes * Before virgl_renderer_resource_get_info_ext,
344e3c82fe0SErico Nunes * getting the modifiers was not possible.
345e3c82fe0SErico Nunes */
346e3c82fe0SErico Nunes *modifiers = 0;
347e3c82fe0SErico Nunes #endif
348e3c82fe0SErico Nunes
349e3c82fe0SErico Nunes return 0;
350e3c82fe0SErico Nunes }
351e3c82fe0SErico Nunes
352d52c454aSMarc-André Lureau static void
virgl_cmd_set_scanout(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)353d52c454aSMarc-André Lureau virgl_cmd_set_scanout(VuGpu *g,
354d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
355d52c454aSMarc-André Lureau {
356d52c454aSMarc-André Lureau struct virtio_gpu_set_scanout ss;
357d52c454aSMarc-André Lureau struct virgl_renderer_resource_info info;
358d52c454aSMarc-André Lureau int ret;
359d52c454aSMarc-André Lureau
360d52c454aSMarc-André Lureau VUGPU_FILL_CMD(ss);
361d52c454aSMarc-André Lureau
362d52c454aSMarc-André Lureau if (ss.scanout_id >= VIRTIO_GPU_MAX_SCANOUTS) {
363d52c454aSMarc-André Lureau g_critical("%s: illegal scanout id specified %d",
364d52c454aSMarc-André Lureau __func__, ss.scanout_id);
365d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
366d52c454aSMarc-André Lureau return;
367d52c454aSMarc-André Lureau }
368d52c454aSMarc-André Lureau
369d52c454aSMarc-André Lureau memset(&info, 0, sizeof(info));
370d52c454aSMarc-André Lureau
371d52c454aSMarc-André Lureau if (ss.resource_id && ss.r.width && ss.r.height) {
372e3c82fe0SErico Nunes uint64_t modifiers = 0;
373e3c82fe0SErico Nunes ret = virgl_get_resource_info_modifiers(ss.resource_id, &info,
374e3c82fe0SErico Nunes &modifiers);
375*574b64aaSDmitry Osipenko if (ret) {
376d52c454aSMarc-André Lureau g_critical("%s: illegal resource specified %d\n",
377d52c454aSMarc-André Lureau __func__, ss.resource_id);
378d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
379d52c454aSMarc-André Lureau return;
380d52c454aSMarc-André Lureau }
381d52c454aSMarc-André Lureau
382d52c454aSMarc-André Lureau int fd = -1;
383d52c454aSMarc-André Lureau if (virgl_renderer_get_fd_for_texture(info.tex_id, &fd) < 0) {
384d52c454aSMarc-André Lureau g_critical("%s: failed to get fd for texture\n", __func__);
385d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID;
386d52c454aSMarc-André Lureau return;
387d52c454aSMarc-André Lureau }
388d52c454aSMarc-André Lureau assert(fd >= 0);
389d52c454aSMarc-André Lureau VhostUserGpuMsg msg = {
390d52c454aSMarc-André Lureau .payload.dmabuf_scanout.scanout_id = ss.scanout_id,
391d52c454aSMarc-André Lureau .payload.dmabuf_scanout.x = ss.r.x,
392d52c454aSMarc-André Lureau .payload.dmabuf_scanout.y = ss.r.y,
393d52c454aSMarc-André Lureau .payload.dmabuf_scanout.width = ss.r.width,
394d52c454aSMarc-André Lureau .payload.dmabuf_scanout.height = ss.r.height,
395d52c454aSMarc-André Lureau .payload.dmabuf_scanout.fd_width = info.width,
396d52c454aSMarc-André Lureau .payload.dmabuf_scanout.fd_height = info.height,
397d52c454aSMarc-André Lureau .payload.dmabuf_scanout.fd_stride = info.stride,
398d52c454aSMarc-André Lureau .payload.dmabuf_scanout.fd_flags = info.flags,
399d52c454aSMarc-André Lureau .payload.dmabuf_scanout.fd_drm_fourcc = info.drm_fourcc
400d52c454aSMarc-André Lureau };
401e3c82fe0SErico Nunes
402e3c82fe0SErico Nunes if (g->use_modifiers) {
403e3c82fe0SErico Nunes /*
4041a9c9a6fSMichael Tokarev * The message uses all the fields set in dmabuf_scanout plus
405e3c82fe0SErico Nunes * modifiers which is appended after VhostUserGpuDMABUFScanout.
406e3c82fe0SErico Nunes */
407e3c82fe0SErico Nunes msg.request = VHOST_USER_GPU_DMABUF_SCANOUT2;
408e3c82fe0SErico Nunes msg.size = sizeof(VhostUserGpuDMABUFScanout2);
409e3c82fe0SErico Nunes msg.payload.dmabuf_scanout2.modifier = modifiers;
410e3c82fe0SErico Nunes } else {
411e3c82fe0SErico Nunes msg.request = VHOST_USER_GPU_DMABUF_SCANOUT;
412e3c82fe0SErico Nunes msg.size = sizeof(VhostUserGpuDMABUFScanout);
413e3c82fe0SErico Nunes }
414e3c82fe0SErico Nunes
415d52c454aSMarc-André Lureau vg_send_msg(g, &msg, fd);
416d52c454aSMarc-André Lureau close(fd);
417d52c454aSMarc-André Lureau } else {
418d52c454aSMarc-André Lureau VhostUserGpuMsg msg = {
419d52c454aSMarc-André Lureau .request = VHOST_USER_GPU_DMABUF_SCANOUT,
420d52c454aSMarc-André Lureau .size = sizeof(VhostUserGpuDMABUFScanout),
421d52c454aSMarc-André Lureau .payload.dmabuf_scanout.scanout_id = ss.scanout_id,
422d52c454aSMarc-André Lureau };
423d52c454aSMarc-André Lureau g_debug("disable scanout");
424d52c454aSMarc-André Lureau vg_send_msg(g, &msg, -1);
425d52c454aSMarc-André Lureau }
426d52c454aSMarc-André Lureau g->scanout[ss.scanout_id].resource_id = ss.resource_id;
427d52c454aSMarc-André Lureau }
428d52c454aSMarc-André Lureau
429d52c454aSMarc-André Lureau static void
virgl_cmd_resource_flush(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)430d52c454aSMarc-André Lureau virgl_cmd_resource_flush(VuGpu *g,
431d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
432d52c454aSMarc-André Lureau {
433d52c454aSMarc-André Lureau struct virtio_gpu_resource_flush rf;
434d52c454aSMarc-André Lureau int i;
435d52c454aSMarc-André Lureau
436d52c454aSMarc-André Lureau VUGPU_FILL_CMD(rf);
437d52c454aSMarc-André Lureau
4380c27b9c5SMarc-André Lureau glFlush();
439d52c454aSMarc-André Lureau if (!rf.resource_id) {
440d52c454aSMarc-André Lureau g_debug("bad resource id for flush..?");
441d52c454aSMarc-André Lureau return;
442d52c454aSMarc-André Lureau }
443d52c454aSMarc-André Lureau for (i = 0; i < VIRTIO_GPU_MAX_SCANOUTS; i++) {
444d52c454aSMarc-André Lureau if (g->scanout[i].resource_id != rf.resource_id) {
445d52c454aSMarc-André Lureau continue;
446d52c454aSMarc-André Lureau }
447d52c454aSMarc-André Lureau VhostUserGpuMsg msg = {
448d52c454aSMarc-André Lureau .request = VHOST_USER_GPU_DMABUF_UPDATE,
449d52c454aSMarc-André Lureau .size = sizeof(VhostUserGpuUpdate),
450d52c454aSMarc-André Lureau .payload.update.scanout_id = i,
451d52c454aSMarc-André Lureau .payload.update.x = rf.r.x,
452d52c454aSMarc-André Lureau .payload.update.y = rf.r.y,
453d52c454aSMarc-André Lureau .payload.update.width = rf.r.width,
454d52c454aSMarc-André Lureau .payload.update.height = rf.r.height
455d52c454aSMarc-André Lureau };
456d52c454aSMarc-André Lureau vg_send_msg(g, &msg, -1);
457d52c454aSMarc-André Lureau vg_wait_ok(g);
458d52c454aSMarc-André Lureau }
459d52c454aSMarc-André Lureau }
460d52c454aSMarc-André Lureau
461d52c454aSMarc-André Lureau static void
virgl_cmd_ctx_attach_resource(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)462d52c454aSMarc-André Lureau virgl_cmd_ctx_attach_resource(VuGpu *g,
463d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
464d52c454aSMarc-André Lureau {
465d52c454aSMarc-André Lureau struct virtio_gpu_ctx_resource att_res;
466d52c454aSMarc-André Lureau
467d52c454aSMarc-André Lureau VUGPU_FILL_CMD(att_res);
468d52c454aSMarc-André Lureau
469d52c454aSMarc-André Lureau virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id);
470d52c454aSMarc-André Lureau }
471d52c454aSMarc-André Lureau
472d52c454aSMarc-André Lureau static void
virgl_cmd_ctx_detach_resource(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)473d52c454aSMarc-André Lureau virgl_cmd_ctx_detach_resource(VuGpu *g,
474d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd)
475d52c454aSMarc-André Lureau {
476d52c454aSMarc-André Lureau struct virtio_gpu_ctx_resource det_res;
477d52c454aSMarc-André Lureau
478d52c454aSMarc-André Lureau VUGPU_FILL_CMD(det_res);
479d52c454aSMarc-André Lureau
480d52c454aSMarc-André Lureau virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id);
481d52c454aSMarc-André Lureau }
482d52c454aSMarc-André Lureau
vg_virgl_process_cmd(VuGpu * g,struct virtio_gpu_ctrl_command * cmd)483d52c454aSMarc-André Lureau void vg_virgl_process_cmd(VuGpu *g, struct virtio_gpu_ctrl_command *cmd)
484d52c454aSMarc-André Lureau {
485d52c454aSMarc-André Lureau virgl_renderer_force_ctx_0();
486d52c454aSMarc-André Lureau switch (cmd->cmd_hdr.type) {
487d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_CTX_CREATE:
488d52c454aSMarc-André Lureau virgl_cmd_context_create(g, cmd);
489d52c454aSMarc-André Lureau break;
490d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_CTX_DESTROY:
491d52c454aSMarc-André Lureau virgl_cmd_context_destroy(g, cmd);
492d52c454aSMarc-André Lureau break;
493d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D:
494d52c454aSMarc-André Lureau virgl_cmd_create_resource_2d(g, cmd);
495d52c454aSMarc-André Lureau break;
496d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D:
497d52c454aSMarc-André Lureau virgl_cmd_create_resource_3d(g, cmd);
498d52c454aSMarc-André Lureau break;
499d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_SUBMIT_3D:
500d52c454aSMarc-André Lureau virgl_cmd_submit_3d(g, cmd);
501d52c454aSMarc-André Lureau break;
502d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D:
503d52c454aSMarc-André Lureau virgl_cmd_transfer_to_host_2d(g, cmd);
504d52c454aSMarc-André Lureau break;
505d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D:
506d52c454aSMarc-André Lureau virgl_cmd_transfer_to_host_3d(g, cmd);
507d52c454aSMarc-André Lureau break;
508d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D:
509d52c454aSMarc-André Lureau virgl_cmd_transfer_from_host_3d(g, cmd);
510d52c454aSMarc-André Lureau break;
511d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING:
512d52c454aSMarc-André Lureau virgl_resource_attach_backing(g, cmd);
513d52c454aSMarc-André Lureau break;
514d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING:
515d52c454aSMarc-André Lureau virgl_resource_detach_backing(g, cmd);
516d52c454aSMarc-André Lureau break;
517d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_SET_SCANOUT:
518d52c454aSMarc-André Lureau virgl_cmd_set_scanout(g, cmd);
519d52c454aSMarc-André Lureau break;
520d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_FLUSH:
521d52c454aSMarc-André Lureau virgl_cmd_resource_flush(g, cmd);
522d52c454aSMarc-André Lureau break;
523d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_RESOURCE_UNREF:
524d52c454aSMarc-André Lureau virgl_cmd_resource_unref(g, cmd);
525d52c454aSMarc-André Lureau break;
526d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE:
527d52c454aSMarc-André Lureau /* TODO add security */
528d52c454aSMarc-André Lureau virgl_cmd_ctx_attach_resource(g, cmd);
529d52c454aSMarc-André Lureau break;
530d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE:
531d52c454aSMarc-André Lureau /* TODO add security */
532d52c454aSMarc-André Lureau virgl_cmd_ctx_detach_resource(g, cmd);
533d52c454aSMarc-André Lureau break;
534d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_GET_CAPSET_INFO:
535d52c454aSMarc-André Lureau virgl_cmd_get_capset_info(g, cmd);
536d52c454aSMarc-André Lureau break;
537d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_GET_CAPSET:
538d52c454aSMarc-André Lureau virgl_cmd_get_capset(g, cmd);
539d52c454aSMarc-André Lureau break;
540d52c454aSMarc-André Lureau case VIRTIO_GPU_CMD_GET_DISPLAY_INFO:
541d52c454aSMarc-André Lureau vg_get_display_info(g, cmd);
542d52c454aSMarc-André Lureau break;
543c0644426SErico Nunes case VIRTIO_GPU_CMD_GET_EDID:
544c0644426SErico Nunes vg_get_edid(g, cmd);
545c0644426SErico Nunes break;
546d52c454aSMarc-André Lureau default:
547d52c454aSMarc-André Lureau g_debug("TODO handle ctrl %x\n", cmd->cmd_hdr.type);
548d52c454aSMarc-André Lureau cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
549d52c454aSMarc-André Lureau break;
550d52c454aSMarc-André Lureau }
551d52c454aSMarc-André Lureau
55272e631c6SMarc-André Lureau if (cmd->state != VG_CMD_STATE_NEW) {
553d52c454aSMarc-André Lureau return;
554d52c454aSMarc-André Lureau }
555d52c454aSMarc-André Lureau
556d52c454aSMarc-André Lureau if (cmd->error) {
557d52c454aSMarc-André Lureau g_warning("%s: ctrl 0x%x, error 0x%x\n", __func__,
558d52c454aSMarc-André Lureau cmd->cmd_hdr.type, cmd->error);
559d52c454aSMarc-André Lureau vg_ctrl_response_nodata(g, cmd, cmd->error);
560d52c454aSMarc-André Lureau return;
561d52c454aSMarc-André Lureau }
562d52c454aSMarc-André Lureau
563d52c454aSMarc-André Lureau if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) {
564d52c454aSMarc-André Lureau vg_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
565d52c454aSMarc-André Lureau return;
566d52c454aSMarc-André Lureau }
567d52c454aSMarc-André Lureau
568d52c454aSMarc-André Lureau g_debug("Creating fence id:%" PRId64 " type:%d",
569d52c454aSMarc-André Lureau cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
570d52c454aSMarc-André Lureau virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type);
571d52c454aSMarc-André Lureau }
572d52c454aSMarc-André Lureau
573d52c454aSMarc-André Lureau static void
virgl_write_fence(void * opaque,uint32_t fence)574d52c454aSMarc-André Lureau virgl_write_fence(void *opaque, uint32_t fence)
575d52c454aSMarc-André Lureau {
576d52c454aSMarc-André Lureau VuGpu *g = opaque;
577d52c454aSMarc-André Lureau struct virtio_gpu_ctrl_command *cmd, *tmp;
578d52c454aSMarc-André Lureau
579d52c454aSMarc-André Lureau QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) {
580d52c454aSMarc-André Lureau /*
581d52c454aSMarc-André Lureau * the guest can end up emitting fences out of order
582d52c454aSMarc-André Lureau * so we should check all fenced cmds not just the first one.
583d52c454aSMarc-André Lureau */
584d52c454aSMarc-André Lureau if (cmd->cmd_hdr.fence_id > fence) {
585d52c454aSMarc-André Lureau continue;
586d52c454aSMarc-André Lureau }
587d52c454aSMarc-André Lureau g_debug("FENCE %" PRIu64, cmd->cmd_hdr.fence_id);
588d52c454aSMarc-André Lureau vg_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA);
589d52c454aSMarc-André Lureau QTAILQ_REMOVE(&g->fenceq, cmd, next);
5904ff97121SPhilippe Mathieu-Daudé free(cmd);
591d52c454aSMarc-André Lureau g->inflight--;
592d52c454aSMarc-André Lureau }
593d52c454aSMarc-André Lureau }
594d52c454aSMarc-André Lureau
595d52c454aSMarc-André Lureau #if defined(VIRGL_RENDERER_CALLBACKS_VERSION) && \
596d52c454aSMarc-André Lureau VIRGL_RENDERER_CALLBACKS_VERSION >= 2
597d52c454aSMarc-André Lureau static int
virgl_get_drm_fd(void * opaque)598d52c454aSMarc-André Lureau virgl_get_drm_fd(void *opaque)
599d52c454aSMarc-André Lureau {
600d52c454aSMarc-André Lureau VuGpu *g = opaque;
601d52c454aSMarc-André Lureau
602d52c454aSMarc-André Lureau return g->drm_rnode_fd;
603d52c454aSMarc-André Lureau }
604d52c454aSMarc-André Lureau #endif
605d52c454aSMarc-André Lureau
606d52c454aSMarc-André Lureau static struct virgl_renderer_callbacks virgl_cbs = {
607d52c454aSMarc-André Lureau #if defined(VIRGL_RENDERER_CALLBACKS_VERSION) && \
608d52c454aSMarc-André Lureau VIRGL_RENDERER_CALLBACKS_VERSION >= 2
609d52c454aSMarc-André Lureau .get_drm_fd = virgl_get_drm_fd,
610d52c454aSMarc-André Lureau .version = 2,
611d52c454aSMarc-André Lureau #else
612d52c454aSMarc-André Lureau .version = 1,
613d52c454aSMarc-André Lureau #endif
614d52c454aSMarc-André Lureau .write_fence = virgl_write_fence,
615d52c454aSMarc-André Lureau };
616d52c454aSMarc-André Lureau
617d52c454aSMarc-André Lureau static void
vg_virgl_poll(VuDev * dev,int condition,void * data)618d52c454aSMarc-André Lureau vg_virgl_poll(VuDev *dev, int condition, void *data)
619d52c454aSMarc-André Lureau {
620d52c454aSMarc-André Lureau virgl_renderer_poll();
621d52c454aSMarc-André Lureau }
622d52c454aSMarc-André Lureau
623d52c454aSMarc-André Lureau bool
vg_virgl_init(VuGpu * g)624d52c454aSMarc-André Lureau vg_virgl_init(VuGpu *g)
625d52c454aSMarc-André Lureau {
626d52c454aSMarc-André Lureau int ret;
627d52c454aSMarc-André Lureau
628d52c454aSMarc-André Lureau if (g->drm_rnode_fd && virgl_cbs.version == 1) {
629d52c454aSMarc-André Lureau g_warning("virgl will use the default rendernode");
630d52c454aSMarc-André Lureau }
631d52c454aSMarc-André Lureau
632d52c454aSMarc-André Lureau ret = virgl_renderer_init(g,
633d52c454aSMarc-André Lureau VIRGL_RENDERER_USE_EGL |
634d52c454aSMarc-André Lureau VIRGL_RENDERER_THREAD_SYNC,
635d52c454aSMarc-André Lureau &virgl_cbs);
636d52c454aSMarc-André Lureau if (ret != 0) {
637d52c454aSMarc-André Lureau return false;
638d52c454aSMarc-André Lureau }
639d52c454aSMarc-André Lureau
640d52c454aSMarc-André Lureau ret = virgl_renderer_get_poll_fd();
641d52c454aSMarc-André Lureau if (ret != -1) {
642d52c454aSMarc-André Lureau g->renderer_source =
643d52c454aSMarc-André Lureau vug_source_new(&g->dev, ret, G_IO_IN, vg_virgl_poll, g);
644d52c454aSMarc-André Lureau }
645d52c454aSMarc-André Lureau
646d52c454aSMarc-André Lureau return true;
647d52c454aSMarc-André Lureau }
648